blob: f405e051e3559060a1e93640417c01a49093bdc7 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
|
//==- X86MnemonicTables.cpp - Generate mnemonic extraction tables. -*- C++ -*-//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This tablegen backend is responsible for emitting tables that group
// instructions by their mnemonic name wrt AsmWriter Variant (e.g. isADD, etc).
//
//===----------------------------------------------------------------------===//
#include "CodeGenInstruction.h"
#include "CodeGenTarget.h"
#include "X86RecognizableInstr.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/TableGenBackend.h"
using namespace llvm;
namespace {
class X86MnemonicTablesEmitter {
CodeGenTarget Target;
public:
X86MnemonicTablesEmitter(RecordKeeper &R) : Target(R) {}
// Output X86 mnemonic tables.
void run(raw_ostream &OS);
};
void X86MnemonicTablesEmitter::run(raw_ostream &OS) {
emitSourceFileHeader("X86 Mnemonic tables", OS);
OS << "namespace llvm {\nnamespace X86 {\n\n";
Record *AsmWriter = Target.getAsmWriter();
unsigned Variant = AsmWriter->getValueAsInt("Variant");
// Hold all instructions grouped by mnemonic
StringMap<SmallVector<const CodeGenInstruction *, 0>> MnemonicToCGInstrMap;
ArrayRef<const CodeGenInstruction *> NumberedInstructions =
Target.getInstructionsByEnumValue();
for (const CodeGenInstruction *I : NumberedInstructions) {
const Record *Def = I->TheDef;
// Filter non-X86 instructions.
if (!Def->isSubClassOf("X86Inst"))
continue;
X86Disassembler::RecognizableInstrBase RI(*I);
if (!RI.shouldBeEmitted())
continue;
if ( // Non-parsable instruction defs contain prefix as part of AsmString
Def->getValueAsString("AsmVariantName") == "NonParsable" ||
// Skip prefix byte
RI.Form == X86Local::PrefixByte)
continue;
std::string Mnemonic = X86Disassembler::getMnemonic(I, Variant);
MnemonicToCGInstrMap[Mnemonic].push_back(I);
}
OS << "#ifdef GET_X86_MNEMONIC_TABLES_H\n";
OS << "#undef GET_X86_MNEMONIC_TABLES_H\n\n";
for (StringRef Mnemonic : MnemonicToCGInstrMap.keys())
OS << "bool is" << Mnemonic << "(unsigned Opcode);\n";
OS << "#endif // GET_X86_MNEMONIC_TABLES_H\n\n";
OS << "#ifdef GET_X86_MNEMONIC_TABLES_CPP\n";
OS << "#undef GET_X86_MNEMONIC_TABLES_CPP\n\n";
for (StringRef Mnemonic : MnemonicToCGInstrMap.keys()) {
OS << "bool is" << Mnemonic << "(unsigned Opcode) {\n";
auto Mnemonics = MnemonicToCGInstrMap[Mnemonic];
if (Mnemonics.size() == 1) {
const CodeGenInstruction *CGI = *Mnemonics.begin();
OS << "\treturn Opcode == " << CGI->TheDef->getName() << ";\n}\n\n";
} else {
OS << "\tswitch (Opcode) {\n";
for (const CodeGenInstruction *CGI : Mnemonics) {
OS << "\tcase " << CGI->TheDef->getName() << ":\n";
}
OS << "\t\treturn true;\n\t}\n\treturn false;\n}\n\n";
}
}
OS << "#endif // GET_X86_MNEMONIC_TABLES_CPP\n\n";
OS << "} // end namespace X86\n} // end namespace llvm";
}
} // namespace
namespace llvm {
void EmitX86MnemonicTables(RecordKeeper &RK, raw_ostream &OS) {
X86MnemonicTablesEmitter(RK).run(OS);
}
} // namespace llvm
|
