blob: ef4a82e0f6c8037629aeab1347706e36034441d7 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
|
#pragma once
#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wunused-parameter"
#endif
//===--------------------- Pipeline.h ---------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
/// \file
///
/// This file implements an ordered container of stages that simulate the
/// pipeline of a hardware backend.
///
//===----------------------------------------------------------------------===//
#ifndef LLVM_MCA_PIPELINE_H
#define LLVM_MCA_PIPELINE_H
#include "llvm/MCA/Stages/Stage.h"
#include "llvm/Support/Error.h"
namespace llvm {
namespace mca {
class HWEventListener;
/// A pipeline for a specific subtarget.
///
/// It emulates an out-of-order execution of instructions. Instructions are
/// fetched from a MCInst sequence managed by an initial 'Fetch' stage.
/// Instructions are firstly fetched, then dispatched to the schedulers, and
/// then executed.
///
/// This class tracks the lifetime of an instruction from the moment where
/// it gets dispatched to the schedulers, to the moment where it finishes
/// executing and register writes are architecturally committed.
/// In particular, it monitors changes in the state of every instruction
/// in flight.
///
/// Instructions are executed in a loop of iterations. The number of iterations
/// is defined by the SourceMgr object, which is managed by the initial stage
/// of the instruction pipeline.
///
/// The Pipeline entry point is method 'run()' which executes cycles in a loop
/// until there are new instructions to dispatch, and not every instruction
/// has been retired.
///
/// Internally, the Pipeline collects statistical information in the form of
/// histograms. For example, it tracks how the dispatch group size changes
/// over time.
class Pipeline {
Pipeline(const Pipeline &P) = delete;
Pipeline &operator=(const Pipeline &P) = delete;
/// An ordered list of stages that define this instruction pipeline.
SmallVector<std::unique_ptr<Stage>, 8> Stages;
std::set<HWEventListener *> Listeners;
unsigned Cycles;
Error runCycle();
bool hasWorkToProcess();
void notifyCycleBegin();
void notifyCycleEnd();
public:
Pipeline() : Cycles(0) {}
void appendStage(std::unique_ptr<Stage> S);
/// Returns the total number of simulated cycles.
Expected<unsigned> run();
void addEventListener(HWEventListener *Listener);
};
} // namespace mca
} // namespace llvm
#endif // LLVM_MCA_PIPELINE_H
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif
|
