blob: d6860adebd7262d6a96f4338ef49e7558a4d9c9b (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
|
#pragma once
#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wunused-parameter"
#endif
//===- RegisterClassInfo.h - Dynamic Register Class Info --------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file implements the RegisterClassInfo class which provides dynamic
// information about target register classes. Callee saved and reserved
// registers depends on calling conventions and other dynamic information, so
// some things cannot be determined statically.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
#define LLVM_CODEGEN_REGISTERCLASSINFO_H
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <memory>
namespace llvm {
class RegisterClassInfo {
struct RCInfo {
unsigned Tag = 0;
unsigned NumRegs = 0;
bool ProperSubClass = false;
uint8_t MinCost = 0;
uint16_t LastCostChange = 0;
std::unique_ptr<MCPhysReg[]> Order;
RCInfo() = default;
operator ArrayRef<MCPhysReg>() const {
return makeArrayRef(Order.get(), NumRegs);
}
};
// Brief cached information for each register class.
std::unique_ptr<RCInfo[]> RegClass;
// Tag changes whenever cached information needs to be recomputed. An RCInfo
// entry is valid when its tag matches.
unsigned Tag = 0;
const MachineFunction *MF = nullptr;
const TargetRegisterInfo *TRI = nullptr;
// Callee saved registers of last MF. Assumed to be valid until the next
// runOnFunction() call.
// Used only to determine if an update was made to CalleeSavedAliases.
const MCPhysReg *CalleeSavedRegs = nullptr;
// Map register alias to the callee saved Register.
SmallVector<MCPhysReg, 4> CalleeSavedAliases;
// Reserved registers in the current MF.
BitVector Reserved;
std::unique_ptr<unsigned[]> PSetLimits;
// The register cost values.
ArrayRef<uint8_t> RegCosts;
// Compute all information about RC.
void compute(const TargetRegisterClass *RC) const;
// Return an up-to-date RCInfo for RC.
const RCInfo &get(const TargetRegisterClass *RC) const {
const RCInfo &RCI = RegClass[RC->getID()];
if (Tag != RCI.Tag)
compute(RC);
return RCI;
}
public:
RegisterClassInfo();
/// runOnFunction - Prepare to answer questions about MF. This must be called
/// before any other methods are used.
void runOnMachineFunction(const MachineFunction &MF);
/// getNumAllocatableRegs - Returns the number of actually allocatable
/// registers in RC in the current function.
unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
return get(RC).NumRegs;
}
/// getOrder - Returns the preferred allocation order for RC. The order
/// contains no reserved registers, and registers that alias callee saved
/// registers come last.
ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
return get(RC);
}
/// isProperSubClass - Returns true if RC has a legal super-class with more
/// allocatable registers.
///
/// Register classes like GR32_NOSP are not proper sub-classes because %esp
/// is not allocatable. Similarly, tGPR is not a proper sub-class in Thumb
/// mode because the GPR super-class is not legal.
bool isProperSubClass(const TargetRegisterClass *RC) const {
return get(RC).ProperSubClass;
}
/// getLastCalleeSavedAlias - Returns the last callee saved register that
/// overlaps PhysReg, or NoRegister if Reg doesn't overlap a
/// CalleeSavedAliases.
MCRegister getLastCalleeSavedAlias(MCRegister PhysReg) const {
if (PhysReg.id() < CalleeSavedAliases.size())
return CalleeSavedAliases[PhysReg];
return MCRegister::NoRegister;
}
/// Get the minimum register cost in RC's allocation order.
/// This is the smallest value in RegCosts[Reg] for all
/// the registers in getOrder(RC).
uint8_t getMinCost(const TargetRegisterClass *RC) const {
return get(RC).MinCost;
}
/// Get the position of the last cost change in getOrder(RC).
///
/// All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the
/// same cost according to RegCosts[Reg].
unsigned getLastCostChange(const TargetRegisterClass *RC) const {
return get(RC).LastCostChange;
}
/// Get the register unit limit for the given pressure set index.
///
/// RegisterClassInfo adjusts this limit for reserved registers.
unsigned getRegPressureSetLimit(unsigned Idx) const {
if (!PSetLimits[Idx])
PSetLimits[Idx] = computePSetLimit(Idx);
return PSetLimits[Idx];
}
protected:
unsigned computePSetLimit(unsigned Idx) const;
};
} // end namespace llvm
#endif // LLVM_CODEGEN_REGISTERCLASSINFO_H
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif
|
