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author | shmel1k <shmel1k@ydb.tech> | 2023-11-26 18:16:14 +0300 |
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committer | shmel1k <shmel1k@ydb.tech> | 2023-11-26 18:43:30 +0300 |
commit | b8cf9e88f4c5c64d9406af533d8948deb050d695 (patch) | |
tree | 218eb61fb3c3b96ec08b4d8cdfef383104a87d63 /contrib/python/Twisted/py2/twisted/conch/mixin.py | |
parent | 523f645a83a0ec97a0332dbc3863bb354c92a328 (diff) | |
download | ydb-b8cf9e88f4c5c64d9406af533d8948deb050d695.tar.gz |
add kikimr_configure
Diffstat (limited to 'contrib/python/Twisted/py2/twisted/conch/mixin.py')
-rw-r--r-- | contrib/python/Twisted/py2/twisted/conch/mixin.py | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/contrib/python/Twisted/py2/twisted/conch/mixin.py b/contrib/python/Twisted/py2/twisted/conch/mixin.py new file mode 100644 index 0000000000..976e9ad18f --- /dev/null +++ b/contrib/python/Twisted/py2/twisted/conch/mixin.py @@ -0,0 +1,55 @@ +# -*- test-case-name: twisted.conch.test.test_mixin -*- +# Copyright (c) Twisted Matrix Laboratories. +# See LICENSE for details. + +""" +Experimental optimization + +This module provides a single mixin class which allows protocols to +collapse numerous small writes into a single larger one. + +@author: Jp Calderone +""" + +from twisted.internet import reactor + +class BufferingMixin: + """ + Mixin which adds write buffering. + """ + _delayedWriteCall = None + data = None + + DELAY = 0.0 + + def schedule(self): + return reactor.callLater(self.DELAY, self.flush) + + + def reschedule(self, token): + token.reset(self.DELAY) + + + def write(self, data): + """ + Buffer some bytes to be written soon. + + Every call to this function delays the real write by C{self.DELAY} + seconds. When the delay expires, all collected bytes are written + to the underlying transport using L{ITransport.writeSequence}. + """ + if self._delayedWriteCall is None: + self.data = [] + self._delayedWriteCall = self.schedule() + else: + self.reschedule(self._delayedWriteCall) + self.data.append(data) + + + def flush(self): + """ + Flush the buffer immediately. + """ + self._delayedWriteCall = None + self.transport.writeSequence(self.data) + self.data = None |