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author | orivej <orivej@yandex-team.ru> | 2022-02-10 16:44:49 +0300 |
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committer | Daniil Cherednik <dcherednik@yandex-team.ru> | 2022-02-10 16:44:49 +0300 |
commit | 718c552901d703c502ccbefdfc3c9028d608b947 (patch) | |
tree | 46534a98bbefcd7b1f3faa5b52c138ab27db75b7 /contrib/python/Pygments/py3/pygments/lexers/hdl.py | |
parent | e9656aae26e0358d5378e5b63dcac5c8dbe0e4d0 (diff) | |
download | ydb-718c552901d703c502ccbefdfc3c9028d608b947.tar.gz |
Restoring authorship annotation for <orivej@yandex-team.ru>. Commit 1 of 2.
Diffstat (limited to 'contrib/python/Pygments/py3/pygments/lexers/hdl.py')
-rw-r--r-- | contrib/python/Pygments/py3/pygments/lexers/hdl.py | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/contrib/python/Pygments/py3/pygments/lexers/hdl.py b/contrib/python/Pygments/py3/pygments/lexers/hdl.py index e96f79a475c..ddaf5d43222 100644 --- a/contrib/python/Pygments/py3/pygments/lexers/hdl.py +++ b/contrib/python/Pygments/py3/pygments/lexers/hdl.py @@ -105,8 +105,8 @@ class VerilogLexer(RegexLexer): 'trior', 'tri0', 'tri1', 'trireg', 'uwire', 'wire', 'wand', 'wor' 'shortreal', 'real', 'realtime'), suffix=r'\b'), Keyword.Type), - (r'[a-zA-Z_]\w*:(?!:)', Name.Label), - (r'\$?[a-zA-Z_]\w*', Name), + (r'[a-zA-Z_]\w*:(?!:)', Name.Label), + (r'\$?[a-zA-Z_]\w*', Name), (r'\\(\S+)', Name), ], 'string': [ @@ -345,8 +345,8 @@ class SystemVerilogLexer(RegexLexer): ), suffix=r'\b'), Name.Builtin), - (r'[a-zA-Z_]\w*:(?!:)', Name.Label), - (r'\$?[a-zA-Z_]\w*', Name), + (r'[a-zA-Z_]\w*:(?!:)', Name.Label), + (r'\$?[a-zA-Z_]\w*', Name), (r'\\(\S+)', Name), ], 'string': [ @@ -391,26 +391,26 @@ class VhdlLexer(RegexLexer): (r'[~!%^&*+=|?:<>/-]', Operator), (r"'[a-z_]\w*", Name.Attribute), (r'[()\[\],.;\']', Punctuation), - (r'"[^\n\\"]*"', String), + (r'"[^\n\\"]*"', String), (r'(library)(\s+)([a-z_]\w*)', bygroups(Keyword, Whitespace, Name.Namespace)), (r'(use)(\s+)(entity)', bygroups(Keyword, Whitespace, Keyword)), - (r'(use)(\s+)([a-z_][\w.]*\.)(all)', + (r'(use)(\s+)([a-z_][\w.]*\.)(all)', bygroups(Keyword, Whitespace, Name.Namespace, Keyword)), (r'(use)(\s+)([a-z_][\w.]*)', bygroups(Keyword, Whitespace, Name.Namespace)), - (r'(std|ieee)(\.[a-z_]\w*)', - bygroups(Name.Namespace, Name.Namespace)), - (words(('std', 'ieee', 'work'), suffix=r'\b'), - Name.Namespace), + (r'(std|ieee)(\.[a-z_]\w*)', + bygroups(Name.Namespace, Name.Namespace)), + (words(('std', 'ieee', 'work'), suffix=r'\b'), + Name.Namespace), (r'(entity|component)(\s+)([a-z_]\w*)', bygroups(Keyword, Whitespace, Name.Class)), (r'(architecture|configuration)(\s+)([a-z_]\w*)(\s+)' r'(of)(\s+)([a-z_]\w*)(\s+)(is)', bygroups(Keyword, Whitespace, Name.Class, Whitespace, Keyword, Whitespace, Name.Class, Whitespace, Keyword)), - (r'([a-z_]\w*)(:)(\s+)(process|for)', + (r'([a-z_]\w*)(:)(\s+)(process|for)', bygroups(Name.Class, Operator, Whitespace, Keyword)), (r'(end)(\s+)', bygroups(using(this), Whitespace), 'endblock'), @@ -431,7 +431,7 @@ class VhdlLexer(RegexLexer): 'boolean', 'bit', 'character', 'severity_level', 'integer', 'time', 'delay_length', 'natural', 'positive', 'string', 'bit_vector', 'file_open_kind', 'file_open_status', 'std_ulogic', 'std_ulogic_vector', - 'std_logic', 'std_logic_vector', 'signed', 'unsigned'), suffix=r'\b'), + 'std_logic', 'std_logic_vector', 'signed', 'unsigned'), suffix=r'\b'), Keyword.Type), ], 'keywords': [ @@ -447,8 +447,8 @@ class VhdlLexer(RegexLexer): 'next', 'nor', 'not', 'null', 'of', 'on', 'open', 'or', 'others', 'out', 'package', 'port', 'postponed', 'procedure', 'process', 'pure', 'range', 'record', - 'register', 'reject', 'rem', 'return', 'rol', 'ror', 'select', - 'severity', 'signal', 'shared', 'sla', 'sll', 'sra', + 'register', 'reject', 'rem', 'return', 'rol', 'ror', 'select', + 'severity', 'signal', 'shared', 'sla', 'sll', 'sra', 'srl', 'subtype', 'then', 'to', 'transport', 'type', 'units', 'until', 'use', 'variable', 'wait', 'when', 'while', 'with', 'xnor', 'xor'), suffix=r'\b'), |