diff options
| author | robot-piglet <[email protected]> | 2025-03-05 13:38:11 +0300 |
|---|---|---|
| committer | robot-piglet <[email protected]> | 2025-03-05 13:49:53 +0300 |
| commit | 9eed360f02de773a5ed2de5d2a3e81fc7f06acfa (patch) | |
| tree | 744a4054e64eb443073c7c6ad36b29cedcf9c2e6 /contrib/libs/llvm14/lib/CodeGen/AllocationOrder.cpp | |
| parent | c141a5c40bda2eed1a68b0626ffdae5fd19359a6 (diff) | |
Intermediate changes
commit_hash:2ec2671384dd8e604d41bc5c52c2f7858e4afea6
Diffstat (limited to 'contrib/libs/llvm14/lib/CodeGen/AllocationOrder.cpp')
| -rw-r--r-- | contrib/libs/llvm14/lib/CodeGen/AllocationOrder.cpp | 53 |
1 files changed, 0 insertions, 53 deletions
diff --git a/contrib/libs/llvm14/lib/CodeGen/AllocationOrder.cpp b/contrib/libs/llvm14/lib/CodeGen/AllocationOrder.cpp deleted file mode 100644 index 2aef1234ac0..00000000000 --- a/contrib/libs/llvm14/lib/CodeGen/AllocationOrder.cpp +++ /dev/null @@ -1,53 +0,0 @@ -//===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file implements an allocation order for virtual registers. -// -// The preferred allocation order for a virtual register depends on allocation -// hints and target hooks. The AllocationOrder class encapsulates all of that. -// -//===----------------------------------------------------------------------===// - -#include "AllocationOrder.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/RegisterClassInfo.h" -#include "llvm/CodeGen/VirtRegMap.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/raw_ostream.h" - -using namespace llvm; - -#define DEBUG_TYPE "regalloc" - -// Compare VirtRegMap::getRegAllocPref(). -AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM, - const RegisterClassInfo &RegClassInfo, - const LiveRegMatrix *Matrix) { - const MachineFunction &MF = VRM.getMachineFunction(); - const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); - auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); - SmallVector<MCPhysReg, 16> Hints; - bool HardHints = - TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix); - - LLVM_DEBUG({ - if (!Hints.empty()) { - dbgs() << "hints:"; - for (unsigned I = 0, E = Hints.size(); I != E; ++I) - dbgs() << ' ' << printReg(Hints[I], TRI); - dbgs() << '\n'; - } - }); -#ifndef NDEBUG - for (unsigned I = 0, E = Hints.size(); I != E; ++I) - assert(is_contained(Order, Hints[I]) && - "Target hint is outside allocation order."); -#endif - return AllocationOrder(std::move(Hints), Order, HardHints); -} |
