Revert ymake build from ydb oss export

176 files changed, 0 insertions, 12827 deletions

diff --git a/contrib/libs/llvm12/include/ya.make b/contrib/libs/llvm12/include/ya.make
deleted file mode 100644
index 38b79416dc..0000000000
--- a/contrib/libs/llvm12/include/ya.make
+++ /dev/null
@@ -1,3964 +0,0 @@
-# Generated by devtools/yamaker.
-
-LIBRARY()
-
-PROVIDES(llvm)
-
-LICENSE(
-    Apache-2.0 WITH LLVM-exception AND
-    BSD-2-Clause AND
-    NCSA AND
-    Public-Domain AND
-    Unicode-Mappings
-)
-
-LICENSE_TEXTS(.yandex_meta/licenses.list.txt)
-
-PEERDIR(
-    contrib/libs/llvm12
-)
-
-NO_UTIL()
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen --gen-directive-decl -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/Frontend/OpenACC -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/Frontend/OpenACC/ACC.td --write-if-changed -o
-        llvm/Frontend/OpenACC/ACC.h.inc -d llvm/Frontend/OpenACC/ACC.h.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/Frontend/Directive/DirectiveBase.td llvm/Frontend/OpenACC/ACC.td
-    OUTPUT_INCLUDES llvm/ADT/BitmaskEnum.h
-    OUT_NOAUTO llvm/Frontend/OpenACC/ACC.h.inc llvm/Frontend/OpenACC/ACC.h.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen --gen-directive-decl -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/Frontend/OpenMP -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/Frontend/OpenMP/OMP.td --write-if-changed -o
-        llvm/Frontend/OpenMP/OMP.h.inc -d llvm/Frontend/OpenMP/OMP.h.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/Frontend/Directive/DirectiveBase.td llvm/Frontend/OpenMP/OMP.td
-    OUTPUT_INCLUDES llvm/ADT/BitmaskEnum.h
-    OUT_NOAUTO llvm/Frontend/OpenMP/OMP.h.inc llvm/Frontend/OpenMP/OMP.h.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-attrs -I ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Attributes.td --write-if-changed -o
-        llvm/IR/Attributes.inc -d llvm/IR/Attributes.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/IR/Attributes.td
-    OUT_NOAUTO llvm/IR/Attributes.inc llvm/IR/Attributes.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicEnums.inc -d llvm/IR/IntrinsicEnums.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicEnums.inc llvm/IR/IntrinsicEnums.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-impl -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicImpl.inc -d llvm/IR/IntrinsicImpl.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicImpl.inc llvm/IR/IntrinsicImpl.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=aarch64 -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicsAArch64.h -d llvm/IR/IntrinsicsAArch64.h.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicsAArch64.h llvm/IR/IntrinsicsAArch64.h.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=amdgcn -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicsAMDGPU.h -d llvm/IR/IntrinsicsAMDGPU.h.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicsAMDGPU.h llvm/IR/IntrinsicsAMDGPU.h.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=arm -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicsARM.h -d llvm/IR/IntrinsicsARM.h.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicsARM.h llvm/IR/IntrinsicsARM.h.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=bpf -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicsBPF.h -d llvm/IR/IntrinsicsBPF.h.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicsBPF.h llvm/IR/IntrinsicsBPF.h.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=hexagon -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicsHexagon.h -d llvm/IR/IntrinsicsHexagon.h.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicsHexagon.h llvm/IR/IntrinsicsHexagon.h.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=mips -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicsMips.h -d llvm/IR/IntrinsicsMips.h.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicsMips.h llvm/IR/IntrinsicsMips.h.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=nvvm -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicsNVPTX.h -d llvm/IR/IntrinsicsNVPTX.h.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicsNVPTX.h llvm/IR/IntrinsicsNVPTX.h.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=ppc -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicsPowerPC.h -d llvm/IR/IntrinsicsPowerPC.h.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicsPowerPC.h llvm/IR/IntrinsicsPowerPC.h.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=r600 -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicsR600.h -d llvm/IR/IntrinsicsR600.h.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicsR600.h llvm/IR/IntrinsicsR600.h.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=riscv -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicsRISCV.h -d llvm/IR/IntrinsicsRISCV.h.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicsRISCV.h llvm/IR/IntrinsicsRISCV.h.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=s390 -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicsS390.h -d llvm/IR/IntrinsicsS390.h.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicsS390.h llvm/IR/IntrinsicsS390.h.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=ve -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicsVE.h -d llvm/IR/IntrinsicsVE.h.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicsVE.h llvm/IR/IntrinsicsVE.h.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=wasm -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicsWebAssembly.h -d llvm/IR/IntrinsicsWebAssembly.h.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicsWebAssembly.h llvm/IR/IntrinsicsWebAssembly.h.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=x86 -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicsX86.h -d llvm/IR/IntrinsicsX86.h.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicsX86.h llvm/IR/IntrinsicsX86.h.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=xcore -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
-        llvm/IR/IntrinsicsXCore.h -d llvm/IR/IntrinsicsXCore.h.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
-        llvm/IR/IntrinsicsXCore.td
-    OUT_NOAUTO llvm/IR/IntrinsicsXCore.h llvm/IR/IntrinsicsXCore.h.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen --gen-directive-impl -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenACC -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/Frontend/OpenACC/ACC.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenACC/ACC.cpp -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenACC/ACC.cpp.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/Frontend/Directive/DirectiveBase.td llvm/Frontend/OpenACC/ACC.td
-    OUTPUT_INCLUDES llvm/ADT/StringRef.h llvm/ADT/StringSwitch.h llvm/Frontend/OpenACC/ACC.h.inc
-        llvm/Support/ErrorHandling.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenACC/ACC.cpp
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenACC/ACC.cpp.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen --gen-directive-impl -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenMP -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/Frontend/OpenMP/OMP.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenMP/OMP.cpp -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenMP/OMP.cpp.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/Frontend/Directive/DirectiveBase.td llvm/Frontend/OpenMP/OMP.td
-    OUTPUT_INCLUDES llvm/ADT/StringRef.h llvm/ADT/StringSwitch.h llvm/Frontend/OpenMP/OMP.h.inc
-        llvm/Support/ErrorHandling.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenMP/OMP.cpp
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenMP/OMP.cpp.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-matcher -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmMatcher.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmMatcher.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmMatcher.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmMatcher.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -asmwriternum=1 -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter1.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter1.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter1.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter1.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-callingconv -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenCallingConv.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenCallingConv.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenCallingConv.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenCallingConv.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDAGISel.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDAGISel.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDAGISel.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDAGISel.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-disassembler -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDisassemblerTables.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDisassemblerTables.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/Support/DataTypes.h llvm/Support/Debug.h
-        llvm/Support/LEB128.h llvm/Support/raw_ostream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDisassemblerTables.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDisassemblerTables.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-exegesis -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenExegesis.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenExegesis.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenExegesis.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenExegesis.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-fast-isel -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenFastISel.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenFastISel.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenFastISel.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenFastISel.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-global-isel -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenGlobalISel.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenGlobalISel.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenGlobalISel.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenGlobalISel.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenInstrInfo.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenInstrInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenInstrInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenInstrInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES _llvm_sstream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-pseudo-lowering -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-global-isel-combiner -combiners=AArch64PostLegalizerCombinerHelper
-        -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/ADT/SparseBitVector.h
-    OUT_NOAUTO
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-global-isel-combiner -combiners=AArch64PostLegalizerLoweringHelper
-        -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/ADT/SparseBitVector.h
-    OUT_NOAUTO
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-global-isel-combiner -combiners=AArch64PreLegalizerCombinerHelper
-        -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/ADT/SparseBitVector.h
-    OUT_NOAUTO
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-bank -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterBank.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterBank.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterBank.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterBank.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-info -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterInfo.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSubtargetInfo.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSubtargetInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSubtargetInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSubtargetInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-searchable-tables -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSystemOperands.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSystemOperands.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSystemOperands.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSystemOperands.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-matcher -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmMatcher.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmMatcher.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmMatcher.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmMatcher.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmWriter.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmWriter.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmWriter.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmWriter.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-callingconv -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenCallingConv.inc
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenCallingConv.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenCallingConv.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenCallingConv.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments
-        contrib/libs/llvm12/lib/Target/ARM/ARM.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDAGISel.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDAGISel.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDAGISel.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDAGISel.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-disassembler -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
-        --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDisassemblerTables.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDisassemblerTables.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/Support/DataTypes.h llvm/Support/Debug.h
-        llvm/Support/LEB128.h llvm/Support/raw_ostream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDisassemblerTables.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDisassemblerTables.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-fast-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenFastISel.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenFastISel.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenFastISel.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenFastISel.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-global-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenGlobalISel.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenGlobalISel.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenGlobalISel.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenGlobalISel.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenInstrInfo.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenInstrInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenInstrInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenInstrInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCCodeEmitter.inc
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCCodeEmitter.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES _llvm_sstream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCCodeEmitter.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCCodeEmitter.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-pseudo-lowering -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/ARM/ARM.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCPseudoLowering.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCPseudoLowering.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCPseudoLowering.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCPseudoLowering.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-bank -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/ARM/ARM.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterBank.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterBank.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterBank.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterBank.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-info -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/ARM/ARM.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterInfo.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSubtargetInfo.inc
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSubtargetInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSubtargetInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSubtargetInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-searchable-tables -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/ARM/ARM.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSystemRegister.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSystemRegister.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSystemRegister.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSystemRegister.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-matcher -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmMatcher.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmMatcher.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmMatcher.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmMatcher.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmWriter.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmWriter.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmWriter.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmWriter.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-callingconv -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenCallingConv.inc
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenCallingConv.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenCallingConv.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenCallingConv.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments
-        contrib/libs/llvm12/lib/Target/BPF/BPF.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDAGISel.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDAGISel.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDAGISel.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDAGISel.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-disassembler -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td
-        --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDisassemblerTables.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDisassemblerTables.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/Support/DataTypes.h llvm/Support/Debug.h
-        llvm/Support/LEB128.h llvm/Support/raw_ostream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDisassemblerTables.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDisassemblerTables.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenInstrInfo.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenInstrInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenInstrInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenInstrInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenMCCodeEmitter.inc
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenMCCodeEmitter.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES _llvm_sstream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenMCCodeEmitter.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenMCCodeEmitter.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-info -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/BPF/BPF.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenRegisterInfo.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenRegisterInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenRegisterInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenRegisterInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenSubtargetInfo.inc
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenSubtargetInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenSubtargetInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenSubtargetInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenAsmWriter.inc
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenAsmWriter.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrFormats.td
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrInfo.td
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXIntrinsics.td
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenAsmWriter.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenAsmWriter.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenDAGISel.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenDAGISel.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrFormats.td
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrInfo.td
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXIntrinsics.td
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenDAGISel.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenDAGISel.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenInstrInfo.inc
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenInstrInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrFormats.td
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrInfo.td
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXIntrinsics.td
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenInstrInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenInstrInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-info -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrFormats.td
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrInfo.td
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXIntrinsics.td
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td
-        --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrFormats.td
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrInfo.td
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXIntrinsics.td
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-matcher -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmMatcher.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmMatcher.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmMatcher.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmMatcher.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmWriter.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmWriter.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmWriter.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmWriter.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-callingconv -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenCallingConv.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenCallingConv.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenCallingConv.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenCallingConv.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDAGISel.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDAGISel.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDAGISel.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDAGISel.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-disassembler -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDisassemblerTables.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDisassemblerTables.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/Support/DataTypes.h llvm/Support/Debug.h
-        llvm/Support/LEB128.h llvm/Support/raw_ostream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDisassemblerTables.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDisassemblerTables.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-exegesis -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/PowerPC/PPC.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenExegesis.inc
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenExegesis.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenExegesis.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenExegesis.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-fast-isel -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenFastISel.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenFastISel.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenFastISel.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenFastISel.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-global-isel -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenGlobalISel.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenGlobalISel.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenGlobalISel.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenGlobalISel.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenInstrInfo.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenInstrInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenInstrInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenInstrInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/PowerPC/PPC.td
-        --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES _llvm_sstream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-bank -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterBank.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterBank.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterBank.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterBank.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-info -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterInfo.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenSubtargetInfo.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenSubtargetInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenSubtargetInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenSubtargetInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-matcher -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmMatcher.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmMatcher.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmMatcher.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmMatcher.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -asmwriternum=1 -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/X86/X86.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter1.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter1.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter1.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter1.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-callingconv -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenCallingConv.inc
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenCallingConv.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenCallingConv.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenCallingConv.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments
-        contrib/libs/llvm12/lib/Target/X86/X86.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDAGISel.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDAGISel.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDAGISel.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDAGISel.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-disassembler -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
-        --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDisassemblerTables.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDisassemblerTables.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDisassemblerTables.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDisassemblerTables.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-x86-EVEX2VEX-tables -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/X86/X86.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenEVEX2VEXTables.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenEVEX2VEXTables.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenEVEX2VEXTables.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenEVEX2VEXTables.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-exegesis -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenExegesis.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenExegesis.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenExegesis.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenExegesis.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-fast-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenFastISel.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenFastISel.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenFastISel.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenFastISel.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-global-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenGlobalISel.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenGlobalISel.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenGlobalISel.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenGlobalISel.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenInstrInfo.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenInstrInfo.inc.d
-        --long-string-literals=0
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenInstrInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenInstrInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-bank -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/X86/X86.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterBank.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterBank.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterBank.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterBank.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-info -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
-        contrib/libs/llvm12/lib/Target/X86/X86.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterInfo.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenSubtargetInfo.inc
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenSubtargetInfo.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
-    OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenSubtargetInfo.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenSubtargetInfo.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include
-        contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-lib -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.inc
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/dsymutil -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/dsymutil/Options.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/dsymutil/Options.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/dsymutil/Options.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/tools/dsymutil/Options.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/dsymutil/Options.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/dsymutil/Options.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-cvtres -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-cvtres/Opts.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-cvtres/Opts.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-cvtres/Opts.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/tools/llvm-cvtres/Opts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-cvtres/Opts.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-cvtres/Opts.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-lipo -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-ml -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-ml/Opts.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-ml/Opts.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-ml/Opts.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/tools/llvm-ml/Opts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-ml/Opts.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-ml/Opts.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-mt -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-mt/Opts.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-mt/Opts.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-mt/Opts.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/tools/llvm-mt/Opts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-mt/Opts.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-mt/Opts.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include
-        contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include
-        contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.td --write-if-changed -o
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/tools/llvm-objcopy/CommonOpts.td
-        contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/tools/llvm-objcopy/CommonOpts.td
-        contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-rc -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-rc/Opts.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-rc/Opts.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-rc/Opts.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/tools/llvm-rc/Opts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-rc/Opts.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-rc/Opts.inc.d
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-symbolizer -Iinclude
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-symbolizer/Opts.td
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-symbolizer/Opts.inc -d
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-symbolizer/Opts.inc.d
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/tools/llvm-symbolizer/Opts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-symbolizer/Opts.inc
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-symbolizer/Opts.inc.d
-)
-
-END()
diff --git a/contrib/libs/llvm12/lib/Analysis/ya.make b/contrib/libs/llvm12/lib/Analysis/ya.make
deleted file mode 100644
index 9de20901d6..0000000000
--- a/contrib/libs/llvm12/lib/Analysis/ya.make
+++ /dev/null
@@ -1,146 +0,0 @@
-# Generated by devtools/yamaker.
-
-LIBRARY()
-
-LICENSE(
-    Apache-2.0 WITH LLVM-exception AND
-    NCSA
-)
-
-LICENSE_TEXTS(.yandex_meta/licenses.list.txt)
-
-PEERDIR(
-    contrib/libs/llvm12
-    contrib/libs/llvm12/include
-    contrib/libs/llvm12/lib/BinaryFormat
-    contrib/libs/llvm12/lib/IR
-    contrib/libs/llvm12/lib/Object
-    contrib/libs/llvm12/lib/ProfileData
-    contrib/libs/llvm12/lib/Support
-)
-
-ADDINCL(
-    contrib/libs/llvm12/lib/Analysis
-)
-
-NO_COMPILER_WARNINGS()
-
-NO_UTIL()
-
-SRCS(
-    AliasAnalysis.cpp
-    AliasAnalysisEvaluator.cpp
-    AliasAnalysisSummary.cpp
-    AliasSetTracker.cpp
-    Analysis.cpp
-    AssumeBundleQueries.cpp
-    AssumptionCache.cpp
-    BasicAliasAnalysis.cpp
-    BlockFrequencyInfo.cpp
-    BlockFrequencyInfoImpl.cpp
-    BranchProbabilityInfo.cpp
-    CFG.cpp
-    CFGPrinter.cpp
-    CFLAndersAliasAnalysis.cpp
-    CFLSteensAliasAnalysis.cpp
-    CGSCCPassManager.cpp
-    CallGraph.cpp
-    CallGraphSCCPass.cpp
-    CallPrinter.cpp
-    CaptureTracking.cpp
-    CmpInstAnalysis.cpp
-    CodeMetrics.cpp
-    ConstantFolding.cpp
-    ConstraintSystem.cpp
-    CostModel.cpp
-    DDG.cpp
-    DDGPrinter.cpp
-    Delinearization.cpp
-    DemandedBits.cpp
-    DependenceAnalysis.cpp
-    DependenceGraphBuilder.cpp
-    DevelopmentModeInlineAdvisor.cpp
-    DivergenceAnalysis.cpp
-    DomPrinter.cpp
-    DomTreeUpdater.cpp
-    DominanceFrontier.cpp
-    EHPersonalities.cpp
-    FunctionPropertiesAnalysis.cpp
-    GlobalsModRef.cpp
-    GuardUtils.cpp
-    HeatUtils.cpp
-    IRSimilarityIdentifier.cpp
-    IVDescriptors.cpp
-    IVUsers.cpp
-    ImportedFunctionsInliningStatistics.cpp
-    IndirectCallPromotionAnalysis.cpp
-    InlineAdvisor.cpp
-    InlineCost.cpp
-    InlineSizeEstimatorAnalysis.cpp
-    InstCount.cpp
-    InstructionPrecedenceTracking.cpp
-    InstructionSimplify.cpp
-    Interval.cpp
-    IntervalPartition.cpp
-    LazyBlockFrequencyInfo.cpp
-    LazyBranchProbabilityInfo.cpp
-    LazyCallGraph.cpp
-    LazyValueInfo.cpp
-    LegacyDivergenceAnalysis.cpp
-    Lint.cpp
-    Loads.cpp
-    LoopAccessAnalysis.cpp
-    LoopAnalysisManager.cpp
-    LoopCacheAnalysis.cpp
-    LoopInfo.cpp
-    LoopNestAnalysis.cpp
-    LoopPass.cpp
-    LoopUnrollAnalyzer.cpp
-    MLInlineAdvisor.cpp
-    MemDepPrinter.cpp
-    MemDerefPrinter.cpp
-    MemoryBuiltins.cpp
-    MemoryDependenceAnalysis.cpp
-    MemoryLocation.cpp
-    MemorySSA.cpp
-    MemorySSAUpdater.cpp
-    ModuleDebugInfoPrinter.cpp
-    ModuleSummaryAnalysis.cpp
-    MustExecute.cpp
-    ObjCARCAliasAnalysis.cpp
-    ObjCARCAnalysisUtils.cpp
-    ObjCARCInstKind.cpp
-    OptimizationRemarkEmitter.cpp
-    PHITransAddr.cpp
-    PhiValues.cpp
-    PostDominators.cpp
-    ProfileSummaryInfo.cpp
-    PtrUseVisitor.cpp
-    RegionInfo.cpp
-    RegionPass.cpp
-    RegionPrinter.cpp
-    ReleaseModeModelRunner.cpp
-    ReplayInlineAdvisor.cpp
-    ScalarEvolution.cpp
-    ScalarEvolutionAliasAnalysis.cpp
-    ScalarEvolutionDivision.cpp
-    ScalarEvolutionNormalization.cpp
-    ScopedNoAliasAA.cpp
-    StackLifetime.cpp
-    StackSafetyAnalysis.cpp
-    SyncDependenceAnalysis.cpp
-    SyntheticCountsUtils.cpp
-    TFUtils.cpp
-    TargetLibraryInfo.cpp
-    TargetTransformInfo.cpp
-    Trace.cpp
-    TypeBasedAliasAnalysis.cpp
-    TypeMetadataUtils.cpp
-    VFABIDemangling.cpp
-    ValueLattice.cpp
-    ValueLatticeUtils.cpp
-    ValueTracking.cpp
-    VectorUtils.cpp
-)
-
-END()
diff --git a/contrib/libs/llvm12/lib/AsmParser/ya.make b/contrib/libs/llvm12/lib/AsmParser/ya.make
deleted file mode 100644
index 5a2ed51a71..0000000000
--- a/contrib/libs/llvm12/lib/AsmParser/ya.make
+++ /dev/null
@@ -1,31 +0,0 @@
-# Generated by devtools/yamaker.
-
-LIBRARY()
-
-LICENSE(Apache-2.0 WITH LLVM-exception)
-
-LICENSE_TEXTS(.yandex_meta/licenses.list.txt)
-
-PEERDIR(
-    contrib/libs/llvm12
-    contrib/libs/llvm12/include
-    contrib/libs/llvm12/lib/BinaryFormat
-    contrib/libs/llvm12/lib/IR
-    contrib/libs/llvm12/lib/Support
-)
-
-ADDINCL(
-    contrib/libs/llvm12/lib/AsmParser
-)
-
-NO_COMPILER_WARNINGS()
-
-NO_UTIL()
-
-SRCS(
-    LLLexer.cpp
-    LLParser.cpp
-    Parser.cpp
-)
-
-END()
diff --git a/contrib/libs/llvm12/lib/BinaryFormat/ya.make b/contrib/libs/llvm12/lib/BinaryFormat/ya.make
deleted file mode 100644
index c466edfa5c..0000000000
--- a/contrib/libs/llvm12/lib/BinaryFormat/ya.make
+++ /dev/null
@@ -1,39 +0,0 @@
-# Generated by devtools/yamaker.
-
-LIBRARY()
-
-LICENSE(
-    Apache-2.0 WITH LLVM-exception AND
-    NCSA
-)
-
-LICENSE_TEXTS(.yandex_meta/licenses.list.txt)
-
-PEERDIR(
-    contrib/libs/llvm12
-    contrib/libs/llvm12/lib/Support
-)
-
-ADDINCL(
-    contrib/libs/llvm12/lib/BinaryFormat
-)
-
-NO_COMPILER_WARNINGS()
-
-NO_UTIL()
-
-SRCS(
-    AMDGPUMetadataVerifier.cpp
-    Dwarf.cpp
-    MachO.cpp
-    Magic.cpp
-    Minidump.cpp
-    MsgPackDocument.cpp
-    MsgPackDocumentYAML.cpp
-    MsgPackReader.cpp
-    MsgPackWriter.cpp
-    Wasm.cpp
-    XCOFF.cpp
-)
-
-END()
diff --git a/contrib/libs/llvm12/lib/Bitcode/Reader/ya.make b/contrib/libs/llvm12/lib/Bitcode/Reader/ya.make
deleted file mode 100644
index 5ff600cff8..0000000000
--- a/contrib/libs/llvm12/lib/Bitcode/Reader/ya.make
+++ /dev/null
@@ -1,33 +0,0 @@
-# Generated by devtools/yamaker.
-
-LIBRARY()
-
-LICENSE(Apache-2.0 WITH LLVM-exception)
-
-LICENSE_TEXTS(.yandex_meta/licenses.list.txt)
-
-PEERDIR(
-    contrib/libs/llvm12
-    contrib/libs/llvm12/include
-    contrib/libs/llvm12/lib/Bitstream/Reader
-    contrib/libs/llvm12/lib/IR
-    contrib/libs/llvm12/lib/Support
-)
-
-ADDINCL(
-    contrib/libs/llvm12/lib/Bitcode/Reader
-)
-
-NO_COMPILER_WARNINGS()
-
-NO_UTIL()
-
-SRCS(
-    BitReader.cpp
-    BitcodeAnalyzer.cpp
-    BitcodeReader.cpp
-    MetadataLoader.cpp
-    ValueList.cpp
-)
-
-END()
diff --git a/contrib/libs/llvm12/lib/Bitcode/Writer/ya.make b/contrib/libs/llvm12/lib/Bitcode/Writer/ya.make
deleted file mode 100644
index 3a4ff16476..0000000000
--- a/contrib/libs/llvm12/lib/Bitcode/Writer/ya.make
+++ /dev/null
@@ -1,34 +0,0 @@
-# Generated by devtools/yamaker.
-
-LIBRARY()
-
-LICENSE(Apache-2.0 WITH LLVM-exception)
-
-LICENSE_TEXTS(.yandex_meta/licenses.list.txt)
-
-PEERDIR(
-    contrib/libs/llvm12
-    contrib/libs/llvm12/include
-    contrib/libs/llvm12/lib/Analysis
-    contrib/libs/llvm12/lib/IR
-    contrib/libs/llvm12/lib/MC
-    contrib/libs/llvm12/lib/Object
-    contrib/libs/llvm12/lib/Support
-)
-
-ADDINCL(
-    contrib/libs/llvm12/lib/Bitcode/Writer
-)
-
-NO_COMPILER_WARNINGS()
-
-NO_UTIL()
-
-SRCS(
-    BitWriter.cpp
-    BitcodeWriter.cpp
-    BitcodeWriterPass.cpp
-    ValueEnumerator.cpp
-)
-
-END()
diff --git a/contrib/libs/llvm12/lib/Bitstream/Reader/ya.make b/contrib/libs/llvm12/lib/Bitstream/Reader/ya.make
deleted file mode 100644
index db6b43a8cb..0000000000
--- a/contrib/libs/llvm12/lib/Bitstream/Reader/ya.make
+++ /dev/null
@@ -1,26 +0,0 @@
-# Generated by devtools/yamaker.
-
-LIBRARY()
-
-LICENSE(Apache-2.0 WITH LLVM-exception)
-
-LICENSE_TEXTS(.yandex_meta/licenses.list.txt)
-
-PEERDIR(
-    contrib/libs/llvm12
-    contrib/libs/llvm12/lib/Support
-)
-
-ADDINCL(
-    contrib/libs/llvm12/lib/Bitstream/Reader
-)
-
-NO_COMPILER_WARNINGS()
-
-NO_UTIL()
-
-SRCS(
-    BitstreamReader.cpp
-)
-
-END()
diff --git a/contrib/libs/llvm12/lib/CodeGen/AsmPrinter/ya.make b/contrib/libs/llvm12/lib/CodeGen/AsmPrinter/ya.make
deleted file mode 100644
index d0236557d8..0000000000
--- a/contrib/libs/llvm12/lib/CodeGen/AsmPrinter/ya.make
+++ /dev/null
@@ -1,70 +0,0 @@
-# Generated by devtools/yamaker.
-
-LIBRARY()
-
-LICENSE(Apache-2.0 WITH LLVM-exception)
-
-LICENSE_TEXTS(.yandex_meta/licenses.list.txt)
-
-PEERDIR(
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-    DIE.cpp
-    DIEHash.cpp
-    DbgEntityHistoryCalculator.cpp
-    DebugHandlerBase.cpp
-    DebugLocStream.cpp
-    DwarfCFIException.cpp
-    DwarfCompileUnit.cpp
-    DwarfDebug.cpp
-    DwarfExpression.cpp
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-    DwarfStringPool.cpp
-    DwarfUnit.cpp
-    EHStreamer.cpp
-    ErlangGCPrinter.cpp
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deleted file mode 100644
index d4ee068aff..0000000000
--- a/contrib/libs/llvm12/lib/CodeGen/GlobalISel/ya.make
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-    MachineInstr.cpp
-    MachineInstrBundle.cpp
-    MachineLICM.cpp
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-    MachineModuleInfo.cpp
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-    MachineOperand.cpp
-    MachineOptimizationRemarkEmitter.cpp
-    MachineOutliner.cpp
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-    MachinePipeliner.cpp
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-    MachineStableHash.cpp
-    MachineStripDebug.cpp
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-    RegAllocGreedy.cpp
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-    RegUsageInfoCollector.cpp
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-    RegisterClassInfo.cpp
-    RegisterCoalescer.cpp
-    RegisterPressure.cpp
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-    RegisterUsageInfo.cpp
-    RenameIndependentSubregs.cpp
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-    SafeStack.cpp
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-    ScheduleDAG.cpp
-    ScheduleDAGInstrs.cpp
-    ScheduleDAGPrinter.cpp
-    ScoreboardHazardRecognizer.cpp
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-    SjLjEHPrepare.cpp
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-    SwiftErrorValueTracking.cpp
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-    UnreachableBlockElim.cpp
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deleted file mode 100644
index f1b7585231..0000000000
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deleted file mode 100644
index 22f831fb25..0000000000
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-
-END()
diff --git a/contrib/libs/llvm12/ya.make b/contrib/libs/llvm12/ya.make
deleted file mode 100644
index fa17df6b8e..0000000000
--- a/contrib/libs/llvm12/ya.make
+++ /dev/null
@@ -1,204 +0,0 @@
-# Generated by devtools/yamaker from nixpkgs 21.11.
-
-LIBRARY()
-
-LICENSE(
-    Apache-2.0 WITH LLVM-exception AND
-    NCSA
-)
-
-LICENSE_TEXTS(.yandex_meta/licenses.list.txt)
-
-VERSION(12.0.1)
-
-ORIGINAL_SOURCE(https://github.com/llvm/llvm-project/releases/download/llvmorg-12.0.1/llvm-12.0.1.src.tar.xz)
-
-ADDINCL(
-    GLOBAL ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/include
-    GLOBAL contrib/libs/llvm12/include
-)
-
-END()
-
-RECURSE(
-    include
-    lib/Analysis
-    lib/AsmParser
-    lib/BinaryFormat
-    lib/Bitcode/Reader
-    lib/Bitcode/Writer
-    lib/Bitstream/Reader
-    lib/CodeGen
-    lib/CodeGen/AsmPrinter
-    lib/CodeGen/GlobalISel
-    lib/CodeGen/MIRParser
-    lib/CodeGen/SelectionDAG
-    lib/DWARFLinker
-    lib/DebugInfo/CodeView
-    lib/DebugInfo/DWARF
-    lib/DebugInfo/GSYM
-    lib/DebugInfo/MSF
-    lib/DebugInfo/PDB
-    lib/DebugInfo/Symbolize
-    lib/Demangle
-    lib/ExecutionEngine
-    lib/ExecutionEngine/Interpreter
-    lib/ExecutionEngine/JITLink
-    lib/ExecutionEngine/MCJIT
-    lib/ExecutionEngine/Orc
-    lib/ExecutionEngine/Orc/Shared
-    lib/ExecutionEngine/Orc/TargetProcess
-    lib/ExecutionEngine/RuntimeDyld
-    lib/Extensions
-    lib/FileCheck
-    lib/Frontend/OpenACC
-    lib/Frontend/OpenMP
-    lib/FuzzMutate
-    lib/IR
-    lib/IRReader
-    lib/InterfaceStub
-    lib/LTO
-    lib/LineEditor
-    lib/Linker
-    lib/MC
-    lib/MC/MCDisassembler
-    lib/MC/MCParser
-    lib/MCA
-    lib/Object
-    lib/ObjectYAML
-    lib/Option
-    lib/Passes
-    lib/ProfileData
-    lib/ProfileData/Coverage
-    lib/Remarks
-    lib/Support
-    lib/TableGen
-    lib/Target
-    lib/Target/AArch64
-    lib/Target/AArch64/AsmParser
-    lib/Target/AArch64/Disassembler
-    lib/Target/AArch64/MCTargetDesc
-    lib/Target/AArch64/TargetInfo
-    lib/Target/AArch64/Utils
-    lib/Target/ARM
-    lib/Target/ARM/AsmParser
-    lib/Target/ARM/Disassembler
-    lib/Target/ARM/MCTargetDesc
-    lib/Target/ARM/TargetInfo
-    lib/Target/ARM/Utils
-    lib/Target/BPF
-    lib/Target/BPF/AsmParser
-    lib/Target/BPF/Disassembler
-    lib/Target/BPF/MCTargetDesc
-    lib/Target/BPF/TargetInfo
-    lib/Target/NVPTX
-    lib/Target/NVPTX/MCTargetDesc
-    lib/Target/NVPTX/TargetInfo
-    lib/Target/PowerPC
-    lib/Target/PowerPC/AsmParser
-    lib/Target/PowerPC/Disassembler
-    lib/Target/PowerPC/MCTargetDesc
-    lib/Target/PowerPC/TargetInfo
-    lib/Target/X86
-    lib/Target/X86/AsmParser
-    lib/Target/X86/Disassembler
-    lib/Target/X86/MCTargetDesc
-    lib/Target/X86/TargetInfo
-    lib/TextAPI/MachO
-    lib/ToolDrivers/llvm-dlltool
-    lib/ToolDrivers/llvm-lib
-    lib/Transforms/AggressiveInstCombine
-    lib/Transforms/CFGuard
-    lib/Transforms/Coroutines
-    lib/Transforms/HelloNew
-    lib/Transforms/IPO
-    lib/Transforms/InstCombine
-    lib/Transforms/Instrumentation
-    lib/Transforms/ObjCARC
-    lib/Transforms/Scalar
-    lib/Transforms/Utils
-    lib/Transforms/Vectorize
-    lib/WindowsManifest
-    lib/XRay
-    tools/bugpoint
-    tools/dsymutil
-    tools/llc
-    tools/lli
-    tools/lli/ChildTarget
-    tools/llvm-ar
-    tools/llvm-as
-    tools/llvm-bcanalyzer
-    tools/llvm-cat
-    tools/llvm-cfi-verify
-    tools/llvm-cfi-verify/lib
-    tools/llvm-config
-    tools/llvm-cov
-    tools/llvm-cvtres
-    tools/llvm-cxxdump
-    tools/llvm-cxxfilt
-    tools/llvm-cxxmap
-    tools/llvm-diff
-    tools/llvm-dis
-    tools/llvm-dwarfdump
-    tools/llvm-dwp
-    tools/llvm-elfabi
-    tools/llvm-exegesis
-    tools/llvm-exegesis/lib
-    tools/llvm-exegesis/lib/AArch64
-    tools/llvm-exegesis/lib/PowerPC
-    tools/llvm-exegesis/lib/X86
-    tools/llvm-extract
-    tools/llvm-gsymutil
-    tools/llvm-ifs
-    tools/llvm-jitlink
-    tools/llvm-jitlink/llvm-jitlink-executor
-    tools/llvm-libtool-darwin
-    tools/llvm-link
-    tools/llvm-lipo
-    tools/llvm-lto
-    tools/llvm-lto2
-    tools/llvm-mc
-    tools/llvm-mca
-    tools/llvm-ml
-    tools/llvm-modextract
-    tools/llvm-mt
-    tools/llvm-nm
-    tools/llvm-objcopy
-    tools/llvm-objdump
-    tools/llvm-opt-report
-    tools/llvm-pdbutil
-    tools/llvm-profdata
-    tools/llvm-profgen
-    tools/llvm-rc
-    tools/llvm-readobj
-    tools/llvm-reduce
-    tools/llvm-rtdyld
-    tools/llvm-size
-    tools/llvm-split
-    tools/llvm-stress
-    tools/llvm-strings
-    tools/llvm-symbolizer
-    tools/llvm-undname
-    tools/llvm-xray
-    tools/lto
-    tools/obj2yaml
-    tools/opt
-    tools/polly/lib
-    tools/polly/lib/External/isl
-    tools/polly/lib/External/ppcg
-    tools/remarks-shlib
-    tools/sancov
-    tools/sanstats
-    tools/split-file
-    tools/verify-uselistorder
-    tools/yaml2obj
-    utils/TableGen
-    utils/TableGen/GlobalISel
-)
-
-IF (OS_LINUX)
-    RECURSE(
-        lib/ExecutionEngine/PerfJITEvents
-        tools/gold
-    )
-ENDIF()