Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 2 of 2.

53 files changed, 2603 insertions, 2603 deletions

diff --git a/contrib/libs/llvm12/utils/DSAclean.py b/contrib/libs/llvm12/utils/DSAclean.py
index 1cd9b6a8d6..c5fb56b037 100755
--- a/contrib/libs/llvm12/utils/DSAclean.py
+++ b/contrib/libs/llvm12/utils/DSAclean.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python 
+#!/usr/bin/env python
 
 #changelog: 
 #10/13/2005b: replaced the # in tmp(.#*)* with alphanumeric and _, this will then remove
diff --git a/contrib/libs/llvm12/utils/DSAextract.py b/contrib/libs/llvm12/utils/DSAextract.py
index b9a0492fbc..1d93f1e30c 100755
--- a/contrib/libs/llvm12/utils/DSAextract.py
+++ b/contrib/libs/llvm12/utils/DSAextract.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python 
+#!/usr/bin/env python
 
 #this is a script to extract given named nodes from a dot file, with
 #the associated edges.  An edge is kept iff for edge x -> y
diff --git a/contrib/libs/llvm12/utils/TableGen/AsmMatcherEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/AsmMatcherEmitter.cpp
index 245aab5049..9d304910ba 100644
--- a/contrib/libs/llvm12/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/AsmMatcherEmitter.cpp
@@ -612,7 +612,7 @@ struct MatchableInfo {
   /// operator< - Compare two matchables.
   bool operator<(const MatchableInfo &RHS) const {
     // The primary comparator is the instruction mnemonic.
-    if (int Cmp = Mnemonic.compare_lower(RHS.Mnemonic)) 
+    if (int Cmp = Mnemonic.compare_lower(RHS.Mnemonic))
       return Cmp == -1;
 
     if (AsmOperands.size() != RHS.AsmOperands.size())
@@ -789,8 +789,8 @@ public:
   }
 
   bool hasOptionalOperands() const {
-    return any_of(Classes, 
-                  [](const ClassInfo &Class) { return Class.IsOptional; }); 
+    return any_of(Classes,
+                  [](const ClassInfo &Class) { return Class.IsOptional; });
   }
 };
 
@@ -1017,7 +1017,7 @@ void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info,
 
     case '$': {
       if (InTok) {
-        addAsmOperand(String.slice(Prev, i), IsIsolatedToken); 
+        addAsmOperand(String.slice(Prev, i), IsIsolatedToken);
         InTok = false;
         IsIsolatedToken = false;
       }
@@ -1112,7 +1112,7 @@ static std::string getEnumNameForToken(StringRef Str) {
     case '-': Res += "_MINUS_"; break;
     case '#': Res += "_HASH_"; break;
     default:
-      if (isAlnum(*it)) 
+      if (isAlnum(*it))
         Res += *it;
       else
         Res += "_" + utostr((unsigned) *it) + "_";
@@ -1977,7 +1977,7 @@ emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
   }
   CvtOS << "  unsigned OpIdx;\n";
   CvtOS << "  Inst.setOpcode(Opcode);\n";
-  CvtOS << "  for (const uint8_t *p = Converter; *p; p += 2) {\n"; 
+  CvtOS << "  for (const uint8_t *p = Converter; *p; p += 2) {\n";
   if (HasOptionalOperands) {
     CvtOS << "    OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];\n";
   } else {
@@ -1987,14 +1987,14 @@ emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
   CvtOS << "    default: llvm_unreachable(\"invalid conversion entry!\");\n";
   CvtOS << "    case CVT_Reg:\n";
   CvtOS << "      static_cast<" << TargetOperandClass
-        << " &>(*Operands[OpIdx]).addRegOperands(Inst, 1);\n"; 
+        << " &>(*Operands[OpIdx]).addRegOperands(Inst, 1);\n";
   CvtOS << "      break;\n";
   CvtOS << "    case CVT_Tied: {\n";
   CvtOS << "      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -\n";
-  CvtOS << "                              std::begin(TiedAsmOperandTable)) &&\n"; 
+  CvtOS << "                              std::begin(TiedAsmOperandTable)) &&\n";
   CvtOS << "             \"Tied operand not found\");\n";
   CvtOS << "      unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];\n";
-  CvtOS << "      if (TiedResOpnd != (uint8_t)-1)\n"; 
+  CvtOS << "      if (TiedResOpnd != (uint8_t)-1)\n";
   CvtOS << "        Inst.addOperand(Inst.getOperand(TiedResOpnd));\n";
   CvtOS << "      break;\n";
   CvtOS << "    }\n";
@@ -2009,7 +2009,7 @@ emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
        << "  assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
        << "  unsigned NumMCOperands = 0;\n"
        << "  const uint8_t *Converter = ConversionTable[Kind];\n"
-       << "  for (const uint8_t *p = Converter; *p; p += 2) {\n" 
+       << "  for (const uint8_t *p = Converter; *p; p += 2) {\n"
        << "    switch (*p) {\n"
        << "    default: llvm_unreachable(\"invalid conversion entry!\");\n"
        << "    case CVT_Reg:\n"
@@ -2126,12 +2126,12 @@ emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
                 << OpInfo.MINumOperands << ");\n"
                 << "      } else {\n"
                 << "        static_cast<" << TargetOperandClass
-                << " &>(*Operands[OpIdx])." << Op.Class->RenderMethod 
+                << " &>(*Operands[OpIdx])." << Op.Class->RenderMethod
                 << "(Inst, " << OpInfo.MINumOperands << ");\n"
                 << "      }\n";
         } else {
           CvtOS << "      static_cast<" << TargetOperandClass
-                << " &>(*Operands[OpIdx])." << Op.Class->RenderMethod 
+                << " &>(*Operands[OpIdx])." << Op.Class->RenderMethod
                 << "(Inst, " << OpInfo.MINumOperands << ");\n";
         }
         CvtOS << "      break;\n";
@@ -2387,9 +2387,9 @@ static void emitMatchClassEnumeration(CodeGenTarget &Target,
 static void emitOperandMatchErrorDiagStrings(AsmMatcherInfo &Info, raw_ostream &OS) {
   // If the target does not use DiagnosticString for any operands, don't emit
   // an unused function.
-  if (llvm::all_of(Info.Classes, [](const ClassInfo &CI) { 
-        return CI.DiagnosticString.empty(); 
-      })) 
+  if (llvm::all_of(Info.Classes, [](const ClassInfo &CI) {
+        return CI.DiagnosticString.empty();
+      }))
     return;
 
   OS << "static const char *getMatchKindDiag(" << Info.Target.getName()
@@ -2445,7 +2445,7 @@ static void emitValidateOperandClass(AsmMatcherInfo &Info,
   OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
      << "MatchClassKind Kind) {\n";
   OS << "  " << Info.Target.getName() << "Operand &Operand = ("
-     << Info.Target.getName() << "Operand &)GOp;\n"; 
+     << Info.Target.getName() << "Operand &)GOp;\n";
 
   // The InvalidMatchClass is not to match any operand.
   OS << "  if (Kind == InvalidMatchClass)\n";
@@ -2808,7 +2808,7 @@ static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
     Record *AsmVariant = Target.getAsmParserVariant(VC);
     int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
     StringRef AsmParserVariantName = AsmVariant->getValueAsString("Name");
-    OS << "  case " << AsmParserVariantNo << ":\n"; 
+    OS << "  case " << AsmParserVariantNo << ":\n";
     emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
                              AsmParserVariantName);
     OS << "    break;\n";
@@ -2877,7 +2877,7 @@ static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
     OS << "  { ";
 
     // Store a pascal-style length byte in the mnemonic.
-    std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.lower(); 
+    std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.lower();
     OS << StringTable.GetOrAddStringOffset(LenMnemonic, false)
        << " /* " << II.Mnemonic << " */, ";
 
@@ -2975,7 +2975,7 @@ static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
         "FeatureBitsets[it->RequiredFeaturesIdx];\n";
   OS << "    if (!ParseForAllFeatures && (AvailableFeatures & "
         "RequiredFeatures) != RequiredFeatures)\n";
-  OS << "      continue;\n\n"; 
+  OS << "      continue;\n\n";
 
   // Emit check to ensure the operand number matches.
   OS << "    // check if the operand in question has a custom parser.\n";
@@ -3008,10 +3008,10 @@ static void emitAsmTiedOperandConstraints(CodeGenTarget &Target,
   OS << "                               uint64_t &ErrorInfo) {\n";
   OS << "  assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n";
   OS << "  const uint8_t *Converter = ConversionTable[Kind];\n";
-  OS << "  for (const uint8_t *p = Converter; *p; p += 2) {\n"; 
+  OS << "  for (const uint8_t *p = Converter; *p; p += 2) {\n";
   OS << "    switch (*p) {\n";
   OS << "    case CVT_Tied: {\n";
-  OS << "      unsigned OpIdx = *(p + 1);\n"; 
+  OS << "      unsigned OpIdx = *(p + 1);\n";
   OS << "      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -\n";
   OS << "                              std::begin(TiedAsmOperandTable)) &&\n";
   OS << "             \"Tied operand not found\");\n";
@@ -3083,7 +3083,7 @@ static void emitMnemonicSpellChecker(raw_ostream &OS, CodeGenTarget &Target,
     OS << "\n";
     OS << "  std::string Res = \", did you mean: \";\n";
     OS << "  unsigned i = 0;\n";
-    OS << "  for (; i < Candidates.size() - 1; i++)\n"; 
+    OS << "  for (; i < Candidates.size() - 1; i++)\n";
     OS << "    Res += Candidates[i].str() + \", \";\n";
     OS << "  return Res + Candidates[i].str() + \"?\";\n";
   }
@@ -3091,68 +3091,68 @@ static void emitMnemonicSpellChecker(raw_ostream &OS, CodeGenTarget &Target,
   OS << "\n";
 }
 
-static void emitMnemonicChecker(raw_ostream &OS, 
-                                CodeGenTarget &Target, 
-                                unsigned VariantCount, 
-                                bool HasMnemonicFirst, 
-                                bool HasMnemonicAliases) { 
-  OS << "static bool " << Target.getName() 
-     << "CheckMnemonic(StringRef Mnemonic,\n"; 
-  OS << "                                " 
-     << "const FeatureBitset &AvailableFeatures,\n"; 
-  OS << "                                " 
-     << "unsigned VariantID) {\n"; 
-
-  if (!VariantCount) { 
-    OS <<  "  return false;\n"; 
-  } else { 
-    if (HasMnemonicAliases) { 
-      OS << "  // Process all MnemonicAliases to remap the mnemonic.\n"; 
-      OS << "  applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);"; 
-      OS << "\n\n"; 
-    } 
-    OS << "  // Find the appropriate table for this asm variant.\n"; 
-    OS << "  const MatchEntry *Start, *End;\n"; 
-    OS << "  switch (VariantID) {\n"; 
-    OS << "  default: llvm_unreachable(\"invalid variant!\");\n"; 
-    for (unsigned VC = 0; VC != VariantCount; ++VC) { 
-      Record *AsmVariant = Target.getAsmParserVariant(VC); 
-      int AsmVariantNo = AsmVariant->getValueAsInt("Variant"); 
-      OS << "  case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC 
-         << "); End = std::end(MatchTable" << VC << "); break;\n"; 
-    } 
-    OS << "  }\n\n"; 
- 
-    OS << "  // Search the table.\n"; 
-    if (HasMnemonicFirst) { 
-      OS << "  auto MnemonicRange = " 
-            "std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n"; 
-    } else { 
-      OS << "  auto MnemonicRange = std::make_pair(Start, End);\n"; 
-      OS << "  unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n"; 
-      OS << "  if (!Mnemonic.empty())\n"; 
-      OS << "    MnemonicRange = " 
-         << "std::equal_range(Start, End, Mnemonic.lower(), LessOpcode());\n\n"; 
-    } 
- 
-    OS << "  if (MnemonicRange.first == MnemonicRange.second)\n"; 
-    OS << "    return false;\n\n"; 
- 
-    OS << "  for (const MatchEntry *it = MnemonicRange.first, " 
-       << "*ie = MnemonicRange.second;\n"; 
-    OS << "       it != ie; ++it) {\n"; 
-    OS << "    const FeatureBitset &RequiredFeatures =\n"; 
-    OS << "      FeatureBitsets[it->RequiredFeaturesIdx];\n"; 
-    OS << "    if ((AvailableFeatures & RequiredFeatures) == "; 
-    OS << "RequiredFeatures)\n"; 
-    OS << "      return true;\n"; 
-    OS << "  }\n"; 
-    OS << "  return false;\n"; 
-  } 
-  OS << "}\n"; 
-  OS << "\n"; 
-} 
- 
+static void emitMnemonicChecker(raw_ostream &OS,
+                                CodeGenTarget &Target,
+                                unsigned VariantCount,
+                                bool HasMnemonicFirst,
+                                bool HasMnemonicAliases) {
+  OS << "static bool " << Target.getName()
+     << "CheckMnemonic(StringRef Mnemonic,\n";
+  OS << "                                "
+     << "const FeatureBitset &AvailableFeatures,\n";
+  OS << "                                "
+     << "unsigned VariantID) {\n";
+
+  if (!VariantCount) {
+    OS <<  "  return false;\n";
+  } else {
+    if (HasMnemonicAliases) {
+      OS << "  // Process all MnemonicAliases to remap the mnemonic.\n";
+      OS << "  applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);";
+      OS << "\n\n";
+    }
+    OS << "  // Find the appropriate table for this asm variant.\n";
+    OS << "  const MatchEntry *Start, *End;\n";
+    OS << "  switch (VariantID) {\n";
+    OS << "  default: llvm_unreachable(\"invalid variant!\");\n";
+    for (unsigned VC = 0; VC != VariantCount; ++VC) {
+      Record *AsmVariant = Target.getAsmParserVariant(VC);
+      int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
+      OS << "  case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
+         << "); End = std::end(MatchTable" << VC << "); break;\n";
+    }
+    OS << "  }\n\n";
+
+    OS << "  // Search the table.\n";
+    if (HasMnemonicFirst) {
+      OS << "  auto MnemonicRange = "
+            "std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
+    } else {
+      OS << "  auto MnemonicRange = std::make_pair(Start, End);\n";
+      OS << "  unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n";
+      OS << "  if (!Mnemonic.empty())\n";
+      OS << "    MnemonicRange = "
+         << "std::equal_range(Start, End, Mnemonic.lower(), LessOpcode());\n\n";
+    }
+
+    OS << "  if (MnemonicRange.first == MnemonicRange.second)\n";
+    OS << "    return false;\n\n";
+
+    OS << "  for (const MatchEntry *it = MnemonicRange.first, "
+       << "*ie = MnemonicRange.second;\n";
+    OS << "       it != ie; ++it) {\n";
+    OS << "    const FeatureBitset &RequiredFeatures =\n";
+    OS << "      FeatureBitsets[it->RequiredFeaturesIdx];\n";
+    OS << "    if ((AvailableFeatures & RequiredFeatures) == ";
+    OS << "RequiredFeatures)\n";
+    OS << "      return true;\n";
+    OS << "  }\n";
+    OS << "  return false;\n";
+  }
+  OS << "}\n";
+  OS << "\n";
+}
+
 // Emit a function mapping match classes to strings, for debugging.
 static void emitMatchClassKindNames(std::forward_list<ClassInfo> &Infos,
                                     raw_ostream &OS) {
@@ -3252,7 +3252,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
   OS << "#undef GET_ASSEMBLER_HEADER\n";
   OS << "  // This should be included into the middle of the declaration of\n";
   OS << "  // your subclasses implementation of MCTargetAsmParser.\n";
-  OS << "  FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;\n"; 
+  OS << "  FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;\n";
   if (HasOptionalOperands) {
     OS << "  void convertToMCInst(unsigned Kind, MCInst &Inst, "
        << "unsigned Opcode,\n"
@@ -3382,7 +3382,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
     HasDeprecation |= MI->HasDeprecation;
 
     // Store a pascal-style length byte in the mnemonic.
-    std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.lower(); 
+    std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.lower();
     MaxMnemonicIndex = std::max(MaxMnemonicIndex,
                         StringTable.GetOrAddStringOffset(LenMnemonic, false));
   }
@@ -3496,8 +3496,8 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
         continue;
 
       // Store a pascal-style length byte in the mnemonic.
-      std::string LenMnemonic = 
-          char(MI->Mnemonic.size()) + MI->Mnemonic.lower(); 
+      std::string LenMnemonic =
+          char(MI->Mnemonic.size()) + MI->Mnemonic.lower();
       OS << "  { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
          << " /* " << MI->Mnemonic << " */, "
          << Target.getInstNamespace() << "::"
@@ -3556,12 +3556,12 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
   OS << "  // Get the instruction mnemonic, which is the first token.\n";
   if (HasMnemonicFirst) {
     OS << "  StringRef Mnemonic = ((" << Target.getName()
-       << "Operand &)*Operands[0]).getToken();\n\n"; 
+       << "Operand &)*Operands[0]).getToken();\n\n";
   } else {
     OS << "  StringRef Mnemonic;\n";
     OS << "  if (Operands[0]->isToken())\n";
     OS << "    Mnemonic = ((" << Target.getName()
-       << "Operand &)*Operands[0]).getToken();\n\n"; 
+       << "Operand &)*Operands[0]).getToken();\n\n";
   }
 
   if (HasMnemonicAliases) {
@@ -3611,7 +3611,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
   }
 
   OS << "  DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"AsmMatcher: found \" <<\n"
-     << "  std::distance(MnemonicRange.first, MnemonicRange.second) <<\n" 
+     << "  std::distance(MnemonicRange.first, MnemonicRange.second) <<\n"
      << "  \" encodings with mnemonic '\" << Mnemonic << \"'\\n\");\n\n";
 
   OS << "  // Return a more specific error code if no mnemonics match.\n";
@@ -3786,10 +3786,10 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
   OS << "      FeatureBitset NewMissingFeatures = RequiredFeatures & "
         "~AvailableFeatures;\n";
   OS << "      DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Missing target features:\";\n";
-  OS << "                      for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)\n"; 
-  OS << "                        if (NewMissingFeatures[I])\n"; 
-  OS << "                          dbgs() << ' ' << I;\n"; 
-  OS << "                      dbgs() << \"\\n\");\n"; 
+  OS << "                      for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)\n";
+  OS << "                        if (NewMissingFeatures[I])\n";
+  OS << "                          dbgs() << ' ' << I;\n";
+  OS << "                      dbgs() << \"\\n\");\n";
   if (ReportMultipleNearMisses) {
     OS << "      FeaturesNearMiss = NearMissInfo::getMissedFeature(NewMissingFeatures);\n";
   } else {
@@ -3924,7 +3924,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
     OS << "        getTargetOptions().MCNoDeprecatedWarn &&\n";
     OS << "        MII.getDeprecatedInfo(Inst, getSTI(), Info)) {\n";
     OS << "      SMLoc Loc = ((" << Target.getName()
-       << "Operand &)*Operands[0]).getStartLoc();\n"; 
+       << "Operand &)*Operands[0]).getStartLoc();\n";
     OS << "      getParser().Warning(Loc, Info, None);\n";
     OS << "    }\n";
   }
@@ -3967,14 +3967,14 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
   emitMnemonicSpellChecker(OS, Target, VariantCount);
 
   OS << "#endif // GET_MNEMONIC_SPELL_CHECKER\n\n";
- 
-  OS << "\n#ifdef GET_MNEMONIC_CHECKER\n"; 
-  OS << "#undef GET_MNEMONIC_CHECKER\n\n"; 
- 
-  emitMnemonicChecker(OS, Target, VariantCount, 
-                      HasMnemonicFirst, HasMnemonicAliases); 
- 
-  OS << "#endif // GET_MNEMONIC_CHECKER\n\n"; 
+
+  OS << "\n#ifdef GET_MNEMONIC_CHECKER\n";
+  OS << "#undef GET_MNEMONIC_CHECKER\n\n";
+
+  emitMnemonicChecker(OS, Target, VariantCount,
+                      HasMnemonicFirst, HasMnemonicAliases);
+
+  OS << "#endif // GET_MNEMONIC_CHECKER\n\n";
 }
 
 namespace llvm {
diff --git a/contrib/libs/llvm12/utils/TableGen/AsmWriterEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/AsmWriterEmitter.cpp
index 41f41e8ed2..92df204475 100644
--- a/contrib/libs/llvm12/utils/TableGen/AsmWriterEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/AsmWriterEmitter.cpp
@@ -65,14 +65,14 @@ public:
 
   void run(raw_ostream &o);
 private:
-  void EmitGetMnemonic( 
-      raw_ostream &o, 
-      std::vector<std::vector<std::string>> &TableDrivenOperandPrinters, 
-      unsigned &BitsLeft, unsigned &AsmStrBits); 
-  void EmitPrintInstruction( 
-      raw_ostream &o, 
-      std::vector<std::vector<std::string>> &TableDrivenOperandPrinters, 
-      unsigned &BitsLeft, unsigned &AsmStrBits); 
+  void EmitGetMnemonic(
+      raw_ostream &o,
+      std::vector<std::vector<std::string>> &TableDrivenOperandPrinters,
+      unsigned &BitsLeft, unsigned &AsmStrBits);
+  void EmitPrintInstruction(
+      raw_ostream &o,
+      std::vector<std::vector<std::string>> &TableDrivenOperandPrinters,
+      unsigned &BitsLeft, unsigned &AsmStrBits);
   void EmitGetRegisterName(raw_ostream &o);
   void EmitPrintAliasInstruction(raw_ostream &O);
 
@@ -218,11 +218,11 @@ FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
 
       // Otherwise, scan to see if all of the other instructions in this command
       // set share the operand.
-      if (any_of(drop_begin(Idxs), [&](unsigned Idx) { 
-            const AsmWriterInst &OtherInst = Instructions[Idx]; 
-            return OtherInst.Operands.size() == Op || 
-                   OtherInst.Operands[Op] != FirstInst.Operands[Op]; 
-          })) 
+      if (any_of(drop_begin(Idxs), [&](unsigned Idx) {
+            const AsmWriterInst &OtherInst = Instructions[Idx];
+            return OtherInst.Operands.size() == Op ||
+                   OtherInst.Operands[Op] != FirstInst.Operands[Op];
+          }))
         break;
 
       // Okay, everything in this command set has the same next operand.  Add it
@@ -293,19 +293,19 @@ static void UnescapeAliasString(std::string &Str) {
   }
 }
 
-void AsmWriterEmitter::EmitGetMnemonic( 
-    raw_ostream &O, 
-    std::vector<std::vector<std::string>> &TableDrivenOperandPrinters, 
-    unsigned &BitsLeft, unsigned &AsmStrBits) { 
+void AsmWriterEmitter::EmitGetMnemonic(
+    raw_ostream &O,
+    std::vector<std::vector<std::string>> &TableDrivenOperandPrinters,
+    unsigned &BitsLeft, unsigned &AsmStrBits) {
   Record *AsmWriter = Target.getAsmWriter();
   StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
   bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
 
-  O << "/// getMnemonic - This method is automatically generated by " 
+  O << "/// getMnemonic - This method is automatically generated by "
        "tablegen\n"
        "/// from the instruction set description.\n"
-       "std::pair<const char *, uint64_t> " 
-    << Target.getName() << ClassName << "::getMnemonic(const MCInst *MI) {\n"; 
+       "std::pair<const char *, uint64_t> "
+    << Target.getName() << ClassName << "::getMnemonic(const MCInst *MI) {\n";
 
   // Build an aggregate string, and build a table of offsets into it.
   SequenceToOffsetTable<std::string> StringTable;
@@ -351,11 +351,11 @@ void AsmWriterEmitter::EmitGetMnemonic(
   }
 
   // Figure out how many bits we used for the string index.
-  AsmStrBits = Log2_32_Ceil(MaxStringIdx + 2); 
+  AsmStrBits = Log2_32_Ceil(MaxStringIdx + 2);
 
   // To reduce code size, we compactify common instructions into a few bits
   // in the opcode-indexed table.
-  BitsLeft = OpcodeInfoBits - AsmStrBits; 
+  BitsLeft = OpcodeInfoBits - AsmStrBits;
 
   while (true) {
     std::vector<std::string> UniqueOperandCommands;
@@ -435,48 +435,48 @@ void AsmWriterEmitter::EmitGetMnemonic(
     ++Table;
   }
 
-  O << "  // Emit the opcode for the instruction.\n"; 
-  O << BitsString; 
- 
-  // Return mnemonic string and bits. 
-  O << "  return {AsmStrs+(Bits & " << (1 << AsmStrBits) - 1 
-    << ")-1, Bits};\n\n"; 
- 
-  O << "}\n"; 
-} 
- 
-/// EmitPrintInstruction - Generate the code for the "printInstruction" method 
-/// implementation. Destroys all instances of AsmWriterInst information, by 
-/// clearing the Instructions vector. 
-void AsmWriterEmitter::EmitPrintInstruction( 
-    raw_ostream &O, 
-    std::vector<std::vector<std::string>> &TableDrivenOperandPrinters, 
-    unsigned &BitsLeft, unsigned &AsmStrBits) { 
-  const unsigned OpcodeInfoBits = 64; 
-  Record *AsmWriter = Target.getAsmWriter(); 
-  StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 
-  bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); 
- 
-  O << "/// printInstruction - This method is automatically generated by " 
-       "tablegen\n" 
-       "/// from the instruction set description.\n" 
-       "void " 
-    << Target.getName() << ClassName 
-    << "::printInstruction(const MCInst *MI, uint64_t Address, " 
-    << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") 
-    << "raw_ostream &O) {\n"; 
- 
+  O << "  // Emit the opcode for the instruction.\n";
+  O << BitsString;
+
+  // Return mnemonic string and bits.
+  O << "  return {AsmStrs+(Bits & " << (1 << AsmStrBits) - 1
+    << ")-1, Bits};\n\n";
+
+  O << "}\n";
+}
+
+/// EmitPrintInstruction - Generate the code for the "printInstruction" method
+/// implementation. Destroys all instances of AsmWriterInst information, by
+/// clearing the Instructions vector.
+void AsmWriterEmitter::EmitPrintInstruction(
+    raw_ostream &O,
+    std::vector<std::vector<std::string>> &TableDrivenOperandPrinters,
+    unsigned &BitsLeft, unsigned &AsmStrBits) {
+  const unsigned OpcodeInfoBits = 64;
+  Record *AsmWriter = Target.getAsmWriter();
+  StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
+  bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
+
+  O << "/// printInstruction - This method is automatically generated by "
+       "tablegen\n"
+       "/// from the instruction set description.\n"
+       "void "
+    << Target.getName() << ClassName
+    << "::printInstruction(const MCInst *MI, uint64_t Address, "
+    << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
+    << "raw_ostream &O) {\n";
+
   // Emit the initial tab character.
   O << "  O << \"\\t\";\n\n";
 
   // Emit the starting string.
-  O << "  auto MnemonicInfo = getMnemonic(MI);\n\n"; 
-  O << "  O << MnemonicInfo.first;\n\n"; 
+  O << "  auto MnemonicInfo = getMnemonic(MI);\n\n";
+  O << "  O << MnemonicInfo.first;\n\n";
+
+  O << "  uint" << ((BitsLeft < (OpcodeInfoBits - 32)) ? 64 : 32)
+    << "_t Bits = MnemonicInfo.second;\n"
+    << "  assert(Bits != 0 && \"Cannot print this instruction.\");\n";
 
-  O << "  uint" << ((BitsLeft < (OpcodeInfoBits - 32)) ? 64 : 32) 
-    << "_t Bits = MnemonicInfo.second;\n" 
-    << "  assert(Bits != 0 && \"Cannot print this instruction.\");\n"; 
- 
   // Output the table driven operand information.
   BitsLeft = OpcodeInfoBits-AsmStrBits;
   for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
@@ -521,8 +521,8 @@ void AsmWriterEmitter::EmitPrintInstruction(
   }
 
   // Okay, delete instructions with no operand info left.
-  llvm::erase_if(Instructions, 
-                 [](AsmWriterInst &Inst) { return Inst.Operands.empty(); }); 
+  llvm::erase_if(Instructions,
+                 [](AsmWriterInst &Inst) { return Inst.Operands.empty(); });
 
   // Because this is a vector, we want to emit from the end.  Reverse all of the
   // elements in the vector.
@@ -713,7 +713,7 @@ public:
         ++Next;
     } else {
       // $name, just eat the usual suspects.
-      while (I != End && (isAlnum(*I) || *I == '_')) 
+      while (I != End && (isAlnum(*I) || *I == '_'))
         ++I;
       Next = I;
     }
@@ -1260,10 +1260,10 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
       << "    break;\n";
 
     for (unsigned i = 0; i < MCOpPredicates.size(); ++i) {
-      StringRef MCOpPred = MCOpPredicates[i]->getValueAsString("MCOperandPredicate"); 
-      O << "  case " << i + 1 << ": {\n" 
-        << MCOpPred.data() << "\n" 
-        << "    }\n"; 
+      StringRef MCOpPred = MCOpPredicates[i]->getValueAsString("MCOperandPredicate");
+      O << "  case " << i + 1 << ": {\n"
+        << MCOpPred.data() << "\n"
+        << "    }\n";
     }
     O << "  }\n"
       << "}\n\n";
@@ -1287,11 +1287,11 @@ AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) {
 }
 
 void AsmWriterEmitter::run(raw_ostream &O) {
-  std::vector<std::vector<std::string>> TableDrivenOperandPrinters; 
-  unsigned BitsLeft = 0; 
-  unsigned AsmStrBits = 0; 
-  EmitGetMnemonic(O, TableDrivenOperandPrinters, BitsLeft, AsmStrBits); 
-  EmitPrintInstruction(O, TableDrivenOperandPrinters, BitsLeft, AsmStrBits); 
+  std::vector<std::vector<std::string>> TableDrivenOperandPrinters;
+  unsigned BitsLeft = 0;
+  unsigned AsmStrBits = 0;
+  EmitGetMnemonic(O, TableDrivenOperandPrinters, BitsLeft, AsmStrBits);
+  EmitPrintInstruction(O, TableDrivenOperandPrinters, BitsLeft, AsmStrBits);
   EmitGetRegisterName(O);
   EmitPrintAliasInstruction(O);
 }
diff --git a/contrib/libs/llvm12/utils/TableGen/AsmWriterInst.cpp b/contrib/libs/llvm12/utils/TableGen/AsmWriterInst.cpp
index 76d05e3c2c..cf24f79334 100644
--- a/contrib/libs/llvm12/utils/TableGen/AsmWriterInst.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/AsmWriterInst.cpp
@@ -18,7 +18,7 @@
 
 using namespace llvm;
 
-static bool isIdentChar(char C) { return isAlnum(C) || C == '_'; } 
+static bool isIdentChar(char C) { return isAlnum(C) || C == '_'; }
 
 std::string AsmWriterOperand::getCode(bool PassSubtarget) const {
   if (OperandType == isLiteralTextOperand) {
diff --git a/contrib/libs/llvm12/utils/TableGen/CallingConvEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/CallingConvEmitter.cpp
index c11f307032..9e997483d2 100644
--- a/contrib/libs/llvm12/utils/TableGen/CallingConvEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/CallingConvEmitter.cpp
@@ -38,7 +38,7 @@ void CallingConvEmitter::run(raw_ostream &O) {
 
   // Emit prototypes for all of the non-custom CC's so that they can forward ref
   // each other.
-  Records.startTimer("Emit prototypes"); 
+  Records.startTimer("Emit prototypes");
   for (Record *CC : CCs) {
     if (!CC->getValueAsBit("Custom")) {
       unsigned Pad = CC->getName().size();
@@ -57,7 +57,7 @@ void CallingConvEmitter::run(raw_ostream &O) {
   }
 
   // Emit each non-custom calling convention description in full.
-  Records.startTimer("Emit full descriptions"); 
+  Records.startTimer("Emit full descriptions");
   for (Record *CC : CCs) {
     if (!CC->getValueAsBit("Custom"))
       EmitCallingConv(CC, O);
@@ -87,7 +87,7 @@ void CallingConvEmitter::EmitCallingConv(Record *CC, raw_ostream &O) {
     EmitAction(CCActions->getElementAsRecord(i), 2, O);
   }
   
-  O << "\n  return true; // CC didn't match.\n"; 
+  O << "\n  return true; // CC didn't match.\n";
   O << "}\n";
 }
 
@@ -240,11 +240,11 @@ void CallingConvEmitter::EmitAction(Record *Action,
         O << IndentStr << "LocInfo = CCValAssign::FPExt;\n";
       } else {
         O << IndentStr << "if (ArgFlags.isSExt())\n"
-          << IndentStr << "  LocInfo = CCValAssign::SExt;\n" 
+          << IndentStr << "  LocInfo = CCValAssign::SExt;\n"
           << IndentStr << "else if (ArgFlags.isZExt())\n"
-          << IndentStr << "  LocInfo = CCValAssign::ZExt;\n" 
+          << IndentStr << "  LocInfo = CCValAssign::ZExt;\n"
           << IndentStr << "else\n"
-          << IndentStr << "  LocInfo = CCValAssign::AExt;\n"; 
+          << IndentStr << "  LocInfo = CCValAssign::AExt;\n";
       }
     } else if (Action->isSubClassOf("CCPromoteToUpperBitsInType")) {
       Record *DestTy = Action->getValueAsDef("DestTy");
@@ -256,11 +256,11 @@ void CallingConvEmitter::EmitAction(Record *Action,
                         "point");
       } else {
         O << IndentStr << "if (ArgFlags.isSExt())\n"
-          << IndentStr << "  LocInfo = CCValAssign::SExtUpper;\n" 
+          << IndentStr << "  LocInfo = CCValAssign::SExtUpper;\n"
           << IndentStr << "else if (ArgFlags.isZExt())\n"
-          << IndentStr << "  LocInfo = CCValAssign::ZExtUpper;\n" 
+          << IndentStr << "  LocInfo = CCValAssign::ZExtUpper;\n"
           << IndentStr << "else\n"
-          << IndentStr << "  LocInfo = CCValAssign::AExtUpper;\n"; 
+          << IndentStr << "  LocInfo = CCValAssign::AExtUpper;\n";
       }
     } else if (Action->isSubClassOf("CCBitConvertToType")) {
       Record *DestTy = Action->getValueAsDef("DestTy");
@@ -284,7 +284,7 @@ void CallingConvEmitter::EmitAction(Record *Action,
       O << IndentStr
         << "if (" << Action->getValueAsString("FuncName") << "(ValNo, ValVT, "
         << "LocVT, LocInfo, ArgFlags, State))\n";
-      O << IndentStr << "  return false;\n"; 
+      O << IndentStr << "  return false;\n";
     } else {
       errs() << *Action;
       PrintFatalError(Action->getLoc(), "Unknown CCAction!");
diff --git a/contrib/libs/llvm12/utils/TableGen/CodeEmitterGen.cpp b/contrib/libs/llvm12/utils/TableGen/CodeEmitterGen.cpp
index b92036616b..0b9a84de05 100644
--- a/contrib/libs/llvm12/utils/TableGen/CodeEmitterGen.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/CodeEmitterGen.cpp
@@ -311,7 +311,7 @@ std::string CodeEmitterGen::getInstructionCaseForEncoding(Record *R, Record *Enc
   for (const RecordVal &RV : EncodingDef->getValues()) {
     // Ignore fixed fields in the record, we're looking for values like:
     //    bits<5> RST = { ?, ?, ?, ?, ? };
-    if (RV.isNonconcreteOK() || RV.getValue()->isComplete()) 
+    if (RV.isNonconcreteOK() || RV.getValue()->isComplete())
       continue;
 
     AddCodeToMergeInOperand(R, BI, std::string(RV.getName()), NumberedOp,
@@ -483,7 +483,7 @@ void CodeEmitterGen::run(raw_ostream &o) {
       << "    Inst = Inst.zext(" << BitWidth << ");\n"
       << "  if (Scratch.getBitWidth() != " << BitWidth << ")\n"
       << "    Scratch = Scratch.zext(" << BitWidth << ");\n"
-      << "  LoadIntFromMemory(Inst, (uint8_t *)&InstBits[opcode * " << NumWords 
+      << "  LoadIntFromMemory(Inst, (uint8_t *)&InstBits[opcode * " << NumWords
       << "], " << NumBytes << ");\n"
       << "  APInt &Value = Inst;\n"
       << "  APInt &op = Scratch;\n"
@@ -643,9 +643,9 @@ void CodeEmitterGen::run(raw_ostream &o) {
     << "    report_fatal_error(Msg.str());\n"
     << "  }\n"
     << "#else\n"
-    << "  // Silence unused variable warning on targets that don't use MCII for " 
+    << "  // Silence unused variable warning on targets that don't use MCII for "
        "other purposes (e.g. BPF).\n"
-    << "  (void)MCII;\n" 
+    << "  (void)MCII;\n"
     << "#endif // NDEBUG\n";
   o << "}\n";
   o << "#endif\n";
diff --git a/contrib/libs/llvm12/utils/TableGen/CodeGenDAGPatterns.cpp b/contrib/libs/llvm12/utils/TableGen/CodeGenDAGPatterns.cpp
index 742fa65cdf..1ca4a68eb1 100644
--- a/contrib/libs/llvm12/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -507,9 +507,9 @@ bool TypeInfer::EnforceSmallerThan(TypeSetByHwMode &Small,
     // Always treat non-scalable MVTs as smaller than scalable MVTs for the
     // purposes of ordering.
     auto ASize = std::make_tuple(A.isScalableVector(), A.getScalarSizeInBits(),
-                                 A.getSizeInBits().getKnownMinSize()); 
+                                 A.getSizeInBits().getKnownMinSize());
     auto BSize = std::make_tuple(B.isScalableVector(), B.getScalarSizeInBits(),
-                                 B.getSizeInBits().getKnownMinSize()); 
+                                 B.getSizeInBits().getKnownMinSize());
     return ASize < BSize;
   };
   auto SameKindLE = [](MVT A, MVT B) -> bool {
@@ -520,10 +520,10 @@ bool TypeInfer::EnforceSmallerThan(TypeSetByHwMode &Small,
         std::make_tuple(B.isVector(), B.isScalableVector()))
       return false;
 
-    return std::make_tuple(A.getScalarSizeInBits(), 
-                           A.getSizeInBits().getKnownMinSize()) <= 
-           std::make_tuple(B.getScalarSizeInBits(), 
-                           B.getSizeInBits().getKnownMinSize()); 
+    return std::make_tuple(A.getScalarSizeInBits(),
+                           A.getSizeInBits().getKnownMinSize()) <=
+           std::make_tuple(B.getScalarSizeInBits(),
+                           B.getSizeInBits().getKnownMinSize());
   };
 
   for (unsigned M : Modes) {
@@ -730,14 +730,14 @@ bool TypeInfer::EnforceSameSize(TypeSetByHwMode &A, TypeSetByHwMode &B) {
   if (B.empty())
     Changed |= EnforceAny(B);
 
-  auto NoSize = [](const SmallSet<TypeSize, 2> &Sizes, MVT T) -> bool { 
+  auto NoSize = [](const SmallSet<TypeSize, 2> &Sizes, MVT T) -> bool {
     return !Sizes.count(T.getSizeInBits());
   };
 
   for (unsigned M : union_modes(A, B)) {
     TypeSetByHwMode::SetType &AS = A.get(M);
     TypeSetByHwMode::SetType &BS = B.get(M);
-    SmallSet<TypeSize, 2> AN, BN; 
+    SmallSet<TypeSize, 2> AN, BN;
 
     for (MVT T : AS)
       AN.insert(T.getSizeInBits());
@@ -873,7 +873,7 @@ bool TreePredicateFn::hasPredCode() const {
 }
 
 std::string TreePredicateFn::getPredCode() const {
-  std::string Code; 
+  std::string Code;
 
   if (!isLoad() && !isStore() && !isAtomic()) {
     Record *MemoryVT = getMemoryVT();
@@ -2390,7 +2390,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
         MVT::SimpleValueType VT = P.second.SimpleTy;
         if (VT == MVT::iPTR || VT == MVT::iPTRAny)
           continue;
-        unsigned Size = MVT(VT).getFixedSizeInBits(); 
+        unsigned Size = MVT(VT).getFixedSizeInBits();
         // Make sure that the value is representable for this type.
         if (Size >= 32)
           continue;
@@ -3088,7 +3088,7 @@ CodeGenDAGPatterns::CodeGenDAGPatterns(RecordKeeper &R,
   VerifyInstructionFlags();
 }
 
-Record *CodeGenDAGPatterns::getSDNodeNamed(StringRef Name) const { 
+Record *CodeGenDAGPatterns::getSDNodeNamed(StringRef Name) const {
   Record *N = Records.getDef(Name);
   if (!N || !N->isSubClassOf("SDNode"))
     PrintFatalError("Error getting SDNode '" + Name + "'!");
@@ -3591,9 +3591,9 @@ static bool hasNullFragReference(DagInit *DI) {
   if (Operator->getName() == "null_frag") return true;
   // If any of the arguments reference the null fragment, return true.
   for (unsigned i = 0, e = DI->getNumArgs(); i != e; ++i) {
-    if (auto Arg = dyn_cast<DefInit>(DI->getArg(i))) 
-      if (Arg->getDef()->getName() == "null_frag") 
-        return true; 
+    if (auto Arg = dyn_cast<DefInit>(DI->getArg(i)))
+      if (Arg->getDef()->getName() == "null_frag")
+        return true;
     DagInit *Arg = dyn_cast<DagInit>(DI->getArg(i));
     if (Arg && hasNullFragReference(Arg))
       return true;
@@ -3701,11 +3701,11 @@ void CodeGenDAGPatterns::parseInstructionPattern(
   for (unsigned i = 0; i != NumResults; ++i) {
     if (i == CGI.Operands.size()) {
       const std::string &OpName =
-          llvm::find_if( 
-              InstResults, 
-              [](const std::pair<std::string, TreePatternNodePtr> &P) { 
-                return P.second; 
-              }) 
+          llvm::find_if(
+              InstResults,
+              [](const std::pair<std::string, TreePatternNodePtr> &P) {
+                return P.second;
+              })
               ->first;
 
       I.error("'" + OpName + "' set but does not appear in operand list!");
@@ -4294,7 +4294,7 @@ void CodeGenDAGPatterns::ExpandHwModeBasedTypes() {
 
     std::vector<Predicate> Preds = P.Predicates;
     const std::vector<Predicate> &MC = ModeChecks[Mode];
-    llvm::append_range(Preds, MC); 
+    llvm::append_range(Preds, MC);
     PatternsToMatch.emplace_back(P.getSrcRecord(), Preds, std::move(NewSrc),
                                  std::move(NewDst), P.getDstRegs(),
                                  P.getAddedComplexity(), Record::getNewUID(),
diff --git a/contrib/libs/llvm12/utils/TableGen/CodeGenDAGPatterns.h b/contrib/libs/llvm12/utils/TableGen/CodeGenDAGPatterns.h
index 42e2c2ff67..bc939fe9ac 100644
--- a/contrib/libs/llvm12/utils/TableGen/CodeGenDAGPatterns.h
+++ b/contrib/libs/llvm12/utils/TableGen/CodeGenDAGPatterns.h
@@ -188,7 +188,7 @@ private:
 
 struct TypeSetByHwMode : public InfoByHwMode<MachineValueTypeSet> {
   using SetType = MachineValueTypeSet;
-  SmallVector<unsigned, 16> AddrSpaces; 
+  SmallVector<unsigned, 16> AddrSpaces;
 
   TypeSetByHwMode() = default;
   TypeSetByHwMode(const TypeSetByHwMode &VTS) = default;
@@ -1176,7 +1176,7 @@ public:
   const CodeGenTarget &getTargetInfo() const { return Target; }
   const TypeSetByHwMode &getLegalTypes() const { return LegalVTS; }
 
-  Record *getSDNodeNamed(StringRef Name) const; 
+  Record *getSDNodeNamed(StringRef Name) const;
 
   const SDNodeInfo &getSDNodeInfo(Record *R) const {
     auto F = SDNodes.find(R);
diff --git a/contrib/libs/llvm12/utils/TableGen/CodeGenInstruction.cpp b/contrib/libs/llvm12/utils/TableGen/CodeGenInstruction.cpp
index 042cbb5e62..960fe08677 100644
--- a/contrib/libs/llvm12/utils/TableGen/CodeGenInstruction.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/CodeGenInstruction.cpp
@@ -472,7 +472,7 @@ HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const {
 /// include text from the specified variant, returning the new string.
 std::string CodeGenInstruction::
 FlattenAsmStringVariants(StringRef Cur, unsigned Variant) {
-  std::string Res; 
+  std::string Res;
 
   for (;;) {
     // Find the start of the next variant string.
diff --git a/contrib/libs/llvm12/utils/TableGen/CodeGenIntrinsics.h b/contrib/libs/llvm12/utils/TableGen/CodeGenIntrinsics.h
index af876f1ad8..c469f662a4 100644
--- a/contrib/libs/llvm12/utils/TableGen/CodeGenIntrinsics.h
+++ b/contrib/libs/llvm12/utils/TableGen/CodeGenIntrinsics.h
@@ -148,7 +148,7 @@ struct CodeGenIntrinsic {
   enum ArgAttrKind {
     NoCapture,
     NoAlias,
-    NoUndef, 
+    NoUndef,
     Returned,
     ReadOnly,
     WriteOnly,
@@ -177,13 +177,13 @@ struct CodeGenIntrinsic {
     return Properties & (1 << Prop);
   }
 
-  /// Goes through all IntrProperties that have IsDefault 
-  /// value set and sets the property. 
-  void setDefaultProperties(Record *R, std::vector<Record *> DefaultProperties); 
- 
-  /// Helper function to set property \p Name to true; 
-  void setProperty(Record *R); 
- 
+  /// Goes through all IntrProperties that have IsDefault
+  /// value set and sets the property.
+  void setDefaultProperties(Record *R, std::vector<Record *> DefaultProperties);
+
+  /// Helper function to set property \p Name to true;
+  void setProperty(Record *R);
+
   /// Returns true if the parameter at \p ParamIdx is a pointer type. Returns
   /// false if the parameter is not a pointer, or \p ParamIdx is greater than
   /// the size of \p IS.ParamVTs.
@@ -193,7 +193,7 @@ struct CodeGenIntrinsic {
 
   bool isParamImmArg(unsigned ParamIdx) const;
 
-  CodeGenIntrinsic(Record *R, std::vector<Record *> DefaultProperties); 
+  CodeGenIntrinsic(Record *R, std::vector<Record *> DefaultProperties);
 };
 
 class CodeGenIntrinsicTable {
diff --git a/contrib/libs/llvm12/utils/TableGen/CodeGenMapTable.cpp b/contrib/libs/llvm12/utils/TableGen/CodeGenMapTable.cpp
index f3edd18211..289a20a96f 100644
--- a/contrib/libs/llvm12/utils/TableGen/CodeGenMapTable.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/CodeGenMapTable.cpp
@@ -144,15 +144,15 @@ public:
     }
   }
 
-  const std::string &getName() const { return Name; } 
+  const std::string &getName() const { return Name; }
 
-  const std::string &getFilterClass() const { return FilterClass; } 
+  const std::string &getFilterClass() const { return FilterClass; }
 
-  ListInit *getRowFields() const { return RowFields; } 
+  ListInit *getRowFields() const { return RowFields; }
 
-  ListInit *getColFields() const { return ColFields; } 
+  ListInit *getColFields() const { return ColFields; }
 
-  ListInit *getKeyCol() const { return KeyCol; } 
+  ListInit *getKeyCol() const { return KeyCol; }
 
   const std::vector<ListInit*> &getValueCols() const {
     return ValueCols;
@@ -190,7 +190,7 @@ private:
 public:
   MapTableEmitter(CodeGenTarget &Target, RecordKeeper &Records, Record *IMRec):
                   Target(Target), InstrMapDesc(IMRec) {
-    const std::string &FilterClass = InstrMapDesc.getFilterClass(); 
+    const std::string &FilterClass = InstrMapDesc.getFilterClass();
     InstrDefs = Records.getAllDerivedDefinitions(FilterClass);
   }
 
@@ -374,7 +374,7 @@ unsigned MapTableEmitter::emitBinSearchTable(raw_ostream &OS) {
   for (unsigned i = 0; i < TotalNumInstr; i++) {
     Record *CurInstr = NumberedInstructions[i]->TheDef;
     std::vector<Record*> ColInstrs = MapTable[CurInstr];
-    std::string OutStr; 
+    std::string OutStr;
     unsigned RelExists = 0;
     if (!ColInstrs.empty()) {
       for (unsigned j = 0; j < NumCol; j++) {
@@ -412,7 +412,7 @@ void MapTableEmitter::emitBinSearch(raw_ostream &OS, unsigned TableSize) {
   OS << "  unsigned start = 0;\n";
   OS << "  unsigned end = " << TableSize << ";\n";
   OS << "  while (start < end) {\n";
-  OS << "    mid = start + (end - start) / 2;\n"; 
+  OS << "    mid = start + (end - start) / 2;\n";
   OS << "    if (Opcode == " << InstrMapDesc.getName() << "Table[mid][0]) {\n";
   OS << "      break;\n";
   OS << "    }\n";
diff --git a/contrib/libs/llvm12/utils/TableGen/CodeGenRegisters.cpp b/contrib/libs/llvm12/utils/TableGen/CodeGenRegisters.cpp
index 48e91b05cd..f9a7ba6bba 100644
--- a/contrib/libs/llvm12/utils/TableGen/CodeGenRegisters.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/CodeGenRegisters.cpp
@@ -196,7 +196,7 @@ void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
   }
 }
 
-StringRef CodeGenRegister::getName() const { 
+StringRef CodeGenRegister::getName() const {
   assert(TheDef && "no def");
   return TheDef->getName();
 }
@@ -496,10 +496,10 @@ void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
       assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct");
       for (CodeGenRegister *SubReg : Cand->ExplicitSubRegs) {
         if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) {
-          if (SubRegIdx->ConcatenationOf.empty()) 
+          if (SubRegIdx->ConcatenationOf.empty())
             Parts.push_back(SubRegIdx);
-          else 
-            append_range(Parts, SubRegIdx->ConcatenationOf); 
+          else
+            append_range(Parts, SubRegIdx->ConcatenationOf);
         } else {
           // Sub-register doesn't exist.
           Parts.clear();
@@ -742,8 +742,8 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
       TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1) {
   GeneratePressureSet = R->getValueAsBit("GeneratePressureSet");
   std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
-  if (TypeList.empty()) 
-    PrintFatalError(R->getLoc(), "RegTypes list must not be empty!"); 
+  if (TypeList.empty())
+    PrintFatalError(R->getLoc(), "RegTypes list must not be empty!");
   for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
     Record *Type = TypeList[i];
     if (!Type->isSubClassOf("ValueType"))
@@ -998,8 +998,8 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
                       const CodeGenRegisterClass *B) {
     // If there are multiple, identical register classes, prefer the original
     // register class.
-    if (A == B) 
-      return false; 
+    if (A == B)
+      return false;
     if (A->getMembers().size() == B->getMembers().size())
       return A == this;
     return A->getMembers().size() > B->getMembers().size();
@@ -1237,7 +1237,7 @@ CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) {
 
 const CodeGenSubRegIndex *
 CodeGenRegBank::findSubRegIdx(const Record* Def) const {
-  return Def2SubRegIdx.lookup(Def); 
+  return Def2SubRegIdx.lookup(Def);
 }
 
 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
@@ -2009,7 +2009,7 @@ void CodeGenRegBank::computeRegUnitSets() {
     if (RCRegUnits.empty())
       continue;
 
-    LLVM_DEBUG(dbgs() << "RC " << RC.getName() << " Units:\n"; 
+    LLVM_DEBUG(dbgs() << "RC " << RC.getName() << " Units:\n";
                for (auto U
                     : RCRegUnits) printRegUnitName(U);
                dbgs() << "\n  UnitSetIDs:");
diff --git a/contrib/libs/llvm12/utils/TableGen/CodeGenRegisters.h b/contrib/libs/llvm12/utils/TableGen/CodeGenRegisters.h
index b6b7e42812..5228e6518f 100644
--- a/contrib/libs/llvm12/utils/TableGen/CodeGenRegisters.h
+++ b/contrib/libs/llvm12/utils/TableGen/CodeGenRegisters.h
@@ -163,7 +163,7 @@ namespace llvm {
 
     CodeGenRegister(Record *R, unsigned Enum);
 
-    StringRef getName() const; 
+    StringRef getName() const;
 
     // Extract more information from TheDef. This is used to build an object
     // graph after all CodeGenRegister objects have been created.
@@ -353,7 +353,7 @@ namespace llvm {
     unsigned getNumValueTypes() const { return VTs.size(); }
 
     bool hasType(const ValueTypeByHwMode &VT) const {
-      return llvm::is_contained(VTs, VT); 
+      return llvm::is_contained(VTs, VT);
     }
 
     const ValueTypeByHwMode &getValueTypeNum(unsigned VTNum) const {
diff --git a/contrib/libs/llvm12/utils/TableGen/CodeGenSchedule.cpp b/contrib/libs/llvm12/utils/TableGen/CodeGenSchedule.cpp
index 0e1161d79d..b20eb6eff4 100644
--- a/contrib/libs/llvm12/utils/TableGen/CodeGenSchedule.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/CodeGenSchedule.cpp
@@ -86,7 +86,7 @@ struct InstRegexOp : public SetTheory::Operator {
     auto Pseudos = Instructions.slice(NumGeneric, NumPseudos);
     auto NonPseudos = Instructions.slice(NumGeneric + NumPseudos);
 
-    for (Init *Arg : Expr->getArgs()) { 
+    for (Init *Arg : Expr->getArgs()) {
       StringInit *SI = dyn_cast<StringInit>(Arg);
       if (!SI)
         PrintFatalError(Loc, "instregex requires pattern string: " +
@@ -248,7 +248,7 @@ void CodeGenSchedModels::checkSTIPredicates() const {
     }
 
     PrintError(R->getLoc(), "STIPredicate " + Name + " multiply declared.");
-    PrintFatalNote(It->second->getLoc(), "Previous declaration was here."); 
+    PrintFatalNote(It->second->getLoc(), "Previous declaration was here.");
   }
 
   // Disallow InstructionEquivalenceClasses with an empty instruction list.
@@ -283,7 +283,7 @@ static APInt constructOperandMask(ArrayRef<int64_t> Indices) {
 
 static void
 processSTIPredicate(STIPredicateFunction &Fn,
-                    const ProcModelMapTy &ProcModelMap) { 
+                    const ProcModelMapTy &ProcModelMap) {
   DenseMap<const Record *, unsigned> Opcode2Index;
   using OpcodeMapPair = std::pair<const Record *, OpcodeInfo>;
   std::vector<OpcodeMapPair> OpcodeMappings;
@@ -453,8 +453,8 @@ void CodeGenSchedModels::checkMCInstPredicates() const {
 
     PrintError(TIIPred->getLoc(),
                "TIIPredicate " + Name + " is multiply defined.");
-    PrintFatalNote(It->second->getLoc(), 
-                   " Previous definition of " + Name + " was here."); 
+    PrintFatalNote(It->second->getLoc(),
+                   " Previous definition of " + Name + " was here.");
   }
 }
 
@@ -950,9 +950,9 @@ void CodeGenSchedModels::collectSchedClasses() {
     }
     // If ProcIndices contains zero, the class applies to all processors.
     LLVM_DEBUG({
-      if (!llvm::is_contained(ProcIndices, 0)) { 
+      if (!llvm::is_contained(ProcIndices, 0)) {
         for (const CodeGenProcModel &PM : ProcModels) {
-          if (!llvm::is_contained(ProcIndices, PM.Index)) 
+          if (!llvm::is_contained(ProcIndices, PM.Index))
             dbgs() << "No machine model for " << Inst->TheDef->getName()
                    << " on processor " << PM.ModelName << '\n';
         }
@@ -1080,14 +1080,14 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) {
             if (RWD->getValueAsDef("SchedModel") == RWModelDef &&
                 RWModelDef->getValueAsBit("FullInstRWOverlapCheck")) {
               assert(!InstDefs.empty()); // Checked at function start.
-              PrintError( 
-                  InstRWDef->getLoc(), 
-                  "Overlapping InstRW definition for \"" + 
-                      InstDefs.front()->getName() + 
-                      "\" also matches previous \"" + 
-                      RWD->getValue("Instrs")->getValue()->getAsString() + 
-                      "\"."); 
-              PrintFatalNote(RWD->getLoc(), "Previous match was here."); 
+              PrintError(
+                  InstRWDef->getLoc(),
+                  "Overlapping InstRW definition for \"" +
+                      InstDefs.front()->getName() +
+                      "\" also matches previous \"" +
+                      RWD->getValue("Instrs")->getValue()->getAsString() +
+                      "\".");
+              PrintFatalNote(RWD->getLoc(), "Previous match was here.");
             }
           }
           LLVM_DEBUG(dbgs() << "InstRW: Reuse SC " << OldSCIdx << ":"
@@ -1116,13 +1116,13 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) {
       for (Record *OldRWDef : SchedClasses[OldSCIdx].InstRWs) {
         if (OldRWDef->getValueAsDef("SchedModel") == RWModelDef) {
           assert(!InstDefs.empty()); // Checked at function start.
-          PrintError( 
-              InstRWDef->getLoc(), 
-              "Overlapping InstRW definition for \"" + 
-                  InstDefs.front()->getName() + "\" also matches previous \"" + 
-                  OldRWDef->getValue("Instrs")->getValue()->getAsString() + 
-                  "\"."); 
-          PrintFatalNote(OldRWDef->getLoc(), "Previous match was here."); 
+          PrintError(
+              InstRWDef->getLoc(),
+              "Overlapping InstRW definition for \"" +
+                  InstDefs.front()->getName() + "\" also matches previous \"" +
+                  OldRWDef->getValue("Instrs")->getValue()->getAsString() +
+                  "\".");
+          PrintFatalNote(OldRWDef->getLoc(), "Previous match was here.");
         }
         assert(OldRWDef != InstRWDef &&
                "SchedClass has duplicate InstRW def");
@@ -1208,10 +1208,10 @@ void CodeGenSchedModels::collectProcItinRW() {
 
 // Gather the unsupported features for processor models.
 void CodeGenSchedModels::collectProcUnsupportedFeatures() {
-  for (CodeGenProcModel &ProcModel : ProcModels) 
-    append_range( 
-        ProcModel.UnsupportedFeaturesDefs, 
-        ProcModel.ModelDef->getValueAsListOfDefs("UnsupportedFeatures")); 
+  for (CodeGenProcModel &ProcModel : ProcModels)
+    append_range(
+        ProcModel.UnsupportedFeaturesDefs,
+        ProcModel.ModelDef->getValueAsListOfDefs("UnsupportedFeatures"));
 }
 
 /// Infer new classes from existing classes. In the process, this may create new
@@ -1247,7 +1247,7 @@ void CodeGenSchedModels::inferFromItinClass(Record *ItinClassDef,
     bool HasMatch = false;
     for (const Record *Rec : PM.ItinRWDefs) {
       RecVec Matched = Rec->getValueAsListOfDefs("MatchedItinClasses");
-      if (!llvm::is_contained(Matched, ItinClassDef)) 
+      if (!llvm::is_contained(Matched, ItinClassDef))
         continue;
       if (HasMatch)
         PrintFatalError(Rec->getLoc(), "Duplicate itinerary class "
@@ -1280,7 +1280,7 @@ void CodeGenSchedModels::inferFromInstRWs(unsigned SCIdx) {
     findRWs(Rec->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
     unsigned PIdx = getProcModel(Rec->getValueAsDef("SchedModel")).Index;
     inferFromRW(Writes, Reads, SCIdx, PIdx); // May mutate SchedClasses.
-    SchedClasses[SCIdx].InstRWProcIndices.insert(PIdx); 
+    SchedClasses[SCIdx].InstRWProcIndices.insert(PIdx);
   }
 }
 
@@ -1313,13 +1313,13 @@ struct PredTransition {
   SmallVector<PredCheck, 4> PredTerm;
   SmallVector<SmallVector<unsigned,4>, 16> WriteSequences;
   SmallVector<SmallVector<unsigned,4>, 16> ReadSequences;
-  unsigned ProcIndex = 0; 
- 
-  PredTransition() = default; 
-  PredTransition(ArrayRef<PredCheck> PT, unsigned ProcId) { 
-    PredTerm.assign(PT.begin(), PT.end()); 
-    ProcIndex = ProcId; 
-  } 
+  unsigned ProcIndex = 0;
+
+  PredTransition() = default;
+  PredTransition(ArrayRef<PredCheck> PT, unsigned ProcId) {
+    PredTerm.assign(PT.begin(), PT.end());
+    ProcIndex = ProcId;
+  }
 };
 
 // Encapsulate a set of partially constructed transitions.
@@ -1332,18 +1332,18 @@ public:
 
   PredTransitions(CodeGenSchedModels &sm): SchedModels(sm) {}
 
-  bool substituteVariantOperand(const SmallVectorImpl<unsigned> &RWSeq, 
+  bool substituteVariantOperand(const SmallVectorImpl<unsigned> &RWSeq,
                                 bool IsRead, unsigned StartIdx);
 
-  bool substituteVariants(const PredTransition &Trans); 
+  bool substituteVariants(const PredTransition &Trans);
 
 #ifndef NDEBUG
   void dump() const;
 #endif
 
 private:
-  bool mutuallyExclusive(Record *PredDef, ArrayRef<Record *> Preds, 
-                         ArrayRef<PredCheck> Term); 
+  bool mutuallyExclusive(Record *PredDef, ArrayRef<Record *> Preds,
+                         ArrayRef<PredCheck> Term);
   void getIntersectingVariants(
     const CodeGenSchedRW &SchedRW, unsigned TransIdx,
     std::vector<TransVariant> &IntersectingVariants);
@@ -1362,7 +1362,7 @@ private:
 // are always checked in the order they are defined in the .td file. Later
 // conditions implicitly negate any prior condition.
 bool PredTransitions::mutuallyExclusive(Record *PredDef,
-                                        ArrayRef<Record *> Preds, 
+                                        ArrayRef<Record *> Preds,
                                         ArrayRef<PredCheck> Term) {
   for (const PredCheck &PC: Term) {
     if (PC.Predicate == PredDef)
@@ -1373,49 +1373,49 @@ bool PredTransitions::mutuallyExclusive(Record *PredDef,
     RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants");
     if (any_of(Variants, [PredDef](const Record *R) {
           return R->getValueAsDef("Predicate") == PredDef;
-        })) { 
-      // To check if PredDef is mutually exclusive with PC we also need to 
-      // check that PC.Predicate is exclusive with all predicates from variant 
-      // we're expanding. Consider following RW sequence with two variants 
-      // (1 & 2), where A, B and C are predicates from corresponding SchedVars: 
-      // 
-      // 1:A/B - 2:C/B 
-      // 
-      // Here C is not mutually exclusive with variant (1), because A doesn't 
-      // exist in variant (2). This means we have possible transitions from A 
-      // to C and from A to B, and fully expanded sequence would look like: 
-      // 
-      // if (A & C) return ...; 
-      // if (A & B) return ...; 
-      // if (B) return ...; 
-      // 
-      // Now let's consider another sequence: 
-      // 
-      // 1:A/B - 2:A/B 
-      // 
-      // Here A in variant (2) is mutually exclusive with variant (1), because 
-      // A also exists in (2). This means A->B transition is impossible and 
-      // expanded sequence would look like: 
-      // 
-      // if (A) return ...; 
-      // if (B) return ...; 
-      if (!count(Preds, PC.Predicate)) 
-        continue; 
+        })) {
+      // To check if PredDef is mutually exclusive with PC we also need to
+      // check that PC.Predicate is exclusive with all predicates from variant
+      // we're expanding. Consider following RW sequence with two variants
+      // (1 & 2), where A, B and C are predicates from corresponding SchedVars:
+      //
+      // 1:A/B - 2:C/B
+      //
+      // Here C is not mutually exclusive with variant (1), because A doesn't
+      // exist in variant (2). This means we have possible transitions from A
+      // to C and from A to B, and fully expanded sequence would look like:
+      //
+      // if (A & C) return ...;
+      // if (A & B) return ...;
+      // if (B) return ...;
+      //
+      // Now let's consider another sequence:
+      //
+      // 1:A/B - 2:A/B
+      //
+      // Here A in variant (2) is mutually exclusive with variant (1), because
+      // A also exists in (2). This means A->B transition is impossible and
+      // expanded sequence would look like:
+      //
+      // if (A) return ...;
+      // if (B) return ...;
+      if (!count(Preds, PC.Predicate))
+        continue;
       return true;
     }
   }
   return false;
 }
 
-static std::vector<Record *> getAllPredicates(ArrayRef<TransVariant> Variants, 
-                                              unsigned ProcId) { 
-  std::vector<Record *> Preds; 
-  for (auto &Variant : Variants) { 
-    if (!Variant.VarOrSeqDef->isSubClassOf("SchedVar")) 
-      continue; 
-    Preds.push_back(Variant.VarOrSeqDef->getValueAsDef("Predicate")); 
+static std::vector<Record *> getAllPredicates(ArrayRef<TransVariant> Variants,
+                                              unsigned ProcId) {
+  std::vector<Record *> Preds;
+  for (auto &Variant : Variants) {
+    if (!Variant.VarOrSeqDef->isSubClassOf("SchedVar"))
+      continue;
+    Preds.push_back(Variant.VarOrSeqDef->getValueAsDef("Predicate"));
   }
-  return Preds; 
+  return Preds;
 }
 
 // Populate IntersectingVariants with any variants or aliased sequences of the
@@ -1434,14 +1434,14 @@ void PredTransitions::getIntersectingVariants(
       Record *ModelDef = SchedRW.TheDef->getValueAsDef("SchedModel");
       VarProcIdx = SchedModels.getProcModel(ModelDef).Index;
     }
-    if (VarProcIdx == 0 || VarProcIdx == TransVec[TransIdx].ProcIndex) { 
-      // Push each variant. Assign TransVecIdx later. 
-      const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants"); 
-      for (Record *VarDef : VarDefs) 
-        Variants.emplace_back(VarDef, SchedRW.Index, VarProcIdx, 0); 
-      if (VarProcIdx == 0) 
-        GenericRW = true; 
-    } 
+    if (VarProcIdx == 0 || VarProcIdx == TransVec[TransIdx].ProcIndex) {
+      // Push each variant. Assign TransVecIdx later.
+      const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");
+      for (Record *VarDef : VarDefs)
+        Variants.emplace_back(VarDef, SchedRW.Index, VarProcIdx, 0);
+      if (VarProcIdx == 0)
+        GenericRW = true;
+    }
   }
   for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
        AI != AE; ++AI) {
@@ -1453,17 +1453,17 @@ void PredTransitions::getIntersectingVariants(
       Record *ModelDef = (*AI)->getValueAsDef("SchedModel");
       AliasProcIdx = SchedModels.getProcModel(ModelDef).Index;
     }
-    if (AliasProcIdx && AliasProcIdx != TransVec[TransIdx].ProcIndex) 
-      continue; 
-    if (!Variants.empty()) { 
-      const CodeGenProcModel &PM = 
-          *(SchedModels.procModelBegin() + AliasProcIdx); 
-      PrintFatalError((*AI)->getLoc(), 
-                      "Multiple variants defined for processor " + 
-                          PM.ModelName + 
-                          " Ensure only one SchedAlias exists per RW."); 
-    } 
- 
+    if (AliasProcIdx && AliasProcIdx != TransVec[TransIdx].ProcIndex)
+      continue;
+    if (!Variants.empty()) {
+      const CodeGenProcModel &PM =
+          *(SchedModels.procModelBegin() + AliasProcIdx);
+      PrintFatalError((*AI)->getLoc(),
+                      "Multiple variants defined for processor " +
+                          PM.ModelName +
+                          " Ensure only one SchedAlias exists per RW.");
+    }
+
     const CodeGenSchedRW &AliasRW =
       SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
 
@@ -1477,17 +1477,17 @@ void PredTransitions::getIntersectingVariants(
     if (AliasProcIdx == 0)
       GenericRW = true;
   }
-  std::vector<Record *> AllPreds = 
-      getAllPredicates(Variants, TransVec[TransIdx].ProcIndex); 
+  std::vector<Record *> AllPreds =
+      getAllPredicates(Variants, TransVec[TransIdx].ProcIndex);
   for (TransVariant &Variant : Variants) {
     // Don't expand variants if the processor models don't intersect.
     // A zero processor index means any processor.
     if (Variant.VarOrSeqDef->isSubClassOf("SchedVar")) {
       Record *PredDef = Variant.VarOrSeqDef->getValueAsDef("Predicate");
-      if (mutuallyExclusive(PredDef, AllPreds, TransVec[TransIdx].PredTerm)) 
+      if (mutuallyExclusive(PredDef, AllPreds, TransVec[TransIdx].PredTerm))
         continue;
     }
- 
+
     if (IntersectingVariants.empty()) {
       // The first variant builds on the existing transition.
       Variant.TransVecIdx = TransIdx;
@@ -1534,7 +1534,7 @@ pushVariant(const TransVariant &VInfo, bool IsRead) {
   if (SchedRW.IsVariadic) {
     unsigned OperIdx = RWSequences.size()-1;
     // Make N-1 copies of this transition's last sequence.
-    RWSequences.reserve(RWSequences.size() + SelectedRWs.size() - 1); 
+    RWSequences.reserve(RWSequences.size() + SelectedRWs.size() - 1);
     RWSequences.insert(RWSequences.end(), SelectedRWs.size() - 1,
                        RWSequences[OperIdx]);
     // Push each of the N elements of the SelectedRWs onto a copy of the last
@@ -1548,7 +1548,7 @@ pushVariant(const TransVariant &VInfo, bool IsRead) {
         ExpandedRWs.push_back(*RWI);
       else
         SchedModels.expandRWSequence(*RWI, ExpandedRWs, IsRead);
-      llvm::append_range(RWSequences[OperIdx], ExpandedRWs); 
+      llvm::append_range(RWSequences[OperIdx], ExpandedRWs);
     }
     assert(OperIdx == RWSequences.size() && "missed a sequence");
   }
@@ -1564,7 +1564,7 @@ pushVariant(const TransVariant &VInfo, bool IsRead) {
       else
         SchedModels.expandRWSequence(*RWI, ExpandedRWs, IsRead);
     }
-    llvm::append_range(Seq, ExpandedRWs); 
+    llvm::append_range(Seq, ExpandedRWs);
   }
 }
 
@@ -1572,9 +1572,9 @@ pushVariant(const TransVariant &VInfo, bool IsRead) {
 // operand. StartIdx is an index into TransVec where partial results
 // starts. RWSeq must be applied to all transitions between StartIdx and the end
 // of TransVec.
-bool PredTransitions::substituteVariantOperand( 
-    const SmallVectorImpl<unsigned> &RWSeq, bool IsRead, unsigned StartIdx) { 
-  bool Subst = false; 
+bool PredTransitions::substituteVariantOperand(
+    const SmallVectorImpl<unsigned> &RWSeq, bool IsRead, unsigned StartIdx) {
+  bool Subst = false;
   // Visit each original RW within the current sequence.
   for (SmallVectorImpl<unsigned>::const_iterator
          RWI = RWSeq.begin(), RWE = RWSeq.end(); RWI != RWE; ++RWI) {
@@ -1584,25 +1584,25 @@ bool PredTransitions::substituteVariantOperand(
     // revisited (TransEnd must be loop invariant).
     for (unsigned TransIdx = StartIdx, TransEnd = TransVec.size();
          TransIdx != TransEnd; ++TransIdx) {
-      // Distribute this partial PredTransition across intersecting variants. 
-      // This will push a copies of TransVec[TransIdx] on the back of TransVec. 
-      std::vector<TransVariant> IntersectingVariants; 
-      getIntersectingVariants(SchedRW, TransIdx, IntersectingVariants); 
-      // Now expand each variant on top of its copy of the transition. 
-      for (const TransVariant &IV : IntersectingVariants) 
-        pushVariant(IV, IsRead); 
-      if (IntersectingVariants.empty()) { 
+      // Distribute this partial PredTransition across intersecting variants.
+      // This will push a copies of TransVec[TransIdx] on the back of TransVec.
+      std::vector<TransVariant> IntersectingVariants;
+      getIntersectingVariants(SchedRW, TransIdx, IntersectingVariants);
+      // Now expand each variant on top of its copy of the transition.
+      for (const TransVariant &IV : IntersectingVariants)
+        pushVariant(IV, IsRead);
+      if (IntersectingVariants.empty()) {
         if (IsRead)
           TransVec[TransIdx].ReadSequences.back().push_back(*RWI);
         else
           TransVec[TransIdx].WriteSequences.back().push_back(*RWI);
         continue;
-      } else { 
-        Subst = true; 
+      } else {
+        Subst = true;
       }
     }
   }
-  return Subst; 
+  return Subst;
 }
 
 // For each variant of a Read/Write in Trans, substitute the sequence of
@@ -1611,13 +1611,13 @@ bool PredTransitions::substituteVariantOperand(
 // predicates should result in linear growth in the total number variants.
 //
 // This is one step in a breadth-first search of nested variants.
-bool PredTransitions::substituteVariants(const PredTransition &Trans) { 
+bool PredTransitions::substituteVariants(const PredTransition &Trans) {
   // Build up a set of partial results starting at the back of
   // PredTransitions. Remember the first new transition.
   unsigned StartIdx = TransVec.size();
-  bool Subst = false; 
-  assert(Trans.ProcIndex != 0); 
-  TransVec.emplace_back(Trans.PredTerm, Trans.ProcIndex); 
+  bool Subst = false;
+  assert(Trans.ProcIndex != 0);
+  TransVec.emplace_back(Trans.PredTerm, Trans.ProcIndex);
 
   // Visit each original write sequence.
   for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator
@@ -1628,7 +1628,7 @@ bool PredTransitions::substituteVariants(const PredTransition &Trans) {
            TransVec.begin() + StartIdx, E = TransVec.end(); I != E; ++I) {
       I->WriteSequences.emplace_back();
     }
-    Subst |= substituteVariantOperand(*WSI, /*IsRead=*/false, StartIdx); 
+    Subst |= substituteVariantOperand(*WSI, /*IsRead=*/false, StartIdx);
   }
   // Visit each original read sequence.
   for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator
@@ -1639,37 +1639,37 @@ bool PredTransitions::substituteVariants(const PredTransition &Trans) {
            TransVec.begin() + StartIdx, E = TransVec.end(); I != E; ++I) {
       I->ReadSequences.emplace_back();
     }
-    Subst |= substituteVariantOperand(*RSI, /*IsRead=*/true, StartIdx); 
-  }
-  return Subst; 
-}
-
-static void addSequences(CodeGenSchedModels &SchedModels, 
-                         const SmallVectorImpl<SmallVector<unsigned, 4>> &Seqs, 
-                         IdxVec &Result, bool IsRead) { 
-  for (const auto &S : Seqs) 
-    if (!S.empty()) 
-      Result.push_back(SchedModels.findOrInsertRW(S, IsRead)); 
-} 
- 
-#ifndef NDEBUG 
-static void dumpRecVec(const RecVec &RV) { 
-  for (const Record *R : RV) 
-    dbgs() << R->getName() << ", "; 
-} 
-#endif 
- 
-static void dumpTransition(const CodeGenSchedModels &SchedModels, 
-                           const CodeGenSchedClass &FromSC, 
-                           const CodeGenSchedTransition &SCTrans, 
-                           const RecVec &Preds) { 
-  LLVM_DEBUG(dbgs() << "Adding transition from " << FromSC.Name << "(" 
-                    << FromSC.Index << ") to " 
-                    << SchedModels.getSchedClass(SCTrans.ToClassIdx).Name << "(" 
-                    << SCTrans.ToClassIdx << ") on pred term: ("; 
-             dumpRecVec(Preds); 
-             dbgs() << ") on processor (" << SCTrans.ProcIndex << ")\n"); 
-} 
+    Subst |= substituteVariantOperand(*RSI, /*IsRead=*/true, StartIdx);
+  }
+  return Subst;
+}
+
+static void addSequences(CodeGenSchedModels &SchedModels,
+                         const SmallVectorImpl<SmallVector<unsigned, 4>> &Seqs,
+                         IdxVec &Result, bool IsRead) {
+  for (const auto &S : Seqs)
+    if (!S.empty())
+      Result.push_back(SchedModels.findOrInsertRW(S, IsRead));
+}
+
+#ifndef NDEBUG
+static void dumpRecVec(const RecVec &RV) {
+  for (const Record *R : RV)
+    dbgs() << R->getName() << ", ";
+}
+#endif
+
+static void dumpTransition(const CodeGenSchedModels &SchedModels,
+                           const CodeGenSchedClass &FromSC,
+                           const CodeGenSchedTransition &SCTrans,
+                           const RecVec &Preds) {
+  LLVM_DEBUG(dbgs() << "Adding transition from " << FromSC.Name << "("
+                    << FromSC.Index << ") to "
+                    << SchedModels.getSchedClass(SCTrans.ToClassIdx).Name << "("
+                    << SCTrans.ToClassIdx << ") on pred term: (";
+             dumpRecVec(Preds);
+             dbgs() << ") on processor (" << SCTrans.ProcIndex << ")\n");
+}
 // Create a new SchedClass for each variant found by inferFromRW. Pass
 static void inferFromTransitions(ArrayRef<PredTransition> LastTransitions,
                                  unsigned FromClassIdx,
@@ -1678,25 +1678,25 @@ static void inferFromTransitions(ArrayRef<PredTransition> LastTransitions,
   // requires creating a new SchedClass.
   for (ArrayRef<PredTransition>::iterator
          I = LastTransitions.begin(), E = LastTransitions.end(); I != E; ++I) {
-    // Variant expansion (substituteVariants) may create unconditional 
-    // transitions. We don't need to build sched classes for them. 
-    if (I->PredTerm.empty()) 
-      continue; 
-    IdxVec OperWritesVariant, OperReadsVariant; 
-    addSequences(SchedModels, I->WriteSequences, OperWritesVariant, false); 
-    addSequences(SchedModels, I->ReadSequences, OperReadsVariant, true); 
+    // Variant expansion (substituteVariants) may create unconditional
+    // transitions. We don't need to build sched classes for them.
+    if (I->PredTerm.empty())
+      continue;
+    IdxVec OperWritesVariant, OperReadsVariant;
+    addSequences(SchedModels, I->WriteSequences, OperWritesVariant, false);
+    addSequences(SchedModels, I->ReadSequences, OperReadsVariant, true);
     CodeGenSchedTransition SCTrans;
- 
-    // Transition should not contain processor indices already assigned to 
-    // InstRWs in this scheduling class. 
-    const CodeGenSchedClass &FromSC = SchedModels.getSchedClass(FromClassIdx); 
-    if (FromSC.InstRWProcIndices.count(I->ProcIndex)) 
-      continue; 
-    SCTrans.ProcIndex = I->ProcIndex; 
+
+    // Transition should not contain processor indices already assigned to
+    // InstRWs in this scheduling class.
+    const CodeGenSchedClass &FromSC = SchedModels.getSchedClass(FromClassIdx);
+    if (FromSC.InstRWProcIndices.count(I->ProcIndex))
+      continue;
+    SCTrans.ProcIndex = I->ProcIndex;
     SCTrans.ToClassIdx =
-        SchedModels.addSchedClass(/*ItinClassDef=*/nullptr, OperWritesVariant, 
-                                  OperReadsVariant, I->ProcIndex); 
- 
+        SchedModels.addSchedClass(/*ItinClassDef=*/nullptr, OperWritesVariant,
+                                  OperReadsVariant, I->ProcIndex);
+
     // The final PredTerm is unique set of predicates guarding the transition.
     RecVec Preds;
     transform(I->PredTerm, std::back_inserter(Preds),
@@ -1704,36 +1704,36 @@ static void inferFromTransitions(ArrayRef<PredTransition> LastTransitions,
                 return P.Predicate;
               });
     Preds.erase(std::unique(Preds.begin(), Preds.end()), Preds.end());
-    dumpTransition(SchedModels, FromSC, SCTrans, Preds); 
+    dumpTransition(SchedModels, FromSC, SCTrans, Preds);
     SCTrans.PredTerm = std::move(Preds);
     SchedModels.getSchedClass(FromClassIdx)
         .Transitions.push_back(std::move(SCTrans));
   }
 }
 
-std::vector<unsigned> CodeGenSchedModels::getAllProcIndices() const { 
-  std::vector<unsigned> ProcIdVec; 
-  for (const auto &PM : ProcModelMap) 
-    if (PM.second != 0) 
-      ProcIdVec.push_back(PM.second); 
-  // The order of the keys (Record pointers) of ProcModelMap are not stable. 
-  // Sort to stabalize the values. 
-  llvm::sort(ProcIdVec); 
-  return ProcIdVec; 
-} 
- 
-static std::vector<PredTransition> 
-makePerProcessorTransitions(const PredTransition &Trans, 
-                            ArrayRef<unsigned> ProcIndices) { 
-  std::vector<PredTransition> PerCpuTransVec; 
-  for (unsigned ProcId : ProcIndices) { 
-    assert(ProcId != 0); 
-    PerCpuTransVec.push_back(Trans); 
-    PerCpuTransVec.back().ProcIndex = ProcId; 
-  } 
-  return PerCpuTransVec; 
-} 
- 
+std::vector<unsigned> CodeGenSchedModels::getAllProcIndices() const {
+  std::vector<unsigned> ProcIdVec;
+  for (const auto &PM : ProcModelMap)
+    if (PM.second != 0)
+      ProcIdVec.push_back(PM.second);
+  // The order of the keys (Record pointers) of ProcModelMap are not stable.
+  // Sort to stabalize the values.
+  llvm::sort(ProcIdVec);
+  return ProcIdVec;
+}
+
+static std::vector<PredTransition>
+makePerProcessorTransitions(const PredTransition &Trans,
+                            ArrayRef<unsigned> ProcIndices) {
+  std::vector<PredTransition> PerCpuTransVec;
+  for (unsigned ProcId : ProcIndices) {
+    assert(ProcId != 0);
+    PerCpuTransVec.push_back(Trans);
+    PerCpuTransVec.back().ProcIndex = ProcId;
+  }
+  return PerCpuTransVec;
+}
+
 // Create new SchedClasses for the given ReadWrite list. If any of the
 // ReadWrites refers to a SchedVariant, create a new SchedClass for each variant
 // of the ReadWrite list, following Aliases if necessary.
@@ -1767,21 +1767,21 @@ void CodeGenSchedModels::inferFromRW(ArrayRef<unsigned> OperWrites,
   }
   LLVM_DEBUG(dbgs() << '\n');
 
-  LastTransitions = makePerProcessorTransitions( 
-      LastTransitions[0], llvm::is_contained(ProcIndices, 0) 
-                              ? ArrayRef<unsigned>(getAllProcIndices()) 
-                              : ProcIndices); 
+  LastTransitions = makePerProcessorTransitions(
+      LastTransitions[0], llvm::is_contained(ProcIndices, 0)
+                              ? ArrayRef<unsigned>(getAllProcIndices())
+                              : ProcIndices);
   // Collect all PredTransitions for individual operands.
   // Iterate until no variant writes remain.
-  bool SubstitutedAny; 
-  do { 
-    SubstitutedAny = false; 
+  bool SubstitutedAny;
+  do {
+    SubstitutedAny = false;
     PredTransitions Transitions(*this);
     for (const PredTransition &Trans : LastTransitions)
-      SubstitutedAny |= Transitions.substituteVariants(Trans); 
+      SubstitutedAny |= Transitions.substituteVariants(Trans);
     LLVM_DEBUG(Transitions.dump());
     LastTransitions.swap(Transitions.TransVec);
-  } while (SubstitutedAny); 
+  } while (SubstitutedAny);
 
   // WARNING: We are about to mutate the SchedClasses vector. Do not refer to
   // OperWrites, OperReads, or ProcIndices after calling inferFromTransitions.
@@ -1824,7 +1824,7 @@ void CodeGenSchedModels::verifyProcResourceGroups(CodeGenProcModel &PM) {
                              OtherUnits.begin(), OtherUnits.end())
           != CheckUnits.end()) {
         // CheckUnits and OtherUnits overlap
-        llvm::append_range(OtherUnits, CheckUnits); 
+        llvm::append_range(OtherUnits, CheckUnits);
         if (!hasSuperGroup(OtherUnits, PM)) {
           PrintFatalError((PM.ProcResourceDefs[i])->getLoc(),
                           "proc resource group overlaps with "
@@ -2046,7 +2046,7 @@ void CodeGenSchedModels::collectItinProcResources(Record *ItinClassDef) {
     for (RecIter II = PM.ItinRWDefs.begin(), IE = PM.ItinRWDefs.end();
          II != IE; ++II) {
       RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");
-      if (!llvm::is_contained(Matched, ItinClassDef)) 
+      if (!llvm::is_contained(Matched, ItinClassDef))
         continue;
       if (HasMatch)
         PrintFatalError((*II)->getLoc(), "Duplicate itinerary class "
@@ -2247,14 +2247,14 @@ void CodeGenSchedClass::dump(const CodeGenSchedModels* SchedModels) const {
       dbgs().indent(10);
     }
   }
-  dbgs() << "\n  ProcIdx: "; dumpIdxVec(ProcIndices); 
+  dbgs() << "\n  ProcIdx: "; dumpIdxVec(ProcIndices);
   if (!Transitions.empty()) {
     dbgs() << "\n Transitions for Proc ";
     for (const CodeGenSchedTransition &Transition : Transitions) {
-      dbgs() << Transition.ProcIndex << ", "; 
+      dbgs() << Transition.ProcIndex << ", ";
     }
   }
-  dbgs() << '\n'; 
+  dbgs() << '\n';
 }
 
 void PredTransitions::dump() const {
diff --git a/contrib/libs/llvm12/utils/TableGen/CodeGenSchedule.h b/contrib/libs/llvm12/utils/TableGen/CodeGenSchedule.h
index 7702b6a31b..9020447c94 100644
--- a/contrib/libs/llvm12/utils/TableGen/CodeGenSchedule.h
+++ b/contrib/libs/llvm12/utils/TableGen/CodeGenSchedule.h
@@ -16,12 +16,12 @@
 
 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/STLExtras.h" 
+#include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/SetTheory.h"
-#include <map> 
+#include <map>
 
 namespace llvm {
 
@@ -96,7 +96,7 @@ struct CodeGenSchedRW {
 /// Represent a transition between SchedClasses induced by SchedVariant.
 struct CodeGenSchedTransition {
   unsigned ToClassIdx;
-  unsigned ProcIndex; 
+  unsigned ProcIndex;
   RecVec PredTerm;
 };
 
@@ -141,8 +141,8 @@ struct CodeGenSchedClass {
   // Instructions should be ignored by this class because they have been split
   // off to join another inferred class.
   RecVec InstRWs;
-  // InstRWs processor indices. Filled in inferFromInstRWs 
-  DenseSet<unsigned> InstRWProcIndices; 
+  // InstRWs processor indices. Filled in inferFromInstRWs
+  DenseSet<unsigned> InstRWProcIndices;
 
   CodeGenSchedClass(unsigned Index, std::string Name, Record *ItinClassDef)
     : Index(Index), Name(std::move(Name)), ItinClassDef(ItinClassDef) {}
@@ -362,7 +362,7 @@ public:
   OpcodeGroup(OpcodeGroup &&Other) = default;
 
   void addOpcode(const Record *Opcode) {
-    assert(!llvm::is_contained(Opcodes, Opcode) && "Opcode already in set!"); 
+    assert(!llvm::is_contained(Opcodes, Opcode) && "Opcode already in set!");
     Opcodes.push_back(Opcode);
   }
 
@@ -410,8 +410,8 @@ public:
   ArrayRef<OpcodeGroup> getGroups() const { return Groups; }
 };
 
-using ProcModelMapTy = DenseMap<const Record *, unsigned>; 
- 
+using ProcModelMapTy = DenseMap<const Record *, unsigned>;
+
 /// Top level container for machine model data.
 class CodeGenSchedModels {
   RecordKeeper &Records;
@@ -445,7 +445,7 @@ class CodeGenSchedModels {
   InstClassMapTy InstrClassMap;
 
   std::vector<STIPredicateFunction> STIPredicates;
-  std::vector<unsigned> getAllProcIndices() const; 
+  std::vector<unsigned> getAllProcIndices() const;
 
 public:
   CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
diff --git a/contrib/libs/llvm12/utils/TableGen/CodeGenTarget.cpp b/contrib/libs/llvm12/utils/TableGen/CodeGenTarget.cpp
index bf728ec269..8f6d212df5 100644
--- a/contrib/libs/llvm12/utils/TableGen/CodeGenTarget.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/CodeGenTarget.cpp
@@ -76,7 +76,7 @@ StringRef llvm::getEnumName(MVT::SimpleValueType T) {
   case MVT::f128:     return "MVT::f128";
   case MVT::ppcf128:  return "MVT::ppcf128";
   case MVT::x86mmx:   return "MVT::x86mmx";
-  case MVT::x86amx:   return "MVT::x86amx"; 
+  case MVT::x86amx:   return "MVT::x86amx";
   case MVT::Glue:     return "MVT::Glue";
   case MVT::isVoid:   return "MVT::isVoid";
   case MVT::v1i1:     return "MVT::v1i1";
@@ -87,7 +87,7 @@ StringRef llvm::getEnumName(MVT::SimpleValueType T) {
   case MVT::v32i1:    return "MVT::v32i1";
   case MVT::v64i1:    return "MVT::v64i1";
   case MVT::v128i1:   return "MVT::v128i1";
-  case MVT::v256i1:   return "MVT::v256i1"; 
+  case MVT::v256i1:   return "MVT::v256i1";
   case MVT::v512i1:   return "MVT::v512i1";
   case MVT::v1024i1:  return "MVT::v1024i1";
   case MVT::v1i8:     return "MVT::v1i8";
@@ -128,9 +128,9 @@ StringRef llvm::getEnumName(MVT::SimpleValueType T) {
   case MVT::v8i64:    return "MVT::v8i64";
   case MVT::v16i64:   return "MVT::v16i64";
   case MVT::v32i64:   return "MVT::v32i64";
-  case MVT::v64i64:   return "MVT::v64i64"; 
-  case MVT::v128i64:  return "MVT::v128i64"; 
-  case MVT::v256i64:  return "MVT::v256i64"; 
+  case MVT::v64i64:   return "MVT::v64i64";
+  case MVT::v128i64:  return "MVT::v128i64";
+  case MVT::v256i64:  return "MVT::v256i64";
   case MVT::v1i128:   return "MVT::v1i128";
   case MVT::v2f16:    return "MVT::v2f16";
   case MVT::v3f16:    return "MVT::v3f16";
@@ -168,9 +168,9 @@ StringRef llvm::getEnumName(MVT::SimpleValueType T) {
   case MVT::v8f64:    return "MVT::v8f64";
   case MVT::v16f64:   return "MVT::v16f64";
   case MVT::v32f64:   return "MVT::v32f64";
-  case MVT::v64f64:   return "MVT::v64f64"; 
-  case MVT::v128f64:  return "MVT::v128f64"; 
-  case MVT::v256f64:  return "MVT::v256f64"; 
+  case MVT::v64f64:   return "MVT::v64f64";
+  case MVT::v128f64:  return "MVT::v128f64";
+  case MVT::v256f64:  return "MVT::v256f64";
   case MVT::nxv1i1:   return "MVT::nxv1i1";
   case MVT::nxv2i1:   return "MVT::nxv2i1";
   case MVT::nxv4i1:   return "MVT::nxv4i1";
@@ -212,22 +212,22 @@ StringRef llvm::getEnumName(MVT::SimpleValueType T) {
   case MVT::nxv2bf16:  return "MVT::nxv2bf16";
   case MVT::nxv4bf16:  return "MVT::nxv4bf16";
   case MVT::nxv8bf16:  return "MVT::nxv8bf16";
-  case MVT::nxv1f32:   return "MVT::nxv1f32"; 
-  case MVT::nxv2f32:   return "MVT::nxv2f32"; 
-  case MVT::nxv4f32:   return "MVT::nxv4f32"; 
-  case MVT::nxv8f32:   return "MVT::nxv8f32"; 
-  case MVT::nxv16f32:  return "MVT::nxv16f32"; 
-  case MVT::nxv1f64:   return "MVT::nxv1f64"; 
-  case MVT::nxv2f64:   return "MVT::nxv2f64"; 
-  case MVT::nxv4f64:   return "MVT::nxv4f64"; 
-  case MVT::nxv8f64:   return "MVT::nxv8f64"; 
-  case MVT::token:     return "MVT::token"; 
-  case MVT::Metadata:  return "MVT::Metadata"; 
-  case MVT::iPTR:      return "MVT::iPTR"; 
-  case MVT::iPTRAny:   return "MVT::iPTRAny"; 
-  case MVT::Untyped:   return "MVT::Untyped"; 
-  case MVT::funcref:   return "MVT::funcref"; 
-  case MVT::externref: return "MVT::externref"; 
+  case MVT::nxv1f32:   return "MVT::nxv1f32";
+  case MVT::nxv2f32:   return "MVT::nxv2f32";
+  case MVT::nxv4f32:   return "MVT::nxv4f32";
+  case MVT::nxv8f32:   return "MVT::nxv8f32";
+  case MVT::nxv16f32:  return "MVT::nxv16f32";
+  case MVT::nxv1f64:   return "MVT::nxv1f64";
+  case MVT::nxv2f64:   return "MVT::nxv2f64";
+  case MVT::nxv4f64:   return "MVT::nxv4f64";
+  case MVT::nxv8f64:   return "MVT::nxv8f64";
+  case MVT::token:     return "MVT::token";
+  case MVT::Metadata:  return "MVT::Metadata";
+  case MVT::iPTR:      return "MVT::iPTR";
+  case MVT::iPTRAny:   return "MVT::iPTRAny";
+  case MVT::Untyped:   return "MVT::Untyped";
+  case MVT::funcref:   return "MVT::funcref";
+  case MVT::externref: return "MVT::externref";
   default: llvm_unreachable("ILLEGAL VALUE TYPE!");
   }
 }
@@ -260,29 +260,29 @@ CodeGenTarget::CodeGenTarget(RecordKeeper &records)
 CodeGenTarget::~CodeGenTarget() {
 }
 
-StringRef CodeGenTarget::getName() const { return TargetRec->getName(); } 
+StringRef CodeGenTarget::getName() const { return TargetRec->getName(); }
 
-/// getInstNamespace - Find and return the target machine's instruction 
-/// namespace. The namespace is cached because it is requested multiple times. 
+/// getInstNamespace - Find and return the target machine's instruction
+/// namespace. The namespace is cached because it is requested multiple times.
 StringRef CodeGenTarget::getInstNamespace() const {
-  if (InstNamespace.empty()) { 
-    for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) { 
-      // We are not interested in the "TargetOpcode" namespace. 
-      if (Inst->Namespace != "TargetOpcode") { 
-        InstNamespace = Inst->Namespace; 
-        break; 
-      } 
-    } 
+  if (InstNamespace.empty()) {
+    for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) {
+      // We are not interested in the "TargetOpcode" namespace.
+      if (Inst->Namespace != "TargetOpcode") {
+        InstNamespace = Inst->Namespace;
+        break;
+      }
+    }
   }
 
-  return InstNamespace; 
+  return InstNamespace;
+}
+
+StringRef CodeGenTarget::getRegNamespace() const {
+  auto &RegClasses = RegBank->getRegClasses();
+  return RegClasses.size() > 0 ? RegClasses.front().Namespace : "";
 }
 
-StringRef CodeGenTarget::getRegNamespace() const { 
-  auto &RegClasses = RegBank->getRegClasses(); 
-  return RegClasses.size() > 0 ? RegClasses.front().Namespace : ""; 
-} 
- 
 Record *CodeGenTarget::getInstructionSet() const {
   return TargetRec->getValueAsDef("InstructionSet");
 }
@@ -341,8 +341,8 @@ CodeGenRegBank &CodeGenTarget::getRegBank() const {
 Optional<CodeGenRegisterClass *>
 CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy,
                                     CodeGenRegBank &RegBank,
-                                    const CodeGenSubRegIndex *SubIdx, 
-                                    bool MustBeAllocatable) const { 
+                                    const CodeGenSubRegIndex *SubIdx,
+                                    bool MustBeAllocatable) const {
   std::vector<CodeGenRegisterClass *> Candidates;
   auto &RegClasses = RegBank.getRegClasses();
 
@@ -355,13 +355,13 @@ CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy,
       continue;
 
     // We have a class. Check if it supports this value type.
-    if (!llvm::is_contained(SubClassWithSubReg->VTs, ValueTy)) 
+    if (!llvm::is_contained(SubClassWithSubReg->VTs, ValueTy))
+      continue;
+
+    // If necessary, check that it is allocatable.
+    if (MustBeAllocatable && !SubClassWithSubReg->Allocatable)
       continue;
 
-    // If necessary, check that it is allocatable. 
-    if (MustBeAllocatable && !SubClassWithSubReg->Allocatable) 
-      continue; 
- 
     // We have a register class which supports both the value type and
     // subregister index. Remember it.
     Candidates.push_back(SubClassWithSubReg);
@@ -395,7 +395,7 @@ void CodeGenTarget::ReadRegAltNameIndices() const {
 /// getRegisterByName - If there is a register with the specific AsmName,
 /// return it.
 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
-  return getRegBank().getRegistersByName().lookup(Name); 
+  return getRegBank().getRegistersByName().lookup(Name);
 }
 
 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
@@ -405,7 +405,7 @@ std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
   for (const auto &RC : getRegBank().getRegClasses()) {
     if (RC.contains(Reg)) {
       ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes();
-      llvm::append_range(Result, InVTs); 
+      llvm::append_range(Result, InVTs);
     }
   }
 
@@ -418,7 +418,7 @@ std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
 
 void CodeGenTarget::ReadLegalValueTypes() const {
   for (const auto &RC : getRegBank().getRegClasses())
-    llvm::append_range(LegalValueTypes, RC.VTs); 
+    llvm::append_range(LegalValueTypes, RC.VTs);
 
   // Remove duplicates.
   llvm::sort(LegalValueTypes);
@@ -612,19 +612,19 @@ ComplexPattern::ComplexPattern(Record *R) {
 //===----------------------------------------------------------------------===//
 
 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) {
-  std::vector<Record *> IntrProperties = 
-      RC.getAllDerivedDefinitions("IntrinsicProperty"); 
-
-  std::vector<Record *> DefaultProperties; 
-  for (Record *Rec : IntrProperties) 
-    if (Rec->getValueAsBit("IsDefault")) 
-      DefaultProperties.push_back(Rec); 
- 
-  std::vector<Record *> Defs = RC.getAllDerivedDefinitions("Intrinsic"); 
+  std::vector<Record *> IntrProperties =
+      RC.getAllDerivedDefinitions("IntrinsicProperty");
+
+  std::vector<Record *> DefaultProperties;
+  for (Record *Rec : IntrProperties)
+    if (Rec->getValueAsBit("IsDefault"))
+      DefaultProperties.push_back(Rec);
+
+  std::vector<Record *> Defs = RC.getAllDerivedDefinitions("Intrinsic");
   Intrinsics.reserve(Defs.size());
 
   for (unsigned I = 0, e = Defs.size(); I != e; ++I)
-    Intrinsics.push_back(CodeGenIntrinsic(Defs[I], DefaultProperties)); 
+    Intrinsics.push_back(CodeGenIntrinsic(Defs[I], DefaultProperties));
 
   llvm::sort(Intrinsics,
              [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) {
@@ -640,8 +640,8 @@ CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) {
   Targets.back().Count = Intrinsics.size() - Targets.back().Offset;
 }
 
-CodeGenIntrinsic::CodeGenIntrinsic(Record *R, 
-                                   std::vector<Record *> DefaultProperties) { 
+CodeGenIntrinsic::CodeGenIntrinsic(Record *R,
+                                   std::vector<Record *> DefaultProperties) {
   TheDef = R;
   std::string DefName = std::string(R->getName());
   ArrayRef<SMLoc> DefLoc = R->getLoc();
@@ -794,12 +794,12 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R,
     assert(Property->isSubClassOf("IntrinsicProperty") &&
            "Expected a property!");
 
-    setProperty(Property); 
+    setProperty(Property);
   }
 
-  // Set default properties to true. 
-  setDefaultProperties(R, DefaultProperties); 
- 
+  // Set default properties to true.
+  setDefaultProperties(R, DefaultProperties);
+
   // Also record the SDPatternOperator Properties.
   Properties = parseSDPatternOperatorProperties(R);
 
@@ -807,92 +807,92 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R,
   llvm::sort(ArgumentAttributes);
 }
 
-void CodeGenIntrinsic::setDefaultProperties( 
-    Record *R, std::vector<Record *> DefaultProperties) { 
-  // opt-out of using default attributes. 
-  if (R->getValueAsBit("DisableDefaultAttributes")) 
-    return; 
- 
-  for (Record *Rec : DefaultProperties) 
-    setProperty(Rec); 
-} 
- 
-void CodeGenIntrinsic::setProperty(Record *R) { 
-  if (R->getName() == "IntrNoMem") 
-    ModRef = NoMem; 
-  else if (R->getName() == "IntrReadMem") { 
-    if (!(ModRef & MR_Ref)) 
-      PrintFatalError(TheDef->getLoc(), 
-                      Twine("IntrReadMem cannot be used after IntrNoMem or " 
-                            "IntrWriteMem. Default is ReadWrite")); 
-    ModRef = ModRefBehavior(ModRef & ~MR_Mod); 
-  } else if (R->getName() == "IntrWriteMem") { 
-    if (!(ModRef & MR_Mod)) 
-      PrintFatalError(TheDef->getLoc(), 
-                      Twine("IntrWriteMem cannot be used after IntrNoMem or " 
-                            "IntrReadMem. Default is ReadWrite")); 
-    ModRef = ModRefBehavior(ModRef & ~MR_Ref); 
-  } else if (R->getName() == "IntrArgMemOnly") 
-    ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem); 
-  else if (R->getName() == "IntrInaccessibleMemOnly") 
-    ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem); 
-  else if (R->getName() == "IntrInaccessibleMemOrArgMemOnly") 
-    ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem | 
-                            MR_InaccessibleMem); 
-  else if (R->getName() == "Commutative") 
-    isCommutative = true; 
-  else if (R->getName() == "Throws") 
-    canThrow = true; 
-  else if (R->getName() == "IntrNoDuplicate") 
-    isNoDuplicate = true; 
-  else if (R->getName() == "IntrConvergent") 
-    isConvergent = true; 
-  else if (R->getName() == "IntrNoReturn") 
-    isNoReturn = true; 
-  else if (R->getName() == "IntrNoSync") 
-    isNoSync = true; 
-  else if (R->getName() == "IntrNoFree") 
-    isNoFree = true; 
-  else if (R->getName() == "IntrWillReturn") 
-    isWillReturn = !isNoReturn; 
-  else if (R->getName() == "IntrCold") 
-    isCold = true; 
-  else if (R->getName() == "IntrSpeculatable") 
-    isSpeculatable = true; 
-  else if (R->getName() == "IntrHasSideEffects") 
-    hasSideEffects = true; 
-  else if (R->isSubClassOf("NoCapture")) { 
-    unsigned ArgNo = R->getValueAsInt("ArgNo"); 
-    ArgumentAttributes.emplace_back(ArgNo, NoCapture, 0); 
-  } else if (R->isSubClassOf("NoAlias")) { 
-    unsigned ArgNo = R->getValueAsInt("ArgNo"); 
-    ArgumentAttributes.emplace_back(ArgNo, NoAlias, 0); 
-  } else if (R->isSubClassOf("NoUndef")) { 
-    unsigned ArgNo = R->getValueAsInt("ArgNo"); 
-    ArgumentAttributes.emplace_back(ArgNo, NoUndef, 0); 
-  } else if (R->isSubClassOf("Returned")) { 
-    unsigned ArgNo = R->getValueAsInt("ArgNo"); 
-    ArgumentAttributes.emplace_back(ArgNo, Returned, 0); 
-  } else if (R->isSubClassOf("ReadOnly")) { 
-    unsigned ArgNo = R->getValueAsInt("ArgNo"); 
-    ArgumentAttributes.emplace_back(ArgNo, ReadOnly, 0); 
-  } else if (R->isSubClassOf("WriteOnly")) { 
-    unsigned ArgNo = R->getValueAsInt("ArgNo"); 
-    ArgumentAttributes.emplace_back(ArgNo, WriteOnly, 0); 
-  } else if (R->isSubClassOf("ReadNone")) { 
-    unsigned ArgNo = R->getValueAsInt("ArgNo"); 
-    ArgumentAttributes.emplace_back(ArgNo, ReadNone, 0); 
-  } else if (R->isSubClassOf("ImmArg")) { 
-    unsigned ArgNo = R->getValueAsInt("ArgNo"); 
-    ArgumentAttributes.emplace_back(ArgNo, ImmArg, 0); 
-  } else if (R->isSubClassOf("Align")) { 
-    unsigned ArgNo = R->getValueAsInt("ArgNo"); 
-    uint64_t Align = R->getValueAsInt("Align"); 
-    ArgumentAttributes.emplace_back(ArgNo, Alignment, Align); 
-  } else 
-    llvm_unreachable("Unknown property!"); 
-} 
- 
+void CodeGenIntrinsic::setDefaultProperties(
+    Record *R, std::vector<Record *> DefaultProperties) {
+  // opt-out of using default attributes.
+  if (R->getValueAsBit("DisableDefaultAttributes"))
+    return;
+
+  for (Record *Rec : DefaultProperties)
+    setProperty(Rec);
+}
+
+void CodeGenIntrinsic::setProperty(Record *R) {
+  if (R->getName() == "IntrNoMem")
+    ModRef = NoMem;
+  else if (R->getName() == "IntrReadMem") {
+    if (!(ModRef & MR_Ref))
+      PrintFatalError(TheDef->getLoc(),
+                      Twine("IntrReadMem cannot be used after IntrNoMem or "
+                            "IntrWriteMem. Default is ReadWrite"));
+    ModRef = ModRefBehavior(ModRef & ~MR_Mod);
+  } else if (R->getName() == "IntrWriteMem") {
+    if (!(ModRef & MR_Mod))
+      PrintFatalError(TheDef->getLoc(),
+                      Twine("IntrWriteMem cannot be used after IntrNoMem or "
+                            "IntrReadMem. Default is ReadWrite"));
+    ModRef = ModRefBehavior(ModRef & ~MR_Ref);
+  } else if (R->getName() == "IntrArgMemOnly")
+    ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem);
+  else if (R->getName() == "IntrInaccessibleMemOnly")
+    ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem);
+  else if (R->getName() == "IntrInaccessibleMemOrArgMemOnly")
+    ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem |
+                            MR_InaccessibleMem);
+  else if (R->getName() == "Commutative")
+    isCommutative = true;
+  else if (R->getName() == "Throws")
+    canThrow = true;
+  else if (R->getName() == "IntrNoDuplicate")
+    isNoDuplicate = true;
+  else if (R->getName() == "IntrConvergent")
+    isConvergent = true;
+  else if (R->getName() == "IntrNoReturn")
+    isNoReturn = true;
+  else if (R->getName() == "IntrNoSync")
+    isNoSync = true;
+  else if (R->getName() == "IntrNoFree")
+    isNoFree = true;
+  else if (R->getName() == "IntrWillReturn")
+    isWillReturn = !isNoReturn;
+  else if (R->getName() == "IntrCold")
+    isCold = true;
+  else if (R->getName() == "IntrSpeculatable")
+    isSpeculatable = true;
+  else if (R->getName() == "IntrHasSideEffects")
+    hasSideEffects = true;
+  else if (R->isSubClassOf("NoCapture")) {
+    unsigned ArgNo = R->getValueAsInt("ArgNo");
+    ArgumentAttributes.emplace_back(ArgNo, NoCapture, 0);
+  } else if (R->isSubClassOf("NoAlias")) {
+    unsigned ArgNo = R->getValueAsInt("ArgNo");
+    ArgumentAttributes.emplace_back(ArgNo, NoAlias, 0);
+  } else if (R->isSubClassOf("NoUndef")) {
+    unsigned ArgNo = R->getValueAsInt("ArgNo");
+    ArgumentAttributes.emplace_back(ArgNo, NoUndef, 0);
+  } else if (R->isSubClassOf("Returned")) {
+    unsigned ArgNo = R->getValueAsInt("ArgNo");
+    ArgumentAttributes.emplace_back(ArgNo, Returned, 0);
+  } else if (R->isSubClassOf("ReadOnly")) {
+    unsigned ArgNo = R->getValueAsInt("ArgNo");
+    ArgumentAttributes.emplace_back(ArgNo, ReadOnly, 0);
+  } else if (R->isSubClassOf("WriteOnly")) {
+    unsigned ArgNo = R->getValueAsInt("ArgNo");
+    ArgumentAttributes.emplace_back(ArgNo, WriteOnly, 0);
+  } else if (R->isSubClassOf("ReadNone")) {
+    unsigned ArgNo = R->getValueAsInt("ArgNo");
+    ArgumentAttributes.emplace_back(ArgNo, ReadNone, 0);
+  } else if (R->isSubClassOf("ImmArg")) {
+    unsigned ArgNo = R->getValueAsInt("ArgNo");
+    ArgumentAttributes.emplace_back(ArgNo, ImmArg, 0);
+  } else if (R->isSubClassOf("Align")) {
+    unsigned ArgNo = R->getValueAsInt("ArgNo");
+    uint64_t Align = R->getValueAsInt("Align");
+    ArgumentAttributes.emplace_back(ArgNo, Alignment, Align);
+  } else
+    llvm_unreachable("Unknown property!");
+}
+
 bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const {
   if (ParamIdx >= IS.ParamVTs.size())
     return false;
diff --git a/contrib/libs/llvm12/utils/TableGen/CodeGenTarget.h b/contrib/libs/llvm12/utils/TableGen/CodeGenTarget.h
index 10bdab7e21..9de9b512f7 100644
--- a/contrib/libs/llvm12/utils/TableGen/CodeGenTarget.h
+++ b/contrib/libs/llvm12/utils/TableGen/CodeGenTarget.h
@@ -60,7 +60,7 @@ class CodeGenTarget {
 
   mutable std::unique_ptr<CodeGenSchedModels> SchedModels;
 
-  mutable StringRef InstNamespace; 
+  mutable StringRef InstNamespace;
   mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
   mutable unsigned NumPseudoInstructions = 0;
 public:
@@ -68,15 +68,15 @@ public:
   ~CodeGenTarget();
 
   Record *getTargetRecord() const { return TargetRec; }
-  StringRef getName() const; 
+  StringRef getName() const;
 
   /// getInstNamespace - Return the target-specific instruction namespace.
   ///
   StringRef getInstNamespace() const;
 
-  /// getRegNamespace - Return the target-specific register namespace. 
-  StringRef getRegNamespace() const; 
- 
+  /// getRegNamespace - Return the target-specific register namespace.
+  StringRef getRegNamespace() const;
+
   /// getInstructionSet - Return the InstructionSet object.
   ///
   Record *getInstructionSet() const;
@@ -111,8 +111,8 @@ public:
   /// covers \p SubIdx if it exists.
   Optional<CodeGenRegisterClass *>
   getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank,
-                       const CodeGenSubRegIndex *SubIdx, 
-                       bool MustBeAllocatable = false) const; 
+                       const CodeGenSubRegIndex *SubIdx,
+                       bool MustBeAllocatable = false) const;
 
   /// getRegisterByName - If there is a register with the specific AsmName,
   /// return it.
diff --git a/contrib/libs/llvm12/utils/TableGen/DAGISelEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/DAGISelEmitter.cpp
index 7e9a624877..32ed0bf987 100644
--- a/contrib/libs/llvm12/utils/TableGen/DAGISelEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/DAGISelEmitter.cpp
@@ -23,10 +23,10 @@ namespace {
 /// DAGISelEmitter - The top-level class which coordinates construction
 /// and emission of the instruction selector.
 class DAGISelEmitter {
-  RecordKeeper &Records; // Just so we can get at the timing functions. 
+  RecordKeeper &Records; // Just so we can get at the timing functions.
   CodeGenDAGPatterns CGP;
 public:
-  explicit DAGISelEmitter(RecordKeeper &R) : Records(R), CGP(R) {} 
+  explicit DAGISelEmitter(RecordKeeper &R) : Records(R), CGP(R) {}
   void run(raw_ostream &OS);
 };
 } // End anonymous namespace
@@ -151,7 +151,7 @@ void DAGISelEmitter::run(raw_ostream &OS) {
              });
 
   // Add all the patterns to a temporary list so we can sort them.
-  Records.startTimer("Sort patterns"); 
+  Records.startTimer("Sort patterns");
   std::vector<const PatternToMatch*> Patterns;
   for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(), E = CGP.ptm_end();
        I != E; ++I)
@@ -159,10 +159,10 @@ void DAGISelEmitter::run(raw_ostream &OS) {
 
   // We want to process the matches in order of minimal cost.  Sort the patterns
   // so the least cost one is at the start.
-  llvm::stable_sort(Patterns, PatternSortingPredicate(CGP)); 
+  llvm::stable_sort(Patterns, PatternSortingPredicate(CGP));
 
   // Convert each variant of each pattern into a Matcher.
-  Records.startTimer("Convert to matchers"); 
+  Records.startTimer("Convert to matchers");
   std::vector<Matcher*> PatternMatchers;
   for (unsigned i = 0, e = Patterns.size(); i != e; ++i) {
     for (unsigned Variant = 0; ; ++Variant) {
@@ -176,19 +176,19 @@ void DAGISelEmitter::run(raw_ostream &OS) {
   std::unique_ptr<Matcher> TheMatcher =
     std::make_unique<ScopeMatcher>(PatternMatchers);
 
-  Records.startTimer("Optimize matchers"); 
+  Records.startTimer("Optimize matchers");
   OptimizeMatcher(TheMatcher, CGP);
- 
+
   //Matcher->dump();
- 
-  Records.startTimer("Emit matcher table"); 
+
+  Records.startTimer("Emit matcher table");
   EmitMatcherTable(TheMatcher.get(), CGP, OS);
 }
 
 namespace llvm {
 
 void EmitDAGISel(RecordKeeper &RK, raw_ostream &OS) {
-  RK.startTimer("Parse patterns"); 
+  RK.startTimer("Parse patterns");
   DAGISelEmitter(RK).run(OS);
 }
 
diff --git a/contrib/libs/llvm12/utils/TableGen/DAGISelMatcher.h b/contrib/libs/llvm12/utils/TableGen/DAGISelMatcher.h
index 370ad82c54..ff9a0cb335 100644
--- a/contrib/libs/llvm12/utils/TableGen/DAGISelMatcher.h
+++ b/contrib/libs/llvm12/utils/TableGen/DAGISelMatcher.h
@@ -31,7 +31,7 @@ Matcher *ConvertPatternToMatcher(const PatternToMatch &Pattern,unsigned Variant,
                                  const CodeGenDAGPatterns &CGP);
 void OptimizeMatcher(std::unique_ptr<Matcher> &Matcher,
                      const CodeGenDAGPatterns &CGP);
-void EmitMatcherTable(Matcher *Matcher, const CodeGenDAGPatterns &CGP, 
+void EmitMatcherTable(Matcher *Matcher, const CodeGenDAGPatterns &CGP,
                       raw_ostream &OS);
 
 
@@ -41,7 +41,7 @@ class Matcher {
   // The next matcher node that is executed after this one.  Null if this is the
   // last stage of a match.
   std::unique_ptr<Matcher> Next;
-  size_t Size; // Size in bytes of matcher and all its children (if any). 
+  size_t Size; // Size in bytes of matcher and all its children (if any).
   virtual void anchor();
 public:
   enum KindTy {
@@ -86,10 +86,10 @@ public:
     EmitNode,             // Create a DAG node
     EmitNodeXForm,        // Run a SDNodeXForm
     CompleteMatch,        // Finish a match and update the results.
-    MorphNodeTo,          // Build a node, finish a match and update results. 
- 
-    // Highest enum value; watch out when adding more. 
-    HighestKind = MorphNodeTo 
+    MorphNodeTo,          // Build a node, finish a match and update results.
+
+    // Highest enum value; watch out when adding more.
+    HighestKind = MorphNodeTo
   };
   const KindTy Kind;
 
@@ -98,8 +98,8 @@ protected:
 public:
   virtual ~Matcher() {}
 
-  unsigned getSize() const { return Size; } 
-  void setSize(unsigned sz) { Size = sz; } 
+  unsigned getSize() const { return Size; }
+  void setSize(unsigned sz) { Size = sz; }
   KindTy getKind() const { return Kind; }
 
   Matcher *getNext() { return Next.get(); }
@@ -706,7 +706,7 @@ public:
   const ComplexPattern &getPattern() const { return Pattern; }
   unsigned getMatchNumber() const { return MatchNumber; }
 
-  std::string getName() const { return Name; } 
+  std::string getName() const { return Name; }
   unsigned getFirstResult() const { return FirstResult; }
 
   static bool classof(const Matcher *N) {
@@ -763,8 +763,8 @@ private:
   }
 };
 
-/// CheckImmAllOnesVMatcher - This checks if the current node is a build_vector 
-/// or splat_vector of all ones. 
+/// CheckImmAllOnesVMatcher - This checks if the current node is a build_vector
+/// or splat_vector of all ones.
 class CheckImmAllOnesVMatcher : public Matcher {
 public:
   CheckImmAllOnesVMatcher() : Matcher(CheckImmAllOnesV) {}
@@ -779,8 +779,8 @@ private:
   bool isContradictoryImpl(const Matcher *M) const override;
 };
 
-/// CheckImmAllZerosVMatcher - This checks if the current node is a 
-/// build_vector or splat_vector of all zeros. 
+/// CheckImmAllZerosVMatcher - This checks if the current node is a
+/// build_vector or splat_vector of all zeros.
 class CheckImmAllZerosVMatcher : public Matcher {
 public:
   CheckImmAllZerosVMatcher() : Matcher(CheckImmAllZerosV) {}
diff --git a/contrib/libs/llvm12/utils/TableGen/DAGISelMatcherEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/DAGISelMatcherEmitter.cpp
index 21ae8b3551..03528a46ae 100644
--- a/contrib/libs/llvm12/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -23,7 +23,7 @@
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
- 
+
 using namespace llvm;
 
 enum {
@@ -48,8 +48,8 @@ namespace {
 class MatcherTableEmitter {
   const CodeGenDAGPatterns &CGP;
 
-  SmallVector<unsigned, Matcher::HighestKind+1> OpcodeCounts; 
- 
+  SmallVector<unsigned, Matcher::HighestKind+1> OpcodeCounts;
+
   DenseMap<TreePattern *, unsigned> NodePredicateMap;
   std::vector<TreePredicateFn> NodePredicates;
   std::vector<TreePredicateFn> NodePredicatesWithOperands;
@@ -82,15 +82,15 @@ class MatcherTableEmitter {
   }
 
 public:
-  MatcherTableEmitter(const CodeGenDAGPatterns &cgp) : CGP(cgp) { 
-    OpcodeCounts.assign(Matcher::HighestKind+1, 0); 
-  } 
+  MatcherTableEmitter(const CodeGenDAGPatterns &cgp) : CGP(cgp) {
+    OpcodeCounts.assign(Matcher::HighestKind+1, 0);
+  }
 
-  unsigned EmitMatcherList(const Matcher *N, const unsigned Indent, 
+  unsigned EmitMatcherList(const Matcher *N, const unsigned Indent,
                            unsigned StartIdx, raw_ostream &OS);
 
-  unsigned SizeMatcherList(Matcher *N, raw_ostream &OS); 
- 
+  unsigned SizeMatcherList(Matcher *N, raw_ostream &OS);
+
   void EmitPredicateFunctions(raw_ostream &OS);
 
   void EmitHistogram(const Matcher *N, raw_ostream &OS);
@@ -101,9 +101,9 @@ private:
   void EmitNodePredicatesFunction(const std::vector<TreePredicateFn> &Preds,
                                   StringRef Decl, raw_ostream &OS);
 
-  unsigned SizeMatcher(Matcher *N, raw_ostream &OS); 
- 
-  unsigned EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx, 
+  unsigned SizeMatcher(Matcher *N, raw_ostream &OS);
+
+  unsigned EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
                        raw_ostream &OS);
 
   unsigned getNodePredicate(TreePredicateFn Pred) {
@@ -173,7 +173,7 @@ static std::string GetPatFromTreePatternNode(const TreePatternNode *N) {
   return str;
 }
 
-static size_t GetVBRSize(unsigned Val) { 
+static size_t GetVBRSize(unsigned Val) {
   if (Val <= 127) return 1;
 
   unsigned NumBytes = 0;
@@ -227,78 +227,78 @@ static std::string getIncludePath(const Record *R) {
   return str;
 }
 
-/// This function traverses the matcher tree and sizes all the nodes 
-/// that are children of the three kinds of nodes that have them. 
-unsigned MatcherTableEmitter:: 
-SizeMatcherList(Matcher *N, raw_ostream &OS) { 
-  unsigned Size = 0; 
-  while (N) { 
-    Size += SizeMatcher(N, OS); 
-    N = N->getNext(); 
-  } 
-  return Size; 
-} 
- 
-/// This function sizes the children of the three kinds of nodes that 
-/// have them. It does so by using special cases for those three 
-/// nodes, but sharing the code in EmitMatcher() for the other kinds. 
-unsigned MatcherTableEmitter:: 
-SizeMatcher(Matcher *N, raw_ostream &OS) { 
-  unsigned Idx = 0; 
- 
-  ++OpcodeCounts[N->getKind()]; 
-  switch (N->getKind()) { 
-  // The Scope matcher has its kind, a series of child size + child, 
-  // and a trailing zero. 
-  case Matcher::Scope: { 
-    ScopeMatcher *SM = cast<ScopeMatcher>(N); 
-    assert(SM->getNext() == nullptr && "Scope matcher should not have next"); 
-    unsigned Size = 1; // Count the kind. 
-    for (unsigned i = 0, e = SM->getNumChildren(); i != e; ++i) { 
-      const size_t ChildSize = SizeMatcherList(SM->getChild(i), OS); 
-      assert(ChildSize != 0 && "Matcher cannot have child of size 0"); 
-      SM->getChild(i)->setSize(ChildSize); 
-      Size += GetVBRSize(ChildSize) + ChildSize; // Count VBR and child size. 
-    } 
-    ++Size; // Count the zero sentinel. 
-    return Size; 
-  } 
- 
-  // SwitchOpcode and SwitchType have their kind, a series of child size + 
-  // opcode/type + child, and a trailing zero. 
-  case Matcher::SwitchOpcode: 
-  case Matcher::SwitchType: { 
-    unsigned Size = 1; // Count the kind. 
-    unsigned NumCases; 
-    if (const SwitchOpcodeMatcher *SOM = dyn_cast<SwitchOpcodeMatcher>(N)) 
-      NumCases = SOM->getNumCases(); 
-    else 
-      NumCases = cast<SwitchTypeMatcher>(N)->getNumCases(); 
-    for (unsigned i = 0, e = NumCases; i != e; ++i) { 
-      Matcher *Child; 
-      if (SwitchOpcodeMatcher *SOM = dyn_cast<SwitchOpcodeMatcher>(N)) { 
-        Child = SOM->getCaseMatcher(i); 
-        Size += 2; // Count the child's opcode. 
-      } else { 
-        Child = cast<SwitchTypeMatcher>(N)->getCaseMatcher(i); 
-        ++Size; // Count the child's type. 
-      } 
-      const size_t ChildSize = SizeMatcherList(Child, OS); 
-      assert(ChildSize != 0 && "Matcher cannot have child of size 0"); 
-      Child->setSize(ChildSize); 
-      Size += GetVBRSize(ChildSize) + ChildSize; // Count VBR and child size. 
-    } 
-    ++Size; // Count the zero sentinel. 
-    return Size; 
-  } 
- 
-  default: 
-    // Employ the matcher emitter to size other matchers. 
-    return EmitMatcher(N, 0, Idx, OS); 
-  } 
-  llvm_unreachable("Unreachable"); 
-} 
- 
+/// This function traverses the matcher tree and sizes all the nodes
+/// that are children of the three kinds of nodes that have them.
+unsigned MatcherTableEmitter::
+SizeMatcherList(Matcher *N, raw_ostream &OS) {
+  unsigned Size = 0;
+  while (N) {
+    Size += SizeMatcher(N, OS);
+    N = N->getNext();
+  }
+  return Size;
+}
+
+/// This function sizes the children of the three kinds of nodes that
+/// have them. It does so by using special cases for those three
+/// nodes, but sharing the code in EmitMatcher() for the other kinds.
+unsigned MatcherTableEmitter::
+SizeMatcher(Matcher *N, raw_ostream &OS) {
+  unsigned Idx = 0;
+
+  ++OpcodeCounts[N->getKind()];
+  switch (N->getKind()) {
+  // The Scope matcher has its kind, a series of child size + child,
+  // and a trailing zero.
+  case Matcher::Scope: {
+    ScopeMatcher *SM = cast<ScopeMatcher>(N);
+    assert(SM->getNext() == nullptr && "Scope matcher should not have next");
+    unsigned Size = 1; // Count the kind.
+    for (unsigned i = 0, e = SM->getNumChildren(); i != e; ++i) {
+      const size_t ChildSize = SizeMatcherList(SM->getChild(i), OS);
+      assert(ChildSize != 0 && "Matcher cannot have child of size 0");
+      SM->getChild(i)->setSize(ChildSize);
+      Size += GetVBRSize(ChildSize) + ChildSize; // Count VBR and child size.
+    }
+    ++Size; // Count the zero sentinel.
+    return Size;
+  }
+
+  // SwitchOpcode and SwitchType have their kind, a series of child size +
+  // opcode/type + child, and a trailing zero.
+  case Matcher::SwitchOpcode:
+  case Matcher::SwitchType: {
+    unsigned Size = 1; // Count the kind.
+    unsigned NumCases;
+    if (const SwitchOpcodeMatcher *SOM = dyn_cast<SwitchOpcodeMatcher>(N))
+      NumCases = SOM->getNumCases();
+    else
+      NumCases = cast<SwitchTypeMatcher>(N)->getNumCases();
+    for (unsigned i = 0, e = NumCases; i != e; ++i) {
+      Matcher *Child;
+      if (SwitchOpcodeMatcher *SOM = dyn_cast<SwitchOpcodeMatcher>(N)) {
+        Child = SOM->getCaseMatcher(i);
+        Size += 2; // Count the child's opcode.
+      } else {
+        Child = cast<SwitchTypeMatcher>(N)->getCaseMatcher(i);
+        ++Size; // Count the child's type.
+      }
+      const size_t ChildSize = SizeMatcherList(Child, OS);
+      assert(ChildSize != 0 && "Matcher cannot have child of size 0");
+      Child->setSize(ChildSize);
+      Size += GetVBRSize(ChildSize) + ChildSize; // Count VBR and child size.
+    }
+    ++Size; // Count the zero sentinel.
+    return Size;
+  }
+
+  default:
+    // Employ the matcher emitter to size other matchers.
+    return EmitMatcher(N, 0, Idx, OS);
+  }
+  llvm_unreachable("Unreachable");
+}
+
 static void BeginEmitFunction(raw_ostream &OS, StringRef RetType,
                               StringRef Decl, bool AddOverride) {
   OS << "#ifdef GET_DAGISEL_DECL\n";
@@ -330,7 +330,7 @@ void MatcherTableEmitter::EmitPatternMatchTable(raw_ostream &OS) {
   BeginEmitFunction(OS, "StringRef", "getPatternForIndex(unsigned Index)",
                     true/*AddOverride*/);
   OS << "{\n";
-  OS << "static const char *PATTERN_MATCH_TABLE[] = {\n"; 
+  OS << "static const char *PATTERN_MATCH_TABLE[] = {\n";
 
   for (const auto &It : VecPatterns) {
     OS << "\"" << It.first << "\",\n";
@@ -344,7 +344,7 @@ void MatcherTableEmitter::EmitPatternMatchTable(raw_ostream &OS) {
   BeginEmitFunction(OS, "StringRef", "getIncludePathForIndex(unsigned Index)",
                     true/*AddOverride*/);
   OS << "{\n";
-  OS << "static const char *INCLUDE_PATH_TABLE[] = {\n"; 
+  OS << "static const char *INCLUDE_PATH_TABLE[] = {\n";
 
   for (const auto &It : VecIncludeStrings) {
     OS << "\"" << It << "\",\n";
@@ -359,7 +359,7 @@ void MatcherTableEmitter::EmitPatternMatchTable(raw_ostream &OS) {
 /// EmitMatcher - Emit bytes for the specified matcher and return
 /// the number of bytes emitted.
 unsigned MatcherTableEmitter::
-EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx, 
+EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
             raw_ostream &OS) {
   OS.indent(Indent);
 
@@ -381,21 +381,21 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
           OS.indent(Indent);
       }
 
-      size_t ChildSize = SM->getChild(i)->getSize(); 
-      size_t VBRSize = GetVBRSize(ChildSize); 
-      EmitVBRValue(ChildSize, OS); 
+      size_t ChildSize = SM->getChild(i)->getSize();
+      size_t VBRSize = GetVBRSize(ChildSize);
+      EmitVBRValue(ChildSize, OS);
       if (!OmitComments) {
-        OS << "/*->" << CurrentIdx + VBRSize + ChildSize << "*/"; 
+        OS << "/*->" << CurrentIdx + VBRSize + ChildSize << "*/";
         if (i == 0)
           OS << " // " << SM->getNumChildren() << " children in Scope";
       }
-      OS << '\n'; 
+      OS << '\n';
 
-      ChildSize = EmitMatcherList(SM->getChild(i), Indent+1, 
-                                  CurrentIdx + VBRSize, OS); 
-      assert(ChildSize == SM->getChild(i)->getSize() && 
-             "Emitted child size does not match calculated size"); 
-      CurrentIdx += VBRSize + ChildSize; 
+      ChildSize = EmitMatcherList(SM->getChild(i), Indent+1,
+                                  CurrentIdx + VBRSize, OS);
+      assert(ChildSize == SM->getChild(i)->getSize() &&
+             "Emitted child size does not match calculated size");
+      CurrentIdx += VBRSize + ChildSize;
     }
 
     // Emit a zero as a sentinel indicating end of 'Scope'.
@@ -534,19 +534,19 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
                      "/*SwitchOpcode*/ " : "/*SwitchType*/ ");
       }
 
-      size_t ChildSize = Child->getSize(); 
-      CurrentIdx += EmitVBRValue(ChildSize, OS) + IdxSize; 
+      size_t ChildSize = Child->getSize();
+      CurrentIdx += EmitVBRValue(ChildSize, OS) + IdxSize;
       if (const SwitchOpcodeMatcher *SOM = dyn_cast<SwitchOpcodeMatcher>(N))
         OS << "TARGET_VAL(" << SOM->getCaseOpcode(i).getEnumName() << "),";
       else
         OS << getEnumName(cast<SwitchTypeMatcher>(N)->getCaseType(i)) << ',';
       if (!OmitComments)
-        OS << "// ->" << CurrentIdx + ChildSize; 
+        OS << "// ->" << CurrentIdx + ChildSize;
       OS << '\n';
- 
-      ChildSize = EmitMatcherList(Child, Indent+1, CurrentIdx, OS); 
-      assert(ChildSize == Child->getSize() && 
-             "Emitted child size does not match calculated size"); 
+
+      ChildSize = EmitMatcherList(Child, Indent+1, CurrentIdx, OS);
+      assert(ChildSize == Child->getSize() &&
+             "Emitted child size does not match calculated size");
       CurrentIdx += ChildSize;
     }
 
@@ -559,7 +559,7 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
              " // EndSwitchOpcode" : " // EndSwitchType");
 
     OS << '\n';
-    return CurrentIdx - StartIdx + 1; 
+    return CurrentIdx - StartIdx + 1;
   }
 
  case Matcher::CheckType:
@@ -853,10 +853,10 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
   llvm_unreachable("Unreachable");
 }
 
-/// This function traverses the matcher tree and emits all the nodes. 
-/// The nodes have already been sized. 
+/// This function traverses the matcher tree and emits all the nodes.
+/// The nodes have already been sized.
 unsigned MatcherTableEmitter::
-EmitMatcherList(const Matcher *N, const unsigned Indent, unsigned CurrentIdx, 
+EmitMatcherList(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
                 raw_ostream &OS) {
   unsigned Size = 0;
   while (N) {
@@ -885,12 +885,12 @@ void MatcherTableEmitter::EmitNodePredicatesFunction(
   OS << "  default: llvm_unreachable(\"Invalid predicate in table?\");\n";
   for (unsigned i = 0, e = Preds.size(); i != e; ++i) {
     // Emit the predicate code corresponding to this pattern.
-    const TreePredicateFn PredFn = Preds[i]; 
+    const TreePredicateFn PredFn = Preds[i];
 
     assert(!PredFn.isAlwaysTrue() && "No code in this predicate");
-    OS << "  case " << i << ": {\n"; 
+    OS << "  case " << i << ": {\n";
     for (auto *SimilarPred :
-             NodePredicatesByCodeToRun[PredFn.getCodeToRunOnSDNode()]) 
+             NodePredicatesByCodeToRun[PredFn.getCodeToRunOnSDNode()])
       OS << "    // " << TreePredicateFn(SimilarPred).getFnName() <<'\n';
 
     OS << PredFn.getCodeToRunOnSDNode() << "\n  }\n";
@@ -931,7 +931,7 @@ void MatcherTableEmitter::EmitPredicateFunctions(raw_ostream &OS) {
     BeginEmitFunction(OS, "bool",
           "CheckComplexPattern(SDNode *Root, SDNode *Parent,\n"
           "      SDValue N, unsigned PatternNo,\n"
-          "      SmallVectorImpl<std::pair<SDValue, SDNode *>> &Result)", 
+          "      SmallVectorImpl<std::pair<SDValue, SDNode *>> &Result)",
           true/*AddOverride*/);
     OS << "{\n";
     OS << "  unsigned NextRes = Result.size();\n";
@@ -1071,16 +1071,16 @@ void MatcherTableEmitter::EmitHistogram(const Matcher *M,
     return;
 
   OS << "  // Opcode Histogram:\n";
-  for (unsigned i = 0, e = OpcodeCounts.size(); i != e; ++i) { 
+  for (unsigned i = 0, e = OpcodeCounts.size(); i != e; ++i) {
     OS << "  // #"
        << left_justify(getOpcodeString((Matcher::KindTy)i), HistOpcWidth)
-       << " = " << OpcodeCounts[i] << '\n'; 
+       << " = " << OpcodeCounts[i] << '\n';
   }
   OS << '\n';
 }
 
 
-void llvm::EmitMatcherTable(Matcher *TheMatcher, 
+void llvm::EmitMatcherTable(Matcher *TheMatcher,
                             const CodeGenDAGPatterns &CGP,
                             raw_ostream &OS) {
   OS << "#if defined(GET_DAGISEL_DECL) && defined(GET_DAGISEL_BODY)\n";
@@ -1115,23 +1115,23 @@ void llvm::EmitMatcherTable(Matcher *TheMatcher,
   BeginEmitFunction(OS, "void", "SelectCode(SDNode *N)", false/*AddOverride*/);
   MatcherTableEmitter MatcherEmitter(CGP);
 
-  // First we size all the children of the three kinds of matchers that have 
-  // them. This is done by sharing the code in EmitMatcher(). but we don't 
-  // want to emit anything, so we turn off comments and use a null stream. 
-  bool SaveOmitComments = OmitComments; 
-  OmitComments = true; 
-  raw_null_ostream NullOS; 
-  unsigned TotalSize = MatcherEmitter.SizeMatcherList(TheMatcher, NullOS); 
-  OmitComments = SaveOmitComments; 
- 
-  // Now that the matchers are sized, we can emit the code for them to the 
-  // final stream. 
+  // First we size all the children of the three kinds of matchers that have
+  // them. This is done by sharing the code in EmitMatcher(). but we don't
+  // want to emit anything, so we turn off comments and use a null stream.
+  bool SaveOmitComments = OmitComments;
+  OmitComments = true;
+  raw_null_ostream NullOS;
+  unsigned TotalSize = MatcherEmitter.SizeMatcherList(TheMatcher, NullOS);
+  OmitComments = SaveOmitComments;
+
+  // Now that the matchers are sized, we can emit the code for them to the
+  // final stream.
   OS << "{\n";
   OS << "  // Some target values are emitted as 2 bytes, TARGET_VAL handles\n";
   OS << "  // this.\n";
   OS << "  #define TARGET_VAL(X) X & 255, unsigned(X) >> 8\n";
   OS << "  static const unsigned char MatcherTable[] = {\n";
-  TotalSize = MatcherEmitter.EmitMatcherList(TheMatcher, 1, 0, OS); 
+  TotalSize = MatcherEmitter.EmitMatcherList(TheMatcher, 1, 0, OS);
   OS << "    0\n  }; // Total Array size is " << (TotalSize+1) << " bytes\n\n";
 
   MatcherEmitter.EmitHistogram(TheMatcher, OS);
diff --git a/contrib/libs/llvm12/utils/TableGen/DAGISelMatcherGen.cpp b/contrib/libs/llvm12/utils/TableGen/DAGISelMatcherGen.cpp
index 1e6a497df7..f7415b87e1 100644
--- a/contrib/libs/llvm12/utils/TableGen/DAGISelMatcherGen.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/DAGISelMatcherGen.cpp
@@ -282,9 +282,9 @@ void MatcherGen::EmitLeafMatchCode(const TreePatternNode *N) {
     // check to ensure that this gets folded into the normal top-level
     // OpcodeSwitch.
     if (N == Pattern.getSrcPattern()) {
-      MVT VT = N->getSimpleType(0); 
-      StringRef Name = VT.isScalableVector() ? "splat_vector" : "build_vector"; 
-      const SDNodeInfo &NI = CGP.getSDNodeInfo(CGP.getSDNodeNamed(Name)); 
+      MVT VT = N->getSimpleType(0);
+      StringRef Name = VT.isScalableVector() ? "splat_vector" : "build_vector";
+      const SDNodeInfo &NI = CGP.getSDNodeInfo(CGP.getSDNodeNamed(Name));
       AddMatcher(new CheckOpcodeMatcher(NI));
     }
     return AddMatcher(new CheckImmAllOnesVMatcher());
@@ -294,9 +294,9 @@ void MatcherGen::EmitLeafMatchCode(const TreePatternNode *N) {
     // check to ensure that this gets folded into the normal top-level
     // OpcodeSwitch.
     if (N == Pattern.getSrcPattern()) {
-      MVT VT = N->getSimpleType(0); 
-      StringRef Name = VT.isScalableVector() ? "splat_vector" : "build_vector"; 
-      const SDNodeInfo &NI = CGP.getSDNodeInfo(CGP.getSDNodeNamed(Name)); 
+      MVT VT = N->getSimpleType(0);
+      StringRef Name = VT.isScalableVector() ? "splat_vector" : "build_vector";
+      const SDNodeInfo &NI = CGP.getSDNodeInfo(CGP.getSDNodeNamed(Name));
       AddMatcher(new CheckOpcodeMatcher(NI));
     }
     return AddMatcher(new CheckImmAllZerosVMatcher());
@@ -748,7 +748,7 @@ void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode *N,
     }
   }
 
-  errs() << "unhandled leaf node:\n"; 
+  errs() << "unhandled leaf node:\n";
   N->dump();
 }
 
diff --git a/contrib/libs/llvm12/utils/TableGen/DFAEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/DFAEmitter.cpp
index 71abb47ca2..781cb0636f 100644
--- a/contrib/libs/llvm12/utils/TableGen/DFAEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/DFAEmitter.cpp
@@ -346,7 +346,7 @@ Transition::Transition(Record *R, Automaton *Parent) {
     } else if (isa<IntRecTy>(SymbolV->getType())) {
       Actions.emplace_back(nullptr, R->getValueAsInt(A), "");
       Types.emplace_back("unsigned");
-    } else if (isa<StringRecTy>(SymbolV->getType())) { 
+    } else if (isa<StringRecTy>(SymbolV->getType())) {
       Actions.emplace_back(nullptr, 0, std::string(R->getValueAsString(A)));
       Types.emplace_back("std::string");
     } else {
diff --git a/contrib/libs/llvm12/utils/TableGen/DFAPacketizerEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/DFAPacketizerEmitter.cpp
index d4ae9208f5..40d9385e5e 100644
--- a/contrib/libs/llvm12/utils/TableGen/DFAPacketizerEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/DFAPacketizerEmitter.cpp
@@ -263,7 +263,7 @@ void DFAPacketizerEmitter::emitForItineraries(
     OS << "  " << ProcModelStartIdx[Model] << ", // " << Model->ModelName
        << "\n";
   }
-  OS << "  " << ScheduleClasses.size() << "\n};\n\n"; 
+  OS << "  " << ScheduleClasses.size() << "\n};\n\n";
 
   // The type of a state in the nondeterministic automaton we're defining.
   using NfaStateTy = uint64_t;
diff --git a/contrib/libs/llvm12/utils/TableGen/DirectiveEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/DirectiveEmitter.cpp
index 6da6be1129..c9daa9b241 100644
--- a/contrib/libs/llvm12/utils/TableGen/DirectiveEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/DirectiveEmitter.cpp
@@ -11,7 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/TableGen/DirectiveEmitter.h" 
+#include "llvm/TableGen/DirectiveEmitter.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringSet.h"
@@ -42,13 +42,13 @@ namespace llvm {
 
 // Generate enum class
 void GenerateEnumClass(const std::vector<Record *> &Records, raw_ostream &OS,
-                       StringRef Enum, StringRef Prefix, 
-                       const DirectiveLanguage &DirLang) { 
+                       StringRef Enum, StringRef Prefix,
+                       const DirectiveLanguage &DirLang) {
   OS << "\n";
   OS << "enum class " << Enum << " {\n";
   for (const auto &R : Records) {
-    BaseRecord Rec{R}; 
-    OS << "  " << Prefix << Rec.getFormattedName() << ",\n"; 
+    BaseRecord Rec{R};
+    OS << "  " << Prefix << Rec.getFormattedName() << ",\n";
   }
   OS << "};\n";
   OS << "\n";
@@ -60,130 +60,130 @@ void GenerateEnumClass(const std::vector<Record *> &Records, raw_ostream &OS,
   // At the same time we do not loose the strong type guarantees of the enum
   // class, that is we cannot pass an unsigned as Directive without an explicit
   // cast.
-  if (DirLang.hasMakeEnumAvailableInNamespace()) { 
+  if (DirLang.hasMakeEnumAvailableInNamespace()) {
     OS << "\n";
     for (const auto &R : Records) {
-      BaseRecord Rec{R}; 
-      OS << "constexpr auto " << Prefix << Rec.getFormattedName() << " = " 
-         << "llvm::" << DirLang.getCppNamespace() << "::" << Enum 
-         << "::" << Prefix << Rec.getFormattedName() << ";\n"; 
+      BaseRecord Rec{R};
+      OS << "constexpr auto " << Prefix << Rec.getFormattedName() << " = "
+         << "llvm::" << DirLang.getCppNamespace() << "::" << Enum
+         << "::" << Prefix << Rec.getFormattedName() << ";\n";
     }
   }
 }
 
-// Generate enums for values that clauses can take. 
-// Also generate function declarations for get<Enum>Name(StringRef Str). 
-void GenerateEnumClauseVal(const std::vector<Record *> &Records, 
-                           raw_ostream &OS, const DirectiveLanguage &DirLang, 
-                           std::string &EnumHelperFuncs) { 
-  for (const auto &R : Records) { 
-    Clause C{R}; 
-    const auto &ClauseVals = C.getClauseVals(); 
-    if (ClauseVals.size() <= 0) 
-      continue; 
- 
-    const auto &EnumName = C.getEnumName(); 
-    if (EnumName.size() == 0) { 
-      PrintError("enumClauseValue field not set in Clause" + 
-                 C.getFormattedName() + "."); 
-      return; 
-    } 
- 
-    OS << "\n"; 
-    OS << "enum class " << EnumName << " {\n"; 
-    for (const auto &CV : ClauseVals) { 
-      ClauseVal CVal{CV}; 
-      OS << "  " << CV->getName() << "=" << CVal.getValue() << ",\n"; 
-    } 
-    OS << "};\n"; 
- 
-    if (DirLang.hasMakeEnumAvailableInNamespace()) { 
-      OS << "\n"; 
-      for (const auto &CV : ClauseVals) { 
-        OS << "constexpr auto " << CV->getName() << " = " 
-           << "llvm::" << DirLang.getCppNamespace() << "::" << EnumName 
-           << "::" << CV->getName() << ";\n"; 
-      } 
-      EnumHelperFuncs += (llvm::Twine(EnumName) + llvm::Twine(" get") + 
-                          llvm::Twine(EnumName) + llvm::Twine("(StringRef);\n")) 
-                             .str(); 
- 
-      EnumHelperFuncs += 
-          (llvm::Twine("llvm::StringRef get") + llvm::Twine(DirLang.getName()) + 
-           llvm::Twine(EnumName) + llvm::Twine("Name(") + 
-           llvm::Twine(EnumName) + llvm::Twine(");\n")) 
-              .str(); 
-    } 
-  } 
-} 
- 
-bool HasDuplicateClauses(const std::vector<Record *> &Clauses, 
-                         const Directive &Directive, 
-                         llvm::StringSet<> &CrtClauses) { 
-  bool HasError = false; 
-  for (const auto &C : Clauses) { 
-    VersionedClause VerClause{C}; 
-    const auto insRes = CrtClauses.insert(VerClause.getClause().getName()); 
-    if (!insRes.second) { 
-      PrintError("Clause " + VerClause.getClause().getRecordName() + 
-                 " already defined on directive " + Directive.getRecordName()); 
-      HasError = true; 
-    } 
-  } 
-  return HasError; 
-} 
- 
-// Check for duplicate clauses in lists. Clauses cannot appear twice in the 
-// three allowed list. Also, since required implies allowed, clauses cannot 
-// appear in both the allowedClauses and requiredClauses lists. 
-bool HasDuplicateClausesInDirectives(const std::vector<Record *> &Directives) { 
-  bool HasDuplicate = false; 
-  for (const auto &D : Directives) { 
-    Directive Dir{D}; 
-    llvm::StringSet<> Clauses; 
-    // Check for duplicates in the three allowed lists. 
-    if (HasDuplicateClauses(Dir.getAllowedClauses(), Dir, Clauses) || 
-        HasDuplicateClauses(Dir.getAllowedOnceClauses(), Dir, Clauses) || 
-        HasDuplicateClauses(Dir.getAllowedExclusiveClauses(), Dir, Clauses)) { 
-      HasDuplicate = true; 
-    } 
-    // Check for duplicate between allowedClauses and required 
-    Clauses.clear(); 
-    if (HasDuplicateClauses(Dir.getAllowedClauses(), Dir, Clauses) || 
-        HasDuplicateClauses(Dir.getRequiredClauses(), Dir, Clauses)) { 
-      HasDuplicate = true; 
-    } 
-    if (HasDuplicate) 
-      PrintFatalError("One or more clauses are defined multiple times on" 
-                      " directive " + 
-                      Dir.getRecordName()); 
-  } 
- 
-  return HasDuplicate; 
-} 
- 
-// Check consitency of records. Return true if an error has been detected. 
-// Return false if the records are valid. 
-bool DirectiveLanguage::HasValidityErrors() const { 
-  if (getDirectiveLanguages().size() != 1) { 
-    PrintFatalError("A single definition of DirectiveLanguage is needed."); 
-    return true; 
-  } 
- 
-  return HasDuplicateClausesInDirectives(getDirectives()); 
-} 
- 
+// Generate enums for values that clauses can take.
+// Also generate function declarations for get<Enum>Name(StringRef Str).
+void GenerateEnumClauseVal(const std::vector<Record *> &Records,
+                           raw_ostream &OS, const DirectiveLanguage &DirLang,
+                           std::string &EnumHelperFuncs) {
+  for (const auto &R : Records) {
+    Clause C{R};
+    const auto &ClauseVals = C.getClauseVals();
+    if (ClauseVals.size() <= 0)
+      continue;
+
+    const auto &EnumName = C.getEnumName();
+    if (EnumName.size() == 0) {
+      PrintError("enumClauseValue field not set in Clause" +
+                 C.getFormattedName() + ".");
+      return;
+    }
+
+    OS << "\n";
+    OS << "enum class " << EnumName << " {\n";
+    for (const auto &CV : ClauseVals) {
+      ClauseVal CVal{CV};
+      OS << "  " << CV->getName() << "=" << CVal.getValue() << ",\n";
+    }
+    OS << "};\n";
+
+    if (DirLang.hasMakeEnumAvailableInNamespace()) {
+      OS << "\n";
+      for (const auto &CV : ClauseVals) {
+        OS << "constexpr auto " << CV->getName() << " = "
+           << "llvm::" << DirLang.getCppNamespace() << "::" << EnumName
+           << "::" << CV->getName() << ";\n";
+      }
+      EnumHelperFuncs += (llvm::Twine(EnumName) + llvm::Twine(" get") +
+                          llvm::Twine(EnumName) + llvm::Twine("(StringRef);\n"))
+                             .str();
+
+      EnumHelperFuncs +=
+          (llvm::Twine("llvm::StringRef get") + llvm::Twine(DirLang.getName()) +
+           llvm::Twine(EnumName) + llvm::Twine("Name(") +
+           llvm::Twine(EnumName) + llvm::Twine(");\n"))
+              .str();
+    }
+  }
+}
+
+bool HasDuplicateClauses(const std::vector<Record *> &Clauses,
+                         const Directive &Directive,
+                         llvm::StringSet<> &CrtClauses) {
+  bool HasError = false;
+  for (const auto &C : Clauses) {
+    VersionedClause VerClause{C};
+    const auto insRes = CrtClauses.insert(VerClause.getClause().getName());
+    if (!insRes.second) {
+      PrintError("Clause " + VerClause.getClause().getRecordName() +
+                 " already defined on directive " + Directive.getRecordName());
+      HasError = true;
+    }
+  }
+  return HasError;
+}
+
+// Check for duplicate clauses in lists. Clauses cannot appear twice in the
+// three allowed list. Also, since required implies allowed, clauses cannot
+// appear in both the allowedClauses and requiredClauses lists.
+bool HasDuplicateClausesInDirectives(const std::vector<Record *> &Directives) {
+  bool HasDuplicate = false;
+  for (const auto &D : Directives) {
+    Directive Dir{D};
+    llvm::StringSet<> Clauses;
+    // Check for duplicates in the three allowed lists.
+    if (HasDuplicateClauses(Dir.getAllowedClauses(), Dir, Clauses) ||
+        HasDuplicateClauses(Dir.getAllowedOnceClauses(), Dir, Clauses) ||
+        HasDuplicateClauses(Dir.getAllowedExclusiveClauses(), Dir, Clauses)) {
+      HasDuplicate = true;
+    }
+    // Check for duplicate between allowedClauses and required
+    Clauses.clear();
+    if (HasDuplicateClauses(Dir.getAllowedClauses(), Dir, Clauses) ||
+        HasDuplicateClauses(Dir.getRequiredClauses(), Dir, Clauses)) {
+      HasDuplicate = true;
+    }
+    if (HasDuplicate)
+      PrintFatalError("One or more clauses are defined multiple times on"
+                      " directive " +
+                      Dir.getRecordName());
+  }
+
+  return HasDuplicate;
+}
+
+// Check consitency of records. Return true if an error has been detected.
+// Return false if the records are valid.
+bool DirectiveLanguage::HasValidityErrors() const {
+  if (getDirectiveLanguages().size() != 1) {
+    PrintFatalError("A single definition of DirectiveLanguage is needed.");
+    return true;
+  }
+
+  return HasDuplicateClausesInDirectives(getDirectives());
+}
+
 // Generate the declaration section for the enumeration in the directive
 // language
 void EmitDirectivesDecl(RecordKeeper &Records, raw_ostream &OS) {
-  const auto DirLang = DirectiveLanguage{Records}; 
-  if (DirLang.HasValidityErrors()) 
+  const auto DirLang = DirectiveLanguage{Records};
+  if (DirLang.HasValidityErrors())
     return;
 
-  OS << "#ifndef LLVM_" << DirLang.getName() << "_INC\n"; 
-  OS << "#define LLVM_" << DirLang.getName() << "_INC\n"; 
+  OS << "#ifndef LLVM_" << DirLang.getName() << "_INC\n";
+  OS << "#define LLVM_" << DirLang.getName() << "_INC\n";
 
-  if (DirLang.hasEnableBitmaskEnumInNamespace()) 
+  if (DirLang.hasEnableBitmaskEnumInNamespace())
     OS << "\n#include \"llvm/ADT/BitmaskEnum.h\"\n";
 
   OS << "\n";
@@ -192,48 +192,48 @@ void EmitDirectivesDecl(RecordKeeper &Records, raw_ostream &OS) {
 
   // Open namespaces defined in the directive language
   llvm::SmallVector<StringRef, 2> Namespaces;
-  llvm::SplitString(DirLang.getCppNamespace(), Namespaces, "::"); 
+  llvm::SplitString(DirLang.getCppNamespace(), Namespaces, "::");
   for (auto Ns : Namespaces)
     OS << "namespace " << Ns << " {\n";
 
-  if (DirLang.hasEnableBitmaskEnumInNamespace()) 
+  if (DirLang.hasEnableBitmaskEnumInNamespace())
     OS << "\nLLVM_ENABLE_BITMASK_ENUMS_IN_NAMESPACE();\n";
 
   // Emit Directive enumeration
-  GenerateEnumClass(DirLang.getDirectives(), OS, "Directive", 
-                    DirLang.getDirectivePrefix(), DirLang); 
+  GenerateEnumClass(DirLang.getDirectives(), OS, "Directive",
+                    DirLang.getDirectivePrefix(), DirLang);
 
   // Emit Clause enumeration
-  GenerateEnumClass(DirLang.getClauses(), OS, "Clause", 
-                    DirLang.getClausePrefix(), DirLang); 
+  GenerateEnumClass(DirLang.getClauses(), OS, "Clause",
+                    DirLang.getClausePrefix(), DirLang);
+
+  // Emit ClauseVal enumeration
+  std::string EnumHelperFuncs;
+  GenerateEnumClauseVal(DirLang.getClauses(), OS, DirLang, EnumHelperFuncs);
 
-  // Emit ClauseVal enumeration 
-  std::string EnumHelperFuncs; 
-  GenerateEnumClauseVal(DirLang.getClauses(), OS, DirLang, EnumHelperFuncs); 
- 
   // Generic function signatures
   OS << "\n";
   OS << "// Enumeration helper functions\n";
-  OS << "Directive get" << DirLang.getName() 
+  OS << "Directive get" << DirLang.getName()
      << "DirectiveKind(llvm::StringRef Str);\n";
   OS << "\n";
-  OS << "llvm::StringRef get" << DirLang.getName() 
+  OS << "llvm::StringRef get" << DirLang.getName()
      << "DirectiveName(Directive D);\n";
   OS << "\n";
-  OS << "Clause get" << DirLang.getName() 
-     << "ClauseKind(llvm::StringRef Str);\n"; 
+  OS << "Clause get" << DirLang.getName()
+     << "ClauseKind(llvm::StringRef Str);\n";
   OS << "\n";
-  OS << "llvm::StringRef get" << DirLang.getName() << "ClauseName(Clause C);\n"; 
+  OS << "llvm::StringRef get" << DirLang.getName() << "ClauseName(Clause C);\n";
   OS << "\n";
   OS << "/// Return true if \\p C is a valid clause for \\p D in version \\p "
      << "Version.\n";
   OS << "bool isAllowedClauseForDirective(Directive D, "
      << "Clause C, unsigned Version);\n";
   OS << "\n";
-  if (EnumHelperFuncs.length() > 0) { 
-    OS << EnumHelperFuncs; 
-    OS << "\n"; 
-  } 
+  if (EnumHelperFuncs.length() > 0) {
+    OS << EnumHelperFuncs;
+    OS << "\n";
+  }
 
   // Closing namespaces
   for (auto Ns : llvm::reverse(Namespaces))
@@ -241,183 +241,183 @@ void EmitDirectivesDecl(RecordKeeper &Records, raw_ostream &OS) {
 
   OS << "} // namespace llvm\n";
 
-  OS << "#endif // LLVM_" << DirLang.getName() << "_INC\n"; 
+  OS << "#endif // LLVM_" << DirLang.getName() << "_INC\n";
 }
 
 // Generate function implementation for get<Enum>Name(StringRef Str)
 void GenerateGetName(const std::vector<Record *> &Records, raw_ostream &OS,
-                     StringRef Enum, const DirectiveLanguage &DirLang, 
-                     StringRef Prefix) { 
+                     StringRef Enum, const DirectiveLanguage &DirLang,
+                     StringRef Prefix) {
   OS << "\n";
-  OS << "llvm::StringRef llvm::" << DirLang.getCppNamespace() << "::get" 
-     << DirLang.getName() << Enum << "Name(" << Enum << " Kind) {\n"; 
+  OS << "llvm::StringRef llvm::" << DirLang.getCppNamespace() << "::get"
+     << DirLang.getName() << Enum << "Name(" << Enum << " Kind) {\n";
   OS << "  switch (Kind) {\n";
   for (const auto &R : Records) {
-    BaseRecord Rec{R}; 
-    OS << "    case " << Prefix << Rec.getFormattedName() << ":\n"; 
+    BaseRecord Rec{R};
+    OS << "    case " << Prefix << Rec.getFormattedName() << ":\n";
     OS << "      return \"";
-    if (Rec.getAlternativeName().empty()) 
-      OS << Rec.getName(); 
+    if (Rec.getAlternativeName().empty())
+      OS << Rec.getName();
     else
-      OS << Rec.getAlternativeName(); 
+      OS << Rec.getAlternativeName();
     OS << "\";\n";
   }
   OS << "  }\n"; // switch
-  OS << "  llvm_unreachable(\"Invalid " << DirLang.getName() << " " << Enum 
+  OS << "  llvm_unreachable(\"Invalid " << DirLang.getName() << " " << Enum
      << " kind\");\n";
   OS << "}\n";
 }
 
 // Generate function implementation for get<Enum>Kind(StringRef Str)
 void GenerateGetKind(const std::vector<Record *> &Records, raw_ostream &OS,
-                     StringRef Enum, const DirectiveLanguage &DirLang, 
-                     StringRef Prefix, bool ImplicitAsUnknown) { 
+                     StringRef Enum, const DirectiveLanguage &DirLang,
+                     StringRef Prefix, bool ImplicitAsUnknown) {
 
-  auto DefaultIt = llvm::find_if( 
-      Records, [](Record *R) { return R->getValueAsBit("isDefault") == true; }); 
+  auto DefaultIt = llvm::find_if(
+      Records, [](Record *R) { return R->getValueAsBit("isDefault") == true; });
 
   if (DefaultIt == Records.end()) {
-    PrintError("At least one " + Enum + " must be defined as default."); 
+    PrintError("At least one " + Enum + " must be defined as default.");
     return;
   }
 
-  BaseRecord DefaultRec{(*DefaultIt)}; 
+  BaseRecord DefaultRec{(*DefaultIt)};
 
   OS << "\n";
-  OS << Enum << " llvm::" << DirLang.getCppNamespace() << "::get" 
-     << DirLang.getName() << Enum << "Kind(llvm::StringRef Str) {\n"; 
+  OS << Enum << " llvm::" << DirLang.getCppNamespace() << "::get"
+     << DirLang.getName() << Enum << "Kind(llvm::StringRef Str) {\n";
   OS << "  return llvm::StringSwitch<" << Enum << ">(Str)\n";
 
   for (const auto &R : Records) {
-    BaseRecord Rec{R}; 
+    BaseRecord Rec{R};
     if (ImplicitAsUnknown && R->getValueAsBit("isImplicit")) {
-      OS << "    .Case(\"" << Rec.getName() << "\"," << Prefix 
-         << DefaultRec.getFormattedName() << ")\n"; 
+      OS << "    .Case(\"" << Rec.getName() << "\"," << Prefix
+         << DefaultRec.getFormattedName() << ")\n";
     } else {
-      OS << "    .Case(\"" << Rec.getName() << "\"," << Prefix 
-         << Rec.getFormattedName() << ")\n"; 
+      OS << "    .Case(\"" << Rec.getName() << "\"," << Prefix
+         << Rec.getFormattedName() << ")\n";
     }
   }
-  OS << "    .Default(" << Prefix << DefaultRec.getFormattedName() << ");\n"; 
+  OS << "    .Default(" << Prefix << DefaultRec.getFormattedName() << ");\n";
   OS << "}\n";
 }
 
-// Generate function implementation for get<ClauseVal>Kind(StringRef Str) 
-void GenerateGetKindClauseVal(const DirectiveLanguage &DirLang, 
-                              raw_ostream &OS) { 
-  for (const auto &R : DirLang.getClauses()) { 
-    Clause C{R}; 
-    const auto &ClauseVals = C.getClauseVals(); 
-    if (ClauseVals.size() <= 0) 
-      continue; 
- 
-    auto DefaultIt = llvm::find_if(ClauseVals, [](Record *CV) { 
-      return CV->getValueAsBit("isDefault") == true; 
-    }); 
- 
-    if (DefaultIt == ClauseVals.end()) { 
-      PrintError("At least one val in Clause " + C.getFormattedName() + 
-                 " must be defined as default."); 
-      return; 
-    } 
-    const auto DefaultName = (*DefaultIt)->getName(); 
- 
-    const auto &EnumName = C.getEnumName(); 
-    if (EnumName.size() == 0) { 
-      PrintError("enumClauseValue field not set in Clause" + 
-                 C.getFormattedName() + "."); 
-      return; 
-    } 
- 
-    OS << "\n"; 
-    OS << EnumName << " llvm::" << DirLang.getCppNamespace() << "::get" 
-       << EnumName << "(llvm::StringRef Str) {\n"; 
-    OS << "  return llvm::StringSwitch<" << EnumName << ">(Str)\n"; 
-    for (const auto &CV : ClauseVals) { 
-      ClauseVal CVal{CV}; 
-      OS << "    .Case(\"" << CVal.getFormattedName() << "\"," << CV->getName() 
-         << ")\n"; 
-    } 
-    OS << "    .Default(" << DefaultName << ");\n"; 
-    OS << "}\n"; 
- 
-    OS << "\n"; 
-    OS << "llvm::StringRef llvm::" << DirLang.getCppNamespace() << "::get" 
-       << DirLang.getName() << EnumName 
-       << "Name(llvm::" << DirLang.getCppNamespace() << "::" << EnumName 
-       << " x) {\n"; 
-    OS << "  switch (x) {\n"; 
-    for (const auto &CV : ClauseVals) { 
-      ClauseVal CVal{CV}; 
-      OS << "    case " << CV->getName() << ":\n"; 
-      OS << "      return \"" << CVal.getFormattedName() << "\";\n"; 
-    } 
-    OS << "  }\n"; // switch 
-    OS << "  llvm_unreachable(\"Invalid " << DirLang.getName() << " " 
-       << EnumName << " kind\");\n"; 
-    OS << "}\n"; 
-  } 
-} 
- 
+// Generate function implementation for get<ClauseVal>Kind(StringRef Str)
+void GenerateGetKindClauseVal(const DirectiveLanguage &DirLang,
+                              raw_ostream &OS) {
+  for (const auto &R : DirLang.getClauses()) {
+    Clause C{R};
+    const auto &ClauseVals = C.getClauseVals();
+    if (ClauseVals.size() <= 0)
+      continue;
+
+    auto DefaultIt = llvm::find_if(ClauseVals, [](Record *CV) {
+      return CV->getValueAsBit("isDefault") == true;
+    });
+
+    if (DefaultIt == ClauseVals.end()) {
+      PrintError("At least one val in Clause " + C.getFormattedName() +
+                 " must be defined as default.");
+      return;
+    }
+    const auto DefaultName = (*DefaultIt)->getName();
+
+    const auto &EnumName = C.getEnumName();
+    if (EnumName.size() == 0) {
+      PrintError("enumClauseValue field not set in Clause" +
+                 C.getFormattedName() + ".");
+      return;
+    }
+
+    OS << "\n";
+    OS << EnumName << " llvm::" << DirLang.getCppNamespace() << "::get"
+       << EnumName << "(llvm::StringRef Str) {\n";
+    OS << "  return llvm::StringSwitch<" << EnumName << ">(Str)\n";
+    for (const auto &CV : ClauseVals) {
+      ClauseVal CVal{CV};
+      OS << "    .Case(\"" << CVal.getFormattedName() << "\"," << CV->getName()
+         << ")\n";
+    }
+    OS << "    .Default(" << DefaultName << ");\n";
+    OS << "}\n";
+
+    OS << "\n";
+    OS << "llvm::StringRef llvm::" << DirLang.getCppNamespace() << "::get"
+       << DirLang.getName() << EnumName
+       << "Name(llvm::" << DirLang.getCppNamespace() << "::" << EnumName
+       << " x) {\n";
+    OS << "  switch (x) {\n";
+    for (const auto &CV : ClauseVals) {
+      ClauseVal CVal{CV};
+      OS << "    case " << CV->getName() << ":\n";
+      OS << "      return \"" << CVal.getFormattedName() << "\";\n";
+    }
+    OS << "  }\n"; // switch
+    OS << "  llvm_unreachable(\"Invalid " << DirLang.getName() << " "
+       << EnumName << " kind\");\n";
+    OS << "}\n";
+  }
+}
+
 void GenerateCaseForVersionedClauses(const std::vector<Record *> &Clauses,
                                      raw_ostream &OS, StringRef DirectiveName,
-                                     const DirectiveLanguage &DirLang, 
+                                     const DirectiveLanguage &DirLang,
                                      llvm::StringSet<> &Cases) {
   for (const auto &C : Clauses) {
-    VersionedClause VerClause{C}; 
-
-    const auto ClauseFormattedName = VerClause.getClause().getFormattedName(); 
- 
-    if (Cases.find(ClauseFormattedName) == Cases.end()) { 
-      Cases.insert(ClauseFormattedName); 
-      OS << "        case " << DirLang.getClausePrefix() << ClauseFormattedName 
-         << ":\n"; 
-      OS << "          return " << VerClause.getMinVersion() 
-         << " <= Version && " << VerClause.getMaxVersion() << " >= Version;\n"; 
+    VersionedClause VerClause{C};
+
+    const auto ClauseFormattedName = VerClause.getClause().getFormattedName();
+
+    if (Cases.find(ClauseFormattedName) == Cases.end()) {
+      Cases.insert(ClauseFormattedName);
+      OS << "        case " << DirLang.getClausePrefix() << ClauseFormattedName
+         << ":\n";
+      OS << "          return " << VerClause.getMinVersion()
+         << " <= Version && " << VerClause.getMaxVersion() << " >= Version;\n";
     }
   }
 }
 
 // Generate the isAllowedClauseForDirective function implementation.
-void GenerateIsAllowedClause(const DirectiveLanguage &DirLang, 
-                             raw_ostream &OS) { 
+void GenerateIsAllowedClause(const DirectiveLanguage &DirLang,
+                             raw_ostream &OS) {
   OS << "\n";
-  OS << "bool llvm::" << DirLang.getCppNamespace() 
-     << "::isAllowedClauseForDirective(" 
+  OS << "bool llvm::" << DirLang.getCppNamespace()
+     << "::isAllowedClauseForDirective("
      << "Directive D, Clause C, unsigned Version) {\n";
-  OS << "  assert(unsigned(D) <= llvm::" << DirLang.getCppNamespace() 
+  OS << "  assert(unsigned(D) <= llvm::" << DirLang.getCppNamespace()
      << "::Directive_enumSize);\n";
-  OS << "  assert(unsigned(C) <= llvm::" << DirLang.getCppNamespace() 
+  OS << "  assert(unsigned(C) <= llvm::" << DirLang.getCppNamespace()
      << "::Clause_enumSize);\n";
 
   OS << "  switch (D) {\n";
 
-  for (const auto &D : DirLang.getDirectives()) { 
-    Directive Dir{D}; 
+  for (const auto &D : DirLang.getDirectives()) {
+    Directive Dir{D};
 
-    OS << "    case " << DirLang.getDirectivePrefix() << Dir.getFormattedName() 
+    OS << "    case " << DirLang.getDirectivePrefix() << Dir.getFormattedName()
        << ":\n";
-    if (Dir.getAllowedClauses().size() == 0 && 
-        Dir.getAllowedOnceClauses().size() == 0 && 
-        Dir.getAllowedExclusiveClauses().size() == 0 && 
-        Dir.getRequiredClauses().size() == 0) { 
+    if (Dir.getAllowedClauses().size() == 0 &&
+        Dir.getAllowedOnceClauses().size() == 0 &&
+        Dir.getAllowedExclusiveClauses().size() == 0 &&
+        Dir.getRequiredClauses().size() == 0) {
       OS << "      return false;\n";
     } else {
       OS << "      switch (C) {\n";
 
       llvm::StringSet<> Cases;
 
-      GenerateCaseForVersionedClauses(Dir.getAllowedClauses(), OS, 
-                                      Dir.getName(), DirLang, Cases); 
+      GenerateCaseForVersionedClauses(Dir.getAllowedClauses(), OS,
+                                      Dir.getName(), DirLang, Cases);
 
-      GenerateCaseForVersionedClauses(Dir.getAllowedOnceClauses(), OS, 
-                                      Dir.getName(), DirLang, Cases); 
+      GenerateCaseForVersionedClauses(Dir.getAllowedOnceClauses(), OS,
+                                      Dir.getName(), DirLang, Cases);
 
-      GenerateCaseForVersionedClauses(Dir.getAllowedExclusiveClauses(), OS, 
-                                      Dir.getName(), DirLang, Cases); 
+      GenerateCaseForVersionedClauses(Dir.getAllowedExclusiveClauses(), OS,
+                                      Dir.getName(), DirLang, Cases);
 
-      GenerateCaseForVersionedClauses(Dir.getRequiredClauses(), OS, 
-                                      Dir.getName(), DirLang, Cases); 
+      GenerateCaseForVersionedClauses(Dir.getRequiredClauses(), OS,
+                                      Dir.getName(), DirLang, Cases);
 
       OS << "        default:\n";
       OS << "          return false;\n";
@@ -427,32 +427,32 @@ void GenerateIsAllowedClause(const DirectiveLanguage &DirLang,
   }
 
   OS << "  }\n"; // End of directives switch
-  OS << "  llvm_unreachable(\"Invalid " << DirLang.getName() 
+  OS << "  llvm_unreachable(\"Invalid " << DirLang.getName()
      << " Directive kind\");\n";
   OS << "}\n"; // End of function isAllowedClauseForDirective
 }
 
 // Generate a simple enum set with the give clauses.
 void GenerateClauseSet(const std::vector<Record *> &Clauses, raw_ostream &OS,
-                       StringRef ClauseSetPrefix, Directive &Dir, 
-                       const DirectiveLanguage &DirLang) { 
+                       StringRef ClauseSetPrefix, Directive &Dir,
+                       const DirectiveLanguage &DirLang) {
 
   OS << "\n";
-  OS << "  static " << DirLang.getClauseEnumSetClass() << " " << ClauseSetPrefix 
-     << DirLang.getDirectivePrefix() << Dir.getFormattedName() << " {\n"; 
+  OS << "  static " << DirLang.getClauseEnumSetClass() << " " << ClauseSetPrefix
+     << DirLang.getDirectivePrefix() << Dir.getFormattedName() << " {\n";
 
   for (const auto &C : Clauses) {
-    VersionedClause VerClause{C}; 
-    OS << "    llvm::" << DirLang.getCppNamespace() 
-       << "::Clause::" << DirLang.getClausePrefix() 
-       << VerClause.getClause().getFormattedName() << ",\n"; 
+    VersionedClause VerClause{C};
+    OS << "    llvm::" << DirLang.getCppNamespace()
+       << "::Clause::" << DirLang.getClausePrefix()
+       << VerClause.getClause().getFormattedName() << ",\n";
   }
   OS << "  };\n";
 }
 
 // Generate an enum set for the 4 kinds of clauses linked to a directive.
-void GenerateDirectiveClauseSets(const DirectiveLanguage &DirLang, 
-                                 raw_ostream &OS) { 
+void GenerateDirectiveClauseSets(const DirectiveLanguage &DirLang,
+                                 raw_ostream &OS) {
 
   IfDefScope Scope("GEN_FLANG_DIRECTIVE_CLAUSE_SETS", OS);
 
@@ -461,24 +461,24 @@ void GenerateDirectiveClauseSets(const DirectiveLanguage &DirLang,
 
   // Open namespaces defined in the directive language.
   llvm::SmallVector<StringRef, 2> Namespaces;
-  llvm::SplitString(DirLang.getCppNamespace(), Namespaces, "::"); 
+  llvm::SplitString(DirLang.getCppNamespace(), Namespaces, "::");
   for (auto Ns : Namespaces)
     OS << "namespace " << Ns << " {\n";
 
-  for (const auto &D : DirLang.getDirectives()) { 
-    Directive Dir{D}; 
+  for (const auto &D : DirLang.getDirectives()) {
+    Directive Dir{D};
 
     OS << "\n";
-    OS << "  // Sets for " << Dir.getName() << "\n"; 
-
-    GenerateClauseSet(Dir.getAllowedClauses(), OS, "allowedClauses_", Dir, 
-                      DirLang); 
-    GenerateClauseSet(Dir.getAllowedOnceClauses(), OS, "allowedOnceClauses_", 
-                      Dir, DirLang); 
-    GenerateClauseSet(Dir.getAllowedExclusiveClauses(), OS, 
-                      "allowedExclusiveClauses_", Dir, DirLang); 
-    GenerateClauseSet(Dir.getRequiredClauses(), OS, "requiredClauses_", Dir, 
-                      DirLang); 
+    OS << "  // Sets for " << Dir.getName() << "\n";
+
+    GenerateClauseSet(Dir.getAllowedClauses(), OS, "allowedClauses_", Dir,
+                      DirLang);
+    GenerateClauseSet(Dir.getAllowedOnceClauses(), OS, "allowedOnceClauses_",
+                      Dir, DirLang);
+    GenerateClauseSet(Dir.getAllowedExclusiveClauses(), OS,
+                      "allowedExclusiveClauses_", Dir, DirLang);
+    GenerateClauseSet(Dir.getRequiredClauses(), OS, "requiredClauses_", Dir,
+                      DirLang);
   }
 
   // Closing namespaces
@@ -491,286 +491,286 @@ void GenerateDirectiveClauseSets(const DirectiveLanguage &DirLang,
 // Generate a map of directive (key) with DirectiveClauses struct as values.
 // The struct holds the 4 sets of enumeration for the 4 kinds of clauses
 // allowances (allowed, allowed once, allowed exclusive and required).
-void GenerateDirectiveClauseMap(const DirectiveLanguage &DirLang, 
-                                raw_ostream &OS) { 
+void GenerateDirectiveClauseMap(const DirectiveLanguage &DirLang,
+                                raw_ostream &OS) {
 
   IfDefScope Scope("GEN_FLANG_DIRECTIVE_CLAUSE_MAP", OS);
 
   OS << "\n";
-  OS << "{\n"; 
+  OS << "{\n";
 
-  for (const auto &D : DirLang.getDirectives()) { 
-    Directive Dir{D}; 
-    OS << "  {llvm::" << DirLang.getCppNamespace() 
-       << "::Directive::" << DirLang.getDirectivePrefix() 
-       << Dir.getFormattedName() << ",\n"; 
+  for (const auto &D : DirLang.getDirectives()) {
+    Directive Dir{D};
+    OS << "  {llvm::" << DirLang.getCppNamespace()
+       << "::Directive::" << DirLang.getDirectivePrefix()
+       << Dir.getFormattedName() << ",\n";
     OS << "    {\n";
-    OS << "      llvm::" << DirLang.getCppNamespace() << "::allowedClauses_" 
-       << DirLang.getDirectivePrefix() << Dir.getFormattedName() << ",\n"; 
-    OS << "      llvm::" << DirLang.getCppNamespace() << "::allowedOnceClauses_" 
-       << DirLang.getDirectivePrefix() << Dir.getFormattedName() << ",\n"; 
-    OS << "      llvm::" << DirLang.getCppNamespace() 
-       << "::allowedExclusiveClauses_" << DirLang.getDirectivePrefix() 
-       << Dir.getFormattedName() << ",\n"; 
-    OS << "      llvm::" << DirLang.getCppNamespace() << "::requiredClauses_" 
-       << DirLang.getDirectivePrefix() << Dir.getFormattedName() << ",\n"; 
+    OS << "      llvm::" << DirLang.getCppNamespace() << "::allowedClauses_"
+       << DirLang.getDirectivePrefix() << Dir.getFormattedName() << ",\n";
+    OS << "      llvm::" << DirLang.getCppNamespace() << "::allowedOnceClauses_"
+       << DirLang.getDirectivePrefix() << Dir.getFormattedName() << ",\n";
+    OS << "      llvm::" << DirLang.getCppNamespace()
+       << "::allowedExclusiveClauses_" << DirLang.getDirectivePrefix()
+       << Dir.getFormattedName() << ",\n";
+    OS << "      llvm::" << DirLang.getCppNamespace() << "::requiredClauses_"
+       << DirLang.getDirectivePrefix() << Dir.getFormattedName() << ",\n";
     OS << "    }\n";
     OS << "  },\n";
   }
 
-  OS << "}\n"; 
+  OS << "}\n";
+}
+
+// Generate classes entry for Flang clauses in the Flang parse-tree
+// If the clause as a non-generic class, no entry is generated.
+// If the clause does not hold a value, an EMPTY_CLASS is used.
+// If the clause class is generic then a WRAPPER_CLASS is used. When the value
+// is optional, the value class is wrapped into a std::optional.
+void GenerateFlangClauseParserClass(const DirectiveLanguage &DirLang,
+                                    raw_ostream &OS) {
+
+  IfDefScope Scope("GEN_FLANG_CLAUSE_PARSER_CLASSES", OS);
+
+  OS << "\n";
+
+  for (const auto &C : DirLang.getClauses()) {
+    Clause Clause{C};
+    if (!Clause.getFlangClass().empty()) {
+      OS << "WRAPPER_CLASS(" << Clause.getFormattedParserClassName() << ", ";
+      if (Clause.isValueOptional() && Clause.isValueList()) {
+        OS << "std::optional<std::list<" << Clause.getFlangClass() << ">>";
+      } else if (Clause.isValueOptional()) {
+        OS << "std::optional<" << Clause.getFlangClass() << ">";
+      } else if (Clause.isValueList()) {
+        OS << "std::list<" << Clause.getFlangClass() << ">";
+      } else {
+        OS << Clause.getFlangClass();
+      }
+    } else {
+      OS << "EMPTY_CLASS(" << Clause.getFormattedParserClassName();
+    }
+    OS << ");\n";
+  }
+}
+
+// Generate a list of the different clause classes for Flang.
+void GenerateFlangClauseParserClassList(const DirectiveLanguage &DirLang,
+                                        raw_ostream &OS) {
+
+  IfDefScope Scope("GEN_FLANG_CLAUSE_PARSER_CLASSES_LIST", OS);
+
+  OS << "\n";
+  llvm::interleaveComma(DirLang.getClauses(), OS, [&](Record *C) {
+    Clause Clause{C};
+    OS << Clause.getFormattedParserClassName() << "\n";
+  });
 }
 
-// Generate classes entry for Flang clauses in the Flang parse-tree 
-// If the clause as a non-generic class, no entry is generated. 
-// If the clause does not hold a value, an EMPTY_CLASS is used. 
-// If the clause class is generic then a WRAPPER_CLASS is used. When the value 
-// is optional, the value class is wrapped into a std::optional. 
-void GenerateFlangClauseParserClass(const DirectiveLanguage &DirLang, 
-                                    raw_ostream &OS) { 
-
-  IfDefScope Scope("GEN_FLANG_CLAUSE_PARSER_CLASSES", OS); 
-
-  OS << "\n"; 
- 
-  for (const auto &C : DirLang.getClauses()) { 
-    Clause Clause{C}; 
-    if (!Clause.getFlangClass().empty()) { 
-      OS << "WRAPPER_CLASS(" << Clause.getFormattedParserClassName() << ", "; 
-      if (Clause.isValueOptional() && Clause.isValueList()) { 
-        OS << "std::optional<std::list<" << Clause.getFlangClass() << ">>"; 
-      } else if (Clause.isValueOptional()) { 
-        OS << "std::optional<" << Clause.getFlangClass() << ">"; 
-      } else if (Clause.isValueList()) { 
-        OS << "std::list<" << Clause.getFlangClass() << ">"; 
-      } else { 
-        OS << Clause.getFlangClass(); 
-      } 
-    } else { 
-      OS << "EMPTY_CLASS(" << Clause.getFormattedParserClassName(); 
-    } 
-    OS << ");\n"; 
-  } 
+// Generate dump node list for the clauses holding a generic class name.
+void GenerateFlangClauseDump(const DirectiveLanguage &DirLang,
+                             raw_ostream &OS) {
+
+  IfDefScope Scope("GEN_FLANG_DUMP_PARSE_TREE_CLAUSES", OS);
+
+  OS << "\n";
+  for (const auto &C : DirLang.getClauses()) {
+    Clause Clause{C};
+    OS << "NODE(" << DirLang.getFlangClauseBaseClass() << ", "
+       << Clause.getFormattedParserClassName() << ")\n";
+  }
 }
 
-// Generate a list of the different clause classes for Flang. 
-void GenerateFlangClauseParserClassList(const DirectiveLanguage &DirLang, 
-                                        raw_ostream &OS) { 
-
-  IfDefScope Scope("GEN_FLANG_CLAUSE_PARSER_CLASSES_LIST", OS); 
-
-  OS << "\n"; 
-  llvm::interleaveComma(DirLang.getClauses(), OS, [&](Record *C) { 
-    Clause Clause{C}; 
-    OS << Clause.getFormattedParserClassName() << "\n"; 
-  }); 
-} 
- 
-// Generate dump node list for the clauses holding a generic class name. 
-void GenerateFlangClauseDump(const DirectiveLanguage &DirLang, 
-                             raw_ostream &OS) { 
- 
-  IfDefScope Scope("GEN_FLANG_DUMP_PARSE_TREE_CLAUSES", OS); 
- 
-  OS << "\n"; 
-  for (const auto &C : DirLang.getClauses()) { 
-    Clause Clause{C}; 
-    OS << "NODE(" << DirLang.getFlangClauseBaseClass() << ", " 
-       << Clause.getFormattedParserClassName() << ")\n"; 
+// Generate Unparse functions for clauses classes in the Flang parse-tree
+// If the clause is a non-generic class, no entry is generated.
+void GenerateFlangClauseUnparse(const DirectiveLanguage &DirLang,
+                                raw_ostream &OS) {
+
+  IfDefScope Scope("GEN_FLANG_CLAUSE_UNPARSE", OS);
+
+  OS << "\n";
+
+  for (const auto &C : DirLang.getClauses()) {
+    Clause Clause{C};
+    if (!Clause.getFlangClass().empty()) {
+      if (Clause.isValueOptional() && Clause.getDefaultValue().empty()) {
+        OS << "void Unparse(const " << DirLang.getFlangClauseBaseClass()
+           << "::" << Clause.getFormattedParserClassName() << " &x) {\n";
+        OS << "  Word(\"" << Clause.getName().upper() << "\");\n";
+
+        OS << "  Walk(\"(\", x.v, \")\");\n";
+        OS << "}\n";
+      } else if (Clause.isValueOptional()) {
+        OS << "void Unparse(const " << DirLang.getFlangClauseBaseClass()
+           << "::" << Clause.getFormattedParserClassName() << " &x) {\n";
+        OS << "  Word(\"" << Clause.getName().upper() << "\");\n";
+        OS << "  Put(\"(\");\n";
+        OS << "  if (x.v.has_value())\n";
+        if (Clause.isValueList())
+          OS << "    Walk(x.v, \",\");\n";
+        else
+          OS << "    Walk(x.v);\n";
+        OS << "  else\n";
+        OS << "    Put(\"" << Clause.getDefaultValue() << "\");\n";
+        OS << "  Put(\")\");\n";
+        OS << "}\n";
+      } else {
+        OS << "void Unparse(const " << DirLang.getFlangClauseBaseClass()
+           << "::" << Clause.getFormattedParserClassName() << " &x) {\n";
+        OS << "  Word(\"" << Clause.getName().upper() << "\");\n";
+        OS << "  Put(\"(\");\n";
+        if (Clause.isValueList())
+          OS << "  Walk(x.v, \",\");\n";
+        else
+          OS << "  Walk(x.v);\n";
+        OS << "  Put(\")\");\n";
+        OS << "}\n";
+      }
+    } else {
+      OS << "void Before(const " << DirLang.getFlangClauseBaseClass()
+         << "::" << Clause.getFormattedParserClassName() << " &) { Word(\""
+         << Clause.getName().upper() << "\"); }\n";
+    }
   }
-} 
-
-// Generate Unparse functions for clauses classes in the Flang parse-tree 
-// If the clause is a non-generic class, no entry is generated. 
-void GenerateFlangClauseUnparse(const DirectiveLanguage &DirLang, 
-                                raw_ostream &OS) { 
-
-  IfDefScope Scope("GEN_FLANG_CLAUSE_UNPARSE", OS); 
-
-  OS << "\n"; 
- 
-  for (const auto &C : DirLang.getClauses()) { 
-    Clause Clause{C}; 
-    if (!Clause.getFlangClass().empty()) { 
-      if (Clause.isValueOptional() && Clause.getDefaultValue().empty()) { 
-        OS << "void Unparse(const " << DirLang.getFlangClauseBaseClass() 
-           << "::" << Clause.getFormattedParserClassName() << " &x) {\n"; 
-        OS << "  Word(\"" << Clause.getName().upper() << "\");\n"; 
- 
-        OS << "  Walk(\"(\", x.v, \")\");\n"; 
-        OS << "}\n"; 
-      } else if (Clause.isValueOptional()) { 
-        OS << "void Unparse(const " << DirLang.getFlangClauseBaseClass() 
-           << "::" << Clause.getFormattedParserClassName() << " &x) {\n"; 
-        OS << "  Word(\"" << Clause.getName().upper() << "\");\n"; 
-        OS << "  Put(\"(\");\n"; 
-        OS << "  if (x.v.has_value())\n"; 
-        if (Clause.isValueList()) 
-          OS << "    Walk(x.v, \",\");\n"; 
-        else 
-          OS << "    Walk(x.v);\n"; 
-        OS << "  else\n"; 
-        OS << "    Put(\"" << Clause.getDefaultValue() << "\");\n"; 
-        OS << "  Put(\")\");\n"; 
-        OS << "}\n"; 
-      } else { 
-        OS << "void Unparse(const " << DirLang.getFlangClauseBaseClass() 
-           << "::" << Clause.getFormattedParserClassName() << " &x) {\n"; 
-        OS << "  Word(\"" << Clause.getName().upper() << "\");\n"; 
-        OS << "  Put(\"(\");\n"; 
-        if (Clause.isValueList()) 
-          OS << "  Walk(x.v, \",\");\n"; 
-        else 
-          OS << "  Walk(x.v);\n"; 
-        OS << "  Put(\")\");\n"; 
-        OS << "}\n"; 
-      } 
-    } else { 
-      OS << "void Before(const " << DirLang.getFlangClauseBaseClass() 
-         << "::" << Clause.getFormattedParserClassName() << " &) { Word(\"" 
-         << Clause.getName().upper() << "\"); }\n"; 
-    } 
-  } 
 }
 
-// Generate the implementation section for the enumeration in the directive 
-// language 
-void EmitDirectivesFlangImpl(const DirectiveLanguage &DirLang, 
-                             raw_ostream &OS) { 
-
-  GenerateDirectiveClauseSets(DirLang, OS); 
-
-  GenerateDirectiveClauseMap(DirLang, OS); 
- 
-  GenerateFlangClauseParserClass(DirLang, OS); 
- 
-  GenerateFlangClauseParserClassList(DirLang, OS); 
- 
-  GenerateFlangClauseDump(DirLang, OS); 
- 
-  GenerateFlangClauseUnparse(DirLang, OS); 
-} 
- 
-void GenerateClauseClassMacro(const DirectiveLanguage &DirLang, 
-                              raw_ostream &OS) { 
-  // Generate macros style information for legacy code in clang 
-  IfDefScope Scope("GEN_CLANG_CLAUSE_CLASS", OS); 
- 
-  OS << "\n"; 
- 
-  OS << "#ifndef CLAUSE\n"; 
-  OS << "#define CLAUSE(Enum, Str, Implicit)\n"; 
-  OS << "#endif\n"; 
-  OS << "#ifndef CLAUSE_CLASS\n"; 
-  OS << "#define CLAUSE_CLASS(Enum, Str, Class)\n"; 
-  OS << "#endif\n"; 
-  OS << "#ifndef CLAUSE_NO_CLASS\n"; 
-  OS << "#define CLAUSE_NO_CLASS(Enum, Str)\n"; 
-  OS << "#endif\n"; 
-  OS << "\n"; 
-  OS << "#define __CLAUSE(Name, Class)                      \\\n"; 
-  OS << "  CLAUSE(" << DirLang.getClausePrefix() 
-     << "##Name, #Name, /* Implicit */ false) \\\n"; 
-  OS << "  CLAUSE_CLASS(" << DirLang.getClausePrefix() 
-     << "##Name, #Name, Class)\n"; 
-  OS << "#define __CLAUSE_NO_CLASS(Name)                    \\\n"; 
-  OS << "  CLAUSE(" << DirLang.getClausePrefix() 
-     << "##Name, #Name, /* Implicit */ false) \\\n"; 
-  OS << "  CLAUSE_NO_CLASS(" << DirLang.getClausePrefix() << "##Name, #Name)\n"; 
-  OS << "#define __IMPLICIT_CLAUSE_CLASS(Name, Str, Class)  \\\n"; 
-  OS << "  CLAUSE(" << DirLang.getClausePrefix() 
-     << "##Name, Str, /* Implicit */ true)    \\\n"; 
-  OS << "  CLAUSE_CLASS(" << DirLang.getClausePrefix() 
-     << "##Name, Str, Class)\n"; 
-  OS << "#define __IMPLICIT_CLAUSE_NO_CLASS(Name, Str)      \\\n"; 
-  OS << "  CLAUSE(" << DirLang.getClausePrefix() 
-     << "##Name, Str, /* Implicit */ true)    \\\n"; 
-  OS << "  CLAUSE_NO_CLASS(" << DirLang.getClausePrefix() << "##Name, Str)\n"; 
-  OS << "\n"; 
- 
-  for (const auto &R : DirLang.getClauses()) { 
-    Clause C{R}; 
-    if (C.getClangClass().empty()) { // NO_CLASS 
-      if (C.isImplicit()) { 
-        OS << "__IMPLICIT_CLAUSE_NO_CLASS(" << C.getFormattedName() << ", \"" 
-           << C.getFormattedName() << "\")\n"; 
-      } else { 
-        OS << "__CLAUSE_NO_CLASS(" << C.getFormattedName() << ")\n"; 
-      } 
-    } else { // CLASS 
-      if (C.isImplicit()) { 
-        OS << "__IMPLICIT_CLAUSE_CLASS(" << C.getFormattedName() << ", \"" 
-           << C.getFormattedName() << "\", " << C.getClangClass() << ")\n"; 
-      } else { 
-        OS << "__CLAUSE(" << C.getFormattedName() << ", " << C.getClangClass() 
-           << ")\n"; 
-      } 
-    } 
+// Generate the implementation section for the enumeration in the directive
+// language
+void EmitDirectivesFlangImpl(const DirectiveLanguage &DirLang,
+                             raw_ostream &OS) {
+
+  GenerateDirectiveClauseSets(DirLang, OS);
+
+  GenerateDirectiveClauseMap(DirLang, OS);
+
+  GenerateFlangClauseParserClass(DirLang, OS);
+
+  GenerateFlangClauseParserClassList(DirLang, OS);
+
+  GenerateFlangClauseDump(DirLang, OS);
+
+  GenerateFlangClauseUnparse(DirLang, OS);
+}
+
+void GenerateClauseClassMacro(const DirectiveLanguage &DirLang,
+                              raw_ostream &OS) {
+  // Generate macros style information for legacy code in clang
+  IfDefScope Scope("GEN_CLANG_CLAUSE_CLASS", OS);
+
+  OS << "\n";
+
+  OS << "#ifndef CLAUSE\n";
+  OS << "#define CLAUSE(Enum, Str, Implicit)\n";
+  OS << "#endif\n";
+  OS << "#ifndef CLAUSE_CLASS\n";
+  OS << "#define CLAUSE_CLASS(Enum, Str, Class)\n";
+  OS << "#endif\n";
+  OS << "#ifndef CLAUSE_NO_CLASS\n";
+  OS << "#define CLAUSE_NO_CLASS(Enum, Str)\n";
+  OS << "#endif\n";
+  OS << "\n";
+  OS << "#define __CLAUSE(Name, Class)                      \\\n";
+  OS << "  CLAUSE(" << DirLang.getClausePrefix()
+     << "##Name, #Name, /* Implicit */ false) \\\n";
+  OS << "  CLAUSE_CLASS(" << DirLang.getClausePrefix()
+     << "##Name, #Name, Class)\n";
+  OS << "#define __CLAUSE_NO_CLASS(Name)                    \\\n";
+  OS << "  CLAUSE(" << DirLang.getClausePrefix()
+     << "##Name, #Name, /* Implicit */ false) \\\n";
+  OS << "  CLAUSE_NO_CLASS(" << DirLang.getClausePrefix() << "##Name, #Name)\n";
+  OS << "#define __IMPLICIT_CLAUSE_CLASS(Name, Str, Class)  \\\n";
+  OS << "  CLAUSE(" << DirLang.getClausePrefix()
+     << "##Name, Str, /* Implicit */ true)    \\\n";
+  OS << "  CLAUSE_CLASS(" << DirLang.getClausePrefix()
+     << "##Name, Str, Class)\n";
+  OS << "#define __IMPLICIT_CLAUSE_NO_CLASS(Name, Str)      \\\n";
+  OS << "  CLAUSE(" << DirLang.getClausePrefix()
+     << "##Name, Str, /* Implicit */ true)    \\\n";
+  OS << "  CLAUSE_NO_CLASS(" << DirLang.getClausePrefix() << "##Name, Str)\n";
+  OS << "\n";
+
+  for (const auto &R : DirLang.getClauses()) {
+    Clause C{R};
+    if (C.getClangClass().empty()) { // NO_CLASS
+      if (C.isImplicit()) {
+        OS << "__IMPLICIT_CLAUSE_NO_CLASS(" << C.getFormattedName() << ", \""
+           << C.getFormattedName() << "\")\n";
+      } else {
+        OS << "__CLAUSE_NO_CLASS(" << C.getFormattedName() << ")\n";
+      }
+    } else { // CLASS
+      if (C.isImplicit()) {
+        OS << "__IMPLICIT_CLAUSE_CLASS(" << C.getFormattedName() << ", \""
+           << C.getFormattedName() << "\", " << C.getClangClass() << ")\n";
+      } else {
+        OS << "__CLAUSE(" << C.getFormattedName() << ", " << C.getClangClass()
+           << ")\n";
+      }
+    }
   }
 
-  OS << "\n"; 
-  OS << "#undef __IMPLICIT_CLAUSE_NO_CLASS\n"; 
-  OS << "#undef __IMPLICIT_CLAUSE_CLASS\n"; 
-  OS << "#undef __CLAUSE\n"; 
-  OS << "#undef CLAUSE_NO_CLASS\n"; 
-  OS << "#undef CLAUSE_CLASS\n"; 
-  OS << "#undef CLAUSE\n"; 
-} 
-
-// Generate the implementation section for the enumeration in the directive 
-// language. 
-void EmitDirectivesGen(RecordKeeper &Records, raw_ostream &OS) { 
-  const auto DirLang = DirectiveLanguage{Records}; 
-  if (DirLang.HasValidityErrors()) 
-    return; 
-
-  EmitDirectivesFlangImpl(DirLang, OS); 
-
-  GenerateClauseClassMacro(DirLang, OS); 
-} 
- 
-// Generate the implementation for the enumeration in the directive 
-// language. This code can be included in library. 
-void EmitDirectivesImpl(RecordKeeper &Records, raw_ostream &OS) { 
-  const auto DirLang = DirectiveLanguage{Records}; 
-  if (DirLang.HasValidityErrors()) 
-    return; 
- 
-  if (!DirLang.getIncludeHeader().empty()) 
-    OS << "#include \"" << DirLang.getIncludeHeader() << "\"\n\n"; 
- 
+  OS << "\n";
+  OS << "#undef __IMPLICIT_CLAUSE_NO_CLASS\n";
+  OS << "#undef __IMPLICIT_CLAUSE_CLASS\n";
+  OS << "#undef __CLAUSE\n";
+  OS << "#undef CLAUSE_NO_CLASS\n";
+  OS << "#undef CLAUSE_CLASS\n";
+  OS << "#undef CLAUSE\n";
+}
+
+// Generate the implementation section for the enumeration in the directive
+// language.
+void EmitDirectivesGen(RecordKeeper &Records, raw_ostream &OS) {
+  const auto DirLang = DirectiveLanguage{Records};
+  if (DirLang.HasValidityErrors())
+    return;
+
+  EmitDirectivesFlangImpl(DirLang, OS);
+
+  GenerateClauseClassMacro(DirLang, OS);
+}
+
+// Generate the implementation for the enumeration in the directive
+// language. This code can be included in library.
+void EmitDirectivesImpl(RecordKeeper &Records, raw_ostream &OS) {
+  const auto DirLang = DirectiveLanguage{Records};
+  if (DirLang.HasValidityErrors())
+    return;
+
+  if (!DirLang.getIncludeHeader().empty())
+    OS << "#include \"" << DirLang.getIncludeHeader() << "\"\n\n";
+
   OS << "#include \"llvm/ADT/StringRef.h\"\n";
   OS << "#include \"llvm/ADT/StringSwitch.h\"\n";
   OS << "#include \"llvm/Support/ErrorHandling.h\"\n";
   OS << "\n";
   OS << "using namespace llvm;\n";
   llvm::SmallVector<StringRef, 2> Namespaces;
-  llvm::SplitString(DirLang.getCppNamespace(), Namespaces, "::"); 
+  llvm::SplitString(DirLang.getCppNamespace(), Namespaces, "::");
   for (auto Ns : Namespaces)
     OS << "using namespace " << Ns << ";\n";
 
   // getDirectiveKind(StringRef Str)
-  GenerateGetKind(DirLang.getDirectives(), OS, "Directive", DirLang, 
-                  DirLang.getDirectivePrefix(), /*ImplicitAsUnknown=*/false); 
+  GenerateGetKind(DirLang.getDirectives(), OS, "Directive", DirLang,
+                  DirLang.getDirectivePrefix(), /*ImplicitAsUnknown=*/false);
 
   // getDirectiveName(Directive Kind)
-  GenerateGetName(DirLang.getDirectives(), OS, "Directive", DirLang, 
-                  DirLang.getDirectivePrefix()); 
+  GenerateGetName(DirLang.getDirectives(), OS, "Directive", DirLang,
+                  DirLang.getDirectivePrefix());
 
   // getClauseKind(StringRef Str)
-  GenerateGetKind(DirLang.getClauses(), OS, "Clause", DirLang, 
-                  DirLang.getClausePrefix(), 
-                  /*ImplicitAsUnknown=*/true); 
+  GenerateGetKind(DirLang.getClauses(), OS, "Clause", DirLang,
+                  DirLang.getClausePrefix(),
+                  /*ImplicitAsUnknown=*/true);
 
   // getClauseName(Clause Kind)
-  GenerateGetName(DirLang.getClauses(), OS, "Clause", DirLang, 
-                  DirLang.getClausePrefix()); 
+  GenerateGetName(DirLang.getClauses(), OS, "Clause", DirLang,
+                  DirLang.getClausePrefix());
+
+  // get<ClauseVal>Kind(StringRef Str)
+  GenerateGetKindClauseVal(DirLang, OS);
 
-  // get<ClauseVal>Kind(StringRef Str) 
-  GenerateGetKindClauseVal(DirLang, OS); 
- 
   // isAllowedClauseForDirective(Directive D, Clause C, unsigned Version)
-  GenerateIsAllowedClause(DirLang, OS); 
+  GenerateIsAllowedClause(DirLang, OS);
 }
 
 } // namespace llvm
diff --git a/contrib/libs/llvm12/utils/TableGen/ExegesisEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/ExegesisEmitter.cpp
index 452b4e36b1..4e532c3716 100644
--- a/contrib/libs/llvm12/utils/TableGen/ExegesisEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/ExegesisEmitter.cpp
@@ -144,7 +144,7 @@ void ExegesisEmitter::emitPfmCountersInfo(const Record &Def,
 
 void ExegesisEmitter::emitPfmCounters(raw_ostream &OS) const {
   // Emit the counter name table.
-  OS << "\nstatic const char *" << Target << "PfmCounterNames[] = {\n"; 
+  OS << "\nstatic const char *" << Target << "PfmCounterNames[] = {\n";
   for (const auto &NameAndIndex : PfmCounterNameTable)
     OS << "  \"" << NameAndIndex.first << "\", // " << NameAndIndex.second
        << "\n";
diff --git a/contrib/libs/llvm12/utils/TableGen/FixedLenDecoderEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/FixedLenDecoderEmitter.cpp
index 4ed833866d..01b39df055 100644
--- a/contrib/libs/llvm12/utils/TableGen/FixedLenDecoderEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/FixedLenDecoderEmitter.cpp
@@ -226,8 +226,8 @@ typedef std::vector<bit_value_t> insn_t;
 
 namespace {
 
-static const uint64_t NO_FIXED_SEGMENTS_SENTINEL = -1ULL; 
- 
+static const uint64_t NO_FIXED_SEGMENTS_SENTINEL = -1ULL;
+
 class FilterChooser;
 
 /// Filter - Filter works with FilterChooser to produce the decoding tree for
@@ -281,7 +281,7 @@ protected:
   std::vector<EncodingIDAndOpcode> VariableInstructions;
 
   // Map of well-known segment value to its delegate.
-  std::map<uint64_t, std::unique_ptr<const FilterChooser>> FilterChooserMap; 
+  std::map<uint64_t, std::unique_ptr<const FilterChooser>> FilterChooserMap;
 
   // Number of instructions which fall under FilteredInstructions category.
   unsigned NumFiltered;
@@ -307,7 +307,7 @@ public:
   const FilterChooser &getVariableFC() const {
     assert(NumFiltered == 1);
     assert(FilterChooserMap.size() == 1);
-    return *(FilterChooserMap.find(NO_FIXED_SEGMENTS_SENTINEL)->second); 
+    return *(FilterChooserMap.find(NO_FIXED_SEGMENTS_SENTINEL)->second);
   }
 
   // Divides the decoding task into sub tasks and delegates them to the
@@ -604,9 +604,9 @@ void Filter::recurse() {
 
     // Delegates to an inferior filter chooser for further processing on this
     // group of instructions whose segment values are variable.
-    FilterChooserMap.insert(std::make_pair(NO_FIXED_SEGMENTS_SENTINEL, 
-        std::make_unique<FilterChooser>(Owner->AllInstructions, 
-            VariableInstructions, Owner->Operands, BitValueArray, *Owner))); 
+    FilterChooserMap.insert(std::make_pair(NO_FIXED_SEGMENTS_SENTINEL,
+        std::make_unique<FilterChooser>(Owner->AllInstructions,
+            VariableInstructions, Owner->Operands, BitValueArray, *Owner)));
   }
 
   // No need to recurse for a singleton filtered instruction.
@@ -675,7 +675,7 @@ void Filter::emitTableEntry(DecoderTableInfo &TableInfo) const {
   for (auto &Filter : FilterChooserMap) {
     // Field value -1 implies a non-empty set of variable instructions.
     // See also recurse().
-    if (Filter.first == NO_FIXED_SEGMENTS_SENTINEL) { 
+    if (Filter.first == NO_FIXED_SEGMENTS_SENTINEL) {
       HasFallthrough = true;
 
       // Each scope should always have at least one filter value to check
@@ -722,7 +722,7 @@ void Filter::emitTableEntry(DecoderTableInfo &TableInfo) const {
   assert(TableInfo.FixupStack.size() > 1 && "fixup stack underflow!");
   FixupScopeList::iterator Source = TableInfo.FixupStack.end() - 1;
   FixupScopeList::iterator Dest = Source - 1;
-  llvm::append_range(*Dest, *Source); 
+  llvm::append_range(*Dest, *Source);
   TableInfo.FixupStack.pop_back();
 
   // If there is no fallthrough, then the final filter should get fixed
@@ -942,7 +942,7 @@ emitPredicateFunction(formatted_raw_ostream &OS, PredicateSet &Predicates,
   // The predicate function is just a big switch statement based on the
   // input predicate index.
   OS.indent(Indentation) << "static bool checkDecoderPredicate(unsigned Idx, "
-    << "const FeatureBitset &Bits) {\n"; 
+    << "const FeatureBitset &Bits) {\n";
   Indentation += 2;
   if (!Predicates.empty()) {
     OS.indent(Indentation) << "switch (Idx) {\n";
@@ -966,7 +966,7 @@ emitDecoderFunction(formatted_raw_ostream &OS, DecoderSet &Decoders,
                     unsigned Indentation) const {
   // The decoder function is just a big switch statement based on the
   // input decoder index.
-  OS.indent(Indentation) << "template <typename InsnType>\n"; 
+  OS.indent(Indentation) << "template <typename InsnType>\n";
   OS.indent(Indentation) << "static DecodeStatus decodeToMCInst(DecodeStatus S,"
     << " unsigned Idx, InsnType insn, MCInst &MI,\n";
   OS.indent(Indentation) << "                                   uint64_t "
@@ -1193,7 +1193,7 @@ bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned &Indentation,
     if (!Pred->getValue("AssemblerMatcherPredicate"))
       continue;
 
-    if (!isa<DagInit>(Pred->getValue("AssemblerCondDag")->getValue())) 
+    if (!isa<DagInit>(Pred->getValue("AssemblerCondDag")->getValue()))
       continue;
 
     const DagInit *D = Pred->getValueAsDag("AssemblerCondDag");
@@ -1887,7 +1887,7 @@ populateInstruction(CodeGenTarget &Target, const Record &EncodingDef,
     for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
       // Ignore fixed fields in the record, we're looking for values like:
       //    bits<5> RST = { ?, ?, ?, ?, ? };
-      if (Vals[i].isNonconcreteOK() || Vals[i].getValue()->isComplete()) 
+      if (Vals[i].isNonconcreteOK() || Vals[i].getValue()->isComplete())
         continue;
 
       // Determine if Vals[i] actually contributes to the Inst encoding.
@@ -2010,8 +2010,8 @@ populateInstruction(CodeGenTarget &Target, const Record &EncodingDef,
   // For each operand, see if we can figure out where it is encoded.
   for (const auto &Op : InOutOperands) {
     if (!NumberedInsnOperands[std::string(Op.second)].empty()) {
-      llvm::append_range(InsnOperands, 
-                         NumberedInsnOperands[std::string(Op.second)]); 
+      llvm::append_range(InsnOperands,
+                         NumberedInsnOperands[std::string(Op.second)]);
       continue;
     }
     if (!NumberedInsnOperands[TiedNames[std::string(Op.second)]].empty()) {
@@ -2162,7 +2162,7 @@ static void emitFieldFromInstruction(formatted_raw_ostream &OS) {
      << "// * Support shift (<<, >>) with signed and unsigned integers on the "
         "RHS\n"
      << "// * Support put (<<) to raw_ostream&\n"
-     << "template <typename InsnType>\n" 
+     << "template <typename InsnType>\n"
      << "#if defined(_MSC_VER) && !defined(__clang__)\n"
      << "__declspec(noinline)\n"
      << "#endif\n"
@@ -2182,7 +2182,7 @@ static void emitFieldFromInstruction(formatted_raw_ostream &OS) {
      << "  return (insn & fieldMask) >> startBit;\n"
      << "}\n"
      << "\n"
-     << "template <typename InsnType>\n" 
+     << "template <typename InsnType>\n"
      << "static InsnType fieldFromInstruction(InsnType insn, unsigned "
         "startBit,\n"
      << "                                     unsigned numBits, "
@@ -2193,7 +2193,7 @@ static void emitFieldFromInstruction(formatted_raw_ostream &OS) {
      << "  return (insn >> startBit) & fieldMask;\n"
      << "}\n"
      << "\n"
-     << "template <typename InsnType>\n" 
+     << "template <typename InsnType>\n"
      << "static InsnType fieldFromInstruction(InsnType insn, unsigned "
         "startBit,\n"
      << "                                     unsigned numBits) {\n"
@@ -2205,14 +2205,14 @@ static void emitFieldFromInstruction(formatted_raw_ostream &OS) {
 // emitDecodeInstruction - Emit the templated helper function
 // decodeInstruction().
 static void emitDecodeInstruction(formatted_raw_ostream &OS) {
-  OS << "template <typename InsnType>\n" 
+  OS << "template <typename InsnType>\n"
      << "static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], "
         "MCInst &MI,\n"
      << "                                      InsnType insn, uint64_t "
         "Address,\n"
      << "                                      const void *DisAsm,\n"
      << "                                      const MCSubtargetInfo &STI) {\n"
-     << "  const FeatureBitset &Bits = STI.getFeatureBits();\n" 
+     << "  const FeatureBitset &Bits = STI.getFeatureBits();\n"
      << "\n"
      << "  const uint8_t *Ptr = DecodeTable;\n"
      << "  InsnType CurFieldValue = 0;\n"
@@ -2374,7 +2374,7 @@ static void emitDecodeInstruction(formatted_raw_ostream &OS) {
      << "      if (Fail)\n"
      << "        S = MCDisassembler::SoftFail;\n"
      << "      LLVM_DEBUG(dbgs() << Loc << \": OPC_SoftFail: \" << (Fail ? "
-        "\"FAIL\\n\" : \"PASS\\n\"));\n" 
+        "\"FAIL\\n\" : \"PASS\\n\"));\n"
      << "      break;\n"
      << "    }\n"
      << "    case MCD::OPC_Fail: {\n"
@@ -2392,7 +2392,7 @@ static void emitDecodeInstruction(formatted_raw_ostream &OS) {
 void FixedLenDecoderEmitter::run(raw_ostream &o) {
   formatted_raw_ostream OS(o);
   OS << "#include \"llvm/MC/MCInst.h\"\n";
-  OS << "#include \"llvm/Support/DataTypes.h\"\n"; 
+  OS << "#include \"llvm/Support/DataTypes.h\"\n";
   OS << "#include \"llvm/Support/Debug.h\"\n";
   OS << "#include \"llvm/Support/LEB128.h\"\n";
   OS << "#include \"llvm/Support/raw_ostream.h\"\n";
diff --git a/contrib/libs/llvm12/utils/TableGen/GICombinerEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/GICombinerEmitter.cpp
index 9390a062ba..ab00cff639 100644
--- a/contrib/libs/llvm12/utils/TableGen/GICombinerEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/GICombinerEmitter.cpp
@@ -150,7 +150,7 @@ protected:
 
   /// A block of arbitrary C++ to finish testing the match.
   /// FIXME: This is a temporary measure until we have actual pattern matching
-  const StringInit *MatchingFixupCode = nullptr; 
+  const StringInit *MatchingFixupCode = nullptr;
 
   /// The MatchData defined by the match stage and required by the apply stage.
   /// This allows the plumbing of arbitrary data from C++ predicates between the
@@ -199,7 +199,7 @@ public:
   unsigned allocUID() { return UID++; }
   StringRef getName() const { return TheDef.getName(); }
   const Record &getDef() const { return TheDef; }
-  const StringInit *getMatchingFixupCode() const { return MatchingFixupCode; } 
+  const StringInit *getMatchingFixupCode() const { return MatchingFixupCode; }
   size_t getNumRoots() const { return Roots.size(); }
 
   GIMatchDag &getMatchDag() { return MatchDag; }
@@ -432,9 +432,9 @@ bool CombineRule::parseInstructionMatcher(
       }
 
       if (InstrOperand.isDef()) {
-        if (any_of(Roots, [&](const RootInfo &X) { 
+        if (any_of(Roots, [&](const RootInfo &X) {
               return X.getPatternSymbol() == Name;
-            })) { 
+            })) {
           N->setMatchRoot();
         }
       }
@@ -460,9 +460,9 @@ bool CombineRule::parseWipMatchOpcodeMatcher(const CodeGenTarget &Target,
         MatchDag.addInstrNode(makeDebugName(*this, Name), insertStrTab(Name),
                               MatchDag.getContext().makeEmptyOperandList());
 
-    if (any_of(Roots, [&](const RootInfo &X) { 
+    if (any_of(Roots, [&](const RootInfo &X) {
           return ArgName && X.getPatternSymbol() == ArgName->getValue();
-        })) { 
+        })) {
       N->setMatchRoot();
     }
 
@@ -514,10 +514,10 @@ bool CombineRule::parseMatcher(const CodeGenTarget &Target) {
 
 
     // Parse arbitrary C++ code we have in lieu of supporting MIR matching
-    if (const StringInit *StringI = dyn_cast<StringInit>(Matchers->getArg(I))) { 
+    if (const StringInit *StringI = dyn_cast<StringInit>(Matchers->getArg(I))) {
       assert(!MatchingFixupCode &&
              "Only one block of arbitrary code is currently permitted");
-      MatchingFixupCode = StringI; 
+      MatchingFixupCode = StringI;
       MatchDag.setHasPostMatchPredicate(true);
       continue;
     }
@@ -589,7 +589,7 @@ bool CombineRule::parseMatcher(const CodeGenTarget &Target) {
 }
 
 class GICombinerEmitter {
-  RecordKeeper &Records; 
+  RecordKeeper &Records;
   StringRef Name;
   const CodeGenTarget &Target;
   Record *Combiner;
@@ -622,7 +622,7 @@ public:
 GICombinerEmitter::GICombinerEmitter(RecordKeeper &RK,
                                      const CodeGenTarget &Target,
                                      StringRef Name, Record *Combiner)
-    : Records(RK), Name(Name), Target(Target), Combiner(Combiner) {} 
+    : Records(RK), Name(Name), Target(Target), Combiner(Combiner) {}
 
 void GICombinerEmitter::emitNameMatcher(raw_ostream &OS) const {
   std::vector<std::pair<std::string, std::string>> Cases;
@@ -758,7 +758,7 @@ void GICombinerEmitter::generateCodeForTree(raw_ostream &OS,
     DagInit *Applyer = RuleDef.getValueAsDag("Apply");
     if (Applyer->getOperatorAsDef(RuleDef.getLoc())->getName() !=
         "apply") {
-      PrintError(RuleDef.getLoc(), "Expected 'apply' operator in Apply DAG"); 
+      PrintError(RuleDef.getLoc(), "Expected 'apply' operator in Apply DAG");
       return;
     }
 
@@ -799,16 +799,16 @@ void GICombinerEmitter::generateCodeForTree(raw_ostream &OS,
       OS << Indent << "      && [&]() {\n"
          << Indent << "      "
          << CodeExpander(Rule->getMatchingFixupCode()->getValue(), Expansions,
-                         RuleDef.getLoc(), ShowExpansions) 
+                         RuleDef.getLoc(), ShowExpansions)
          << "\n"
          << Indent << "      return true;\n"
          << Indent << "  }()";
     }
     OS << ") {\n" << Indent << "   ";
 
-    if (const StringInit *Code = dyn_cast<StringInit>(Applyer->getArg(0))) { 
+    if (const StringInit *Code = dyn_cast<StringInit>(Applyer->getArg(0))) {
       OS << CodeExpander(Code->getAsUnquotedString(), Expansions,
-                         RuleDef.getLoc(), ShowExpansions) 
+                         RuleDef.getLoc(), ShowExpansions)
          << "\n"
          << Indent << "    return true;\n"
          << Indent << "  }\n";
@@ -846,7 +846,7 @@ static void emitAdditionalHelperMethodArguments(raw_ostream &OS,
 }
 
 void GICombinerEmitter::run(raw_ostream &OS) {
-  Records.startTimer("Gather rules"); 
+  Records.startTimer("Gather rules");
   gatherRules(Rules, Combiner->getValueAsListOfDefs("Rules"));
   if (StopAfterParse) {
     MatchDagCtx.print(errs());
@@ -858,7 +858,7 @@ void GICombinerEmitter::run(raw_ostream &OS) {
     PrintFatalError(Combiner->getLoc(), "Failed to parse one or more rules");
   LLVM_DEBUG(dbgs() << "Optimizing tree for " << Rules.size() << " rules\n");
   std::unique_ptr<GIMatchTree> Tree;
-  Records.startTimer("Optimize combiner"); 
+  Records.startTimer("Optimize combiner");
   {
     GIMatchTreeBuilder TreeBuilder(0);
     for (const auto &Rule : Rules) {
@@ -881,7 +881,7 @@ void GICombinerEmitter::run(raw_ostream &OS) {
     return;
   }
 
-  Records.startTimer("Emit combiner"); 
+  Records.startTimer("Emit combiner");
   OS << "#ifdef " << Name.upper() << "_GENCOMBINERHELPER_DEPS\n"
      << "#include \"llvm/ADT/SparseBitVector.h\"\n"
      << "namespace llvm {\n"
@@ -905,10 +905,10 @@ void GICombinerEmitter::run(raw_ostream &OS) {
   if (!StateClass.empty())
     OS << " : public " << StateClass;
   OS << " {\n"
-     << "  const " << getClassName() << "RuleConfig *RuleConfig;\n" 
+     << "  const " << getClassName() << "RuleConfig *RuleConfig;\n"
      << "\n"
      << "public:\n"
-     << "  template <typename... Args>" << getClassName() << "(const " 
+     << "  template <typename... Args>" << getClassName() << "(const "
      << getClassName() << "RuleConfig &RuleConfig, Args &&... args) : ";
   if (!StateClass.empty())
     OS << StateClass << "(std::forward<Args>(args)...), ";
@@ -938,9 +938,9 @@ void GICombinerEmitter::run(raw_ostream &OS) {
      << "    if (First >= Last)\n"
      << "      report_fatal_error(\"Beginning of range should be before "
         "end of range\");\n"
-     << "    return {{*First, *Last + 1}};\n" 
+     << "    return {{*First, *Last + 1}};\n"
      << "  } else if (RangePair.first == \"*\") {\n"
-     << "    return {{0, " << Rules.size() << "}};\n" 
+     << "    return {{0, " << Rules.size() << "}};\n"
      << "  } else {\n"
      << "    const auto I = getRuleIdxForIdentifier(RangePair.first);\n"
      << "    if (!I.hasValue())\n"
@@ -954,7 +954,7 @@ void GICombinerEmitter::run(raw_ostream &OS) {
     OS << "bool " << getClassName() << "RuleConfig::setRule"
        << (Enabled ? "Enabled" : "Disabled") << "(StringRef RuleIdentifier) {\n"
        << "  auto MaybeRange = getRuleRangeForIdentifier(RuleIdentifier);\n"
-       << "  if (!MaybeRange.hasValue())\n" 
+       << "  if (!MaybeRange.hasValue())\n"
        << "    return false;\n"
        << "  for (auto I = MaybeRange->first; I < MaybeRange->second; ++I)\n"
        << "    DisabledRules." << (Enabled ? "reset" : "set") << "(I);\n"
@@ -1017,7 +1017,7 @@ void GICombinerEmitter::run(raw_ostream &OS) {
      << "  MachineBasicBlock *MBB = MI.getParent();\n"
      << "  MachineFunction *MF = MBB->getParent();\n"
      << "  MachineRegisterInfo &MRI = MF->getRegInfo();\n"
-     << "  SmallVector<MachineInstr *, 8> MIs = {&MI};\n\n" 
+     << "  SmallVector<MachineInstr *, 8> MIs = {&MI};\n\n"
      << "  (void)MBB; (void)MF; (void)MRI; (void)RuleConfig;\n\n";
 
   OS << "  // Match data\n";
diff --git a/contrib/libs/llvm12/utils/TableGen/GlobalISel/CodeExpander.cpp b/contrib/libs/llvm12/utils/TableGen/GlobalISel/CodeExpander.cpp
index 43efd58f02..3ebb293f46 100644
--- a/contrib/libs/llvm12/utils/TableGen/GlobalISel/CodeExpander.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/GlobalISel/CodeExpander.cpp
@@ -58,15 +58,15 @@ void CodeExpander::emit(raw_ostream &OS) const {
       // Warn if we split because no terminator was found.
       StringRef EndVar = StartVar.drop_front(2 /* ${ */ + Var.size());
       if (EndVar.empty()) {
-        PrintWarning(Loc, "Unterminated expansion '${" + Var + "'"); 
-        PrintNote("Code: [{" + Code + "}]"); 
+        PrintWarning(Loc, "Unterminated expansion '${" + Var + "'");
+        PrintNote("Code: [{" + Code + "}]");
       }
 
       auto ValueI = Expansions.find(Var);
       if (ValueI == Expansions.end()) {
-        PrintError(Loc, 
-                   "Attempt to expand an undeclared variable '" + Var + "'"); 
-        PrintNote("Code: [{" + Code + "}]"); 
+        PrintError(Loc,
+                   "Attempt to expand an undeclared variable '" + Var + "'");
+        PrintNote("Code: [{" + Code + "}]");
       }
       if (ShowExpansions)
         OS << "/*$" << Var << "{*/";
@@ -76,8 +76,8 @@ void CodeExpander::emit(raw_ostream &OS) const {
       continue;
     }
 
-    PrintWarning(Loc, "Assuming missing escape character: \\$"); 
-    PrintNote("Code: [{" + Code + "}]"); 
+    PrintWarning(Loc, "Assuming missing escape character: \\$");
+    PrintNote("Code: [{" + Code + "}]");
     OS << "$";
     Current = Current.drop_front(1);
   }
diff --git a/contrib/libs/llvm12/utils/TableGen/GlobalISel/GIMatchDag.cpp b/contrib/libs/llvm12/utils/TableGen/GlobalISel/GIMatchDag.cpp
index 1a4bd0a7b5..7e037dd03b 100644
--- a/contrib/libs/llvm12/utils/TableGen/GlobalISel/GIMatchDag.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/GlobalISel/GIMatchDag.cpp
@@ -41,7 +41,7 @@ void GIMatchDag::writeDOTGraph(raw_ostream &OS, StringRef ID) const {
     SmallVector<std::pair<unsigned, StringRef>, 8> ToPrint;
     for (const auto &Assignment : N->user_assigned_operand_names())
       ToPrint.emplace_back(Assignment.first, Assignment.second);
-    llvm::sort(ToPrint); 
+    llvm::sort(ToPrint);
     StringRef Separator = "";
     for (const auto &Assignment : ToPrint) {
       OS << Separator << "$" << Assignment.second << "=getOperand("
diff --git a/contrib/libs/llvm12/utils/TableGen/GlobalISel/GIMatchDagInstr.cpp b/contrib/libs/llvm12/utils/TableGen/GlobalISel/GIMatchDagInstr.cpp
index 250d35733d..ad9fbea8f8 100644
--- a/contrib/libs/llvm12/utils/TableGen/GlobalISel/GIMatchDagInstr.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/GlobalISel/GIMatchDagInstr.cpp
@@ -27,7 +27,7 @@ void GIMatchDagInstr::print(raw_ostream &OS) const {
     SmallVector<std::pair<unsigned, StringRef>, 8> ToPrint;
     for (const auto &Assignment : UserAssignedNamesForOperands)
       ToPrint.emplace_back(Assignment.first, Assignment.second);
-    llvm::sort(ToPrint); 
+    llvm::sort(ToPrint);
     StringRef Separator = "";
     for (const auto &Assignment : ToPrint) {
       OS << Separator << "$" << Assignment.second << "=getOperand("
diff --git a/contrib/libs/llvm12/utils/TableGen/GlobalISel/GIMatchTree.cpp b/contrib/libs/llvm12/utils/TableGen/GlobalISel/GIMatchTree.cpp
index 1991ca5b20..d08a83333c 100644
--- a/contrib/libs/llvm12/utils/TableGen/GlobalISel/GIMatchTree.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/GlobalISel/GIMatchTree.cpp
@@ -121,7 +121,7 @@ void GIMatchTreeBuilderLeafInfo::declareInstr(const GIMatchDagInstr *Instr, unsi
     Info.bindOperandVariable(VarBinding.second, ID, VarBinding.first);
 
   // Clear the bit indicating we haven't visited this instr.
-  const auto &NodeI = find(MatchDag.instr_nodes(), Instr); 
+  const auto &NodeI = find(MatchDag.instr_nodes(), Instr);
   assert(NodeI != MatchDag.instr_nodes_end() && "Instr isn't in this DAG");
   unsigned InstrIdx = MatchDag.getInstrNodeIdx(NodeI);
   RemainingInstrNodes.reset(InstrIdx);
@@ -265,10 +265,10 @@ void GIMatchTreeBuilder::runStep() {
       LLVM_DEBUG(dbgs() << "Leaf contains multiple rules, drop after the first "
                            "fully tested rule\n");
       auto FirstFullyTested =
-          llvm::find_if(Leaves, [](const GIMatchTreeBuilderLeafInfo &X) { 
-            return X.isFullyTraversed() && X.isFullyTested() && 
-                   !X.getMatchDag().hasPostMatchPredicate(); 
-          }); 
+          llvm::find_if(Leaves, [](const GIMatchTreeBuilderLeafInfo &X) {
+            return X.isFullyTraversed() && X.isFullyTested() &&
+                   !X.getMatchDag().hasPostMatchPredicate();
+          });
       if (FirstFullyTested != Leaves.end())
         FirstFullyTested++;
 
@@ -454,7 +454,7 @@ void GIMatchTreeOpcodePartitioner::repartition(
         // predicates for one instruction in the same DAG. That should be
         // impossible.
         assert(AllOpcodes && "Conflicting opcode predicates");
-        append_range(OpcodesForThisPredicate, OpcodeP->getInstrs()); 
+        append_range(OpcodesForThisPredicate, OpcodeP->getInstrs());
       }
 
       for (const CodeGenInstruction *Expected : OpcodesForThisPredicate) {
diff --git a/contrib/libs/llvm12/utils/TableGen/GlobalISel/GIMatchTree.h b/contrib/libs/llvm12/utils/TableGen/GlobalISel/GIMatchTree.h
index 4de73e37e6..bf41a2e0e2 100644
--- a/contrib/libs/llvm12/utils/TableGen/GlobalISel/GIMatchTree.h
+++ b/contrib/libs/llvm12/utils/TableGen/GlobalISel/GIMatchTree.h
@@ -353,7 +353,7 @@ public:
   void declareOperand(unsigned InstrID, unsigned OpIdx);
 
   GIMatchTreeInstrInfo *getInstrInfo(unsigned ID) const {
-    return InstrIDToInfo.lookup(ID); 
+    return InstrIDToInfo.lookup(ID);
   }
 
   void dump(raw_ostream &OS) const {
diff --git a/contrib/libs/llvm12/utils/TableGen/GlobalISel/ya.make b/contrib/libs/llvm12/utils/TableGen/GlobalISel/ya.make
index 803b878bc4..4a072b7300 100644
--- a/contrib/libs/llvm12/utils/TableGen/GlobalISel/ya.make
+++ b/contrib/libs/llvm12/utils/TableGen/GlobalISel/ya.make
@@ -12,7 +12,7 @@ LICENSE(Apache-2.0 WITH LLVM-exception)
 LICENSE_TEXTS(.yandex_meta/licenses.list.txt)
 
 PEERDIR(
-    contrib/libs/llvm12 
+    contrib/libs/llvm12
 )
 
 ADDINCL(
diff --git a/contrib/libs/llvm12/utils/TableGen/GlobalISelEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/GlobalISelEmitter.cpp
index f99d7d9f4c..0a6985a3ea 100644
--- a/contrib/libs/llvm12/utils/TableGen/GlobalISelEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/GlobalISelEmitter.cpp
@@ -187,21 +187,21 @@ class InstructionMatcher;
 static Optional<LLTCodeGen> MVTToLLT(MVT::SimpleValueType SVT) {
   MVT VT(SVT);
 
-  if (VT.isScalableVector()) 
-    return None; 
- 
-  if (VT.isFixedLengthVector() && VT.getVectorNumElements() != 1) 
+  if (VT.isScalableVector())
+    return None;
+
+  if (VT.isFixedLengthVector() && VT.getVectorNumElements() != 1)
     return LLTCodeGen(
         LLT::vector(VT.getVectorNumElements(), VT.getScalarSizeInBits()));
 
   if (VT.isInteger() || VT.isFloatingPoint())
     return LLTCodeGen(LLT::scalar(VT.getSizeInBits()));
- 
+
   return None;
 }
 
 static std::string explainPredicates(const TreePatternNode *N) {
-  std::string Explanation; 
+  std::string Explanation;
   StringRef Separator = "";
   for (const TreePredicateCall &Call : N->getPredicateCalls()) {
     const TreePredicateFn &P = Call.Fn;
@@ -305,8 +305,8 @@ static Error failedImport(const Twine &Reason) {
 }
 
 static Error isTrivialOperatorNode(const TreePatternNode *N) {
-  std::string Explanation; 
-  std::string Separator; 
+  std::string Explanation;
+  std::string Separator;
 
   bool HasUnsupportedPredicate = false;
   for (const TreePredicateCall &Call : N->getPredicateCalls()) {
@@ -393,10 +393,10 @@ getNameForFeatureBitset(const std::vector<Record *> &FeatureBitset) {
   return Name;
 }
 
-static std::string getScopedName(unsigned Scope, const std::string &Name) { 
-  return ("pred:" + Twine(Scope) + ":" + Name).str(); 
-} 
- 
+static std::string getScopedName(unsigned Scope, const std::string &Name) {
+  return ("pred:" + Twine(Scope) + ":" + Name).str();
+}
+
 //===- MatchTable Helpers -------------------------------------------------===//
 
 class MatchTable;
@@ -453,8 +453,8 @@ public:
   MatchTableRecord(Optional<unsigned> LabelID_, StringRef EmitStr,
                    unsigned NumElements, unsigned Flags,
                    int64_t RawValue = std::numeric_limits<int64_t>::min())
-      : LabelID(LabelID_.getValueOr(~0u)), EmitStr(EmitStr), 
-        NumElements(NumElements), Flags(Flags), RawValue(RawValue) { 
+      : LabelID(LabelID_.getValueOr(~0u)), EmitStr(EmitStr),
+        NumElements(NumElements), Flags(Flags), RawValue(RawValue) {
     assert((!LabelID_.hasValue() || LabelID != ~0u) &&
            "This value is reserved for non-labels");
   }
@@ -859,11 +859,11 @@ protected:
       DefinedComplexPatternSubOperandMap;
   /// A map of Symbolic Names to ComplexPattern sub-operands.
   DefinedComplexPatternSubOperandMap ComplexSubOperands;
-  /// A map used to for multiple referenced error check of ComplexSubOperand. 
-  /// ComplexSubOperand can't be referenced multiple from different operands, 
-  /// however multiple references from same operand are allowed since that is 
-  /// how 'same operand checks' are generated. 
-  StringMap<std::string> ComplexSubOperandsParentName; 
+  /// A map used to for multiple referenced error check of ComplexSubOperand.
+  /// ComplexSubOperand can't be referenced multiple from different operands,
+  /// however multiple references from same operand are allowed since that is
+  /// how 'same operand checks' are generated.
+  StringMap<std::string> ComplexSubOperandsParentName;
 
   uint64_t RuleID;
   static uint64_t NextRuleID;
@@ -929,25 +929,25 @@ public:
   void definePhysRegOperand(Record *Reg, OperandMatcher &OM);
 
   Error defineComplexSubOperand(StringRef SymbolicName, Record *ComplexPattern,
-                                unsigned RendererID, unsigned SubOperandID, 
-                                StringRef ParentSymbolicName) { 
-    std::string ParentName(ParentSymbolicName); 
-    if (ComplexSubOperands.count(SymbolicName)) { 
-      const std::string &RecordedParentName = 
-          ComplexSubOperandsParentName[SymbolicName]; 
-      if (RecordedParentName != ParentName) 
-        return failedImport("Error: Complex suboperand " + SymbolicName + 
-                            " referenced by different operands: " + 
-                            RecordedParentName + " and " + ParentName + "."); 
-      // Complex suboperand referenced more than once from same the operand is 
-      // used to generate 'same operand check'. Emitting of 
-      // GIR_ComplexSubOperandRenderer for them is already handled. 
-      return Error::success(); 
-    } 
+                                unsigned RendererID, unsigned SubOperandID,
+                                StringRef ParentSymbolicName) {
+    std::string ParentName(ParentSymbolicName);
+    if (ComplexSubOperands.count(SymbolicName)) {
+      const std::string &RecordedParentName =
+          ComplexSubOperandsParentName[SymbolicName];
+      if (RecordedParentName != ParentName)
+        return failedImport("Error: Complex suboperand " + SymbolicName +
+                            " referenced by different operands: " +
+                            RecordedParentName + " and " + ParentName + ".");
+      // Complex suboperand referenced more than once from same the operand is
+      // used to generate 'same operand check'. Emitting of
+      // GIR_ComplexSubOperandRenderer for them is already handled.
+      return Error::success();
+    }
 
     ComplexSubOperands[SymbolicName] =
         std::make_tuple(ComplexPattern, RendererID, SubOperandID);
-    ComplexSubOperandsParentName[SymbolicName] = ParentName; 
+    ComplexSubOperandsParentName[SymbolicName] = ParentName;
 
     return Error::success();
   }
@@ -1108,7 +1108,7 @@ public:
     IPM_MemoryVsLLTSize,
     IPM_MemoryAddressSpace,
     IPM_MemoryAlignment,
-    IPM_VectorSplatImm, 
+    IPM_VectorSplatImm,
     IPM_GenericPredicate,
     OPM_SameOperand,
     OPM_ComplexPattern,
@@ -1121,7 +1121,7 @@ public:
     OPM_PointerToAny,
     OPM_RegBank,
     OPM_MBB,
-    OPM_RecordNamedOperand, 
+    OPM_RecordNamedOperand,
   };
 
 protected:
@@ -1291,15 +1291,15 @@ public:
       : OperandPredicateMatcher(OPM_PointerToAny, InsnVarID, OpIdx),
         SizeInBits(SizeInBits) {}
 
-  static bool classof(const PredicateMatcher *P) { 
+  static bool classof(const PredicateMatcher *P) {
     return P->getKind() == OPM_PointerToAny;
   }
 
-  bool isIdentical(const PredicateMatcher &B) const override { 
-    return OperandPredicateMatcher::isIdentical(B) && 
-           SizeInBits == cast<PointerToAnyOperandMatcher>(&B)->SizeInBits; 
-  } 
- 
+  bool isIdentical(const PredicateMatcher &B) const override {
+    return OperandPredicateMatcher::isIdentical(B) &&
+           SizeInBits == cast<PointerToAnyOperandMatcher>(&B)->SizeInBits;
+  }
+
   void emitPredicateOpcodes(MatchTable &Table,
                             RuleMatcher &Rule) const override {
     Table << MatchTable::Opcode("GIM_CheckPointerToAny")
@@ -1310,40 +1310,40 @@ public:
   }
 };
 
-/// Generates code to record named operand in RecordedOperands list at StoreIdx. 
-/// Predicates with 'let PredicateCodeUsesOperands = 1' get RecordedOperands as 
-/// an argument to predicate's c++ code once all operands have been matched. 
-class RecordNamedOperandMatcher : public OperandPredicateMatcher { 
-protected: 
-  unsigned StoreIdx; 
-  std::string Name; 
- 
-public: 
-  RecordNamedOperandMatcher(unsigned InsnVarID, unsigned OpIdx, 
-                            unsigned StoreIdx, StringRef Name) 
-      : OperandPredicateMatcher(OPM_RecordNamedOperand, InsnVarID, OpIdx), 
-        StoreIdx(StoreIdx), Name(Name) {} 
- 
-  static bool classof(const PredicateMatcher *P) { 
-    return P->getKind() == OPM_RecordNamedOperand; 
-  } 
- 
-  bool isIdentical(const PredicateMatcher &B) const override { 
-    return OperandPredicateMatcher::isIdentical(B) && 
-           StoreIdx == cast<RecordNamedOperandMatcher>(&B)->StoreIdx && 
-           Name == cast<RecordNamedOperandMatcher>(&B)->Name; 
-  } 
- 
-  void emitPredicateOpcodes(MatchTable &Table, 
-                            RuleMatcher &Rule) const override { 
-    Table << MatchTable::Opcode("GIM_RecordNamedOperand") 
-          << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) 
-          << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx) 
-          << MatchTable::Comment("StoreIdx") << MatchTable::IntValue(StoreIdx) 
-          << MatchTable::Comment("Name : " + Name) << MatchTable::LineBreak; 
-  } 
-}; 
- 
+/// Generates code to record named operand in RecordedOperands list at StoreIdx.
+/// Predicates with 'let PredicateCodeUsesOperands = 1' get RecordedOperands as
+/// an argument to predicate's c++ code once all operands have been matched.
+class RecordNamedOperandMatcher : public OperandPredicateMatcher {
+protected:
+  unsigned StoreIdx;
+  std::string Name;
+
+public:
+  RecordNamedOperandMatcher(unsigned InsnVarID, unsigned OpIdx,
+                            unsigned StoreIdx, StringRef Name)
+      : OperandPredicateMatcher(OPM_RecordNamedOperand, InsnVarID, OpIdx),
+        StoreIdx(StoreIdx), Name(Name) {}
+
+  static bool classof(const PredicateMatcher *P) {
+    return P->getKind() == OPM_RecordNamedOperand;
+  }
+
+  bool isIdentical(const PredicateMatcher &B) const override {
+    return OperandPredicateMatcher::isIdentical(B) &&
+           StoreIdx == cast<RecordNamedOperandMatcher>(&B)->StoreIdx &&
+           Name == cast<RecordNamedOperandMatcher>(&B)->Name;
+  }
+
+  void emitPredicateOpcodes(MatchTable &Table,
+                            RuleMatcher &Rule) const override {
+    Table << MatchTable::Opcode("GIM_RecordNamedOperand")
+          << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID)
+          << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx)
+          << MatchTable::Comment("StoreIdx") << MatchTable::IntValue(StoreIdx)
+          << MatchTable::Comment("Name : " + Name) << MatchTable::LineBreak;
+  }
+};
+
 /// Generates code to check that an operand is a particular target constant.
 class ComplexPatternOperandMatcher : public OperandPredicateMatcher {
 protected:
@@ -1583,7 +1583,7 @@ public:
         AllocatedTemporariesBaseID(AllocatedTemporariesBaseID) {}
 
   bool hasSymbolicName() const { return !SymbolicName.empty(); }
-  StringRef getSymbolicName() const { return SymbolicName; } 
+  StringRef getSymbolicName() const { return SymbolicName; }
   void setSymbolicName(StringRef Name) {
     assert(SymbolicName.empty() && "Operand already has a symbolic name");
     SymbolicName = std::string(Name);
@@ -1730,23 +1730,23 @@ PredicateListMatcher<PredicateMatcher>::getNoPredicateComment() const {
 /// Generates code to check the opcode of an instruction.
 class InstructionOpcodeMatcher : public InstructionPredicateMatcher {
 protected:
-  // Allow matching one to several, similar opcodes that share properties. This 
-  // is to handle patterns where one SelectionDAG operation maps to multiple 
-  // GlobalISel ones (e.g. G_BUILD_VECTOR and G_BUILD_VECTOR_TRUNC). The first 
-  // is treated as the canonical opcode. 
-  SmallVector<const CodeGenInstruction *, 2> Insts; 
+  // Allow matching one to several, similar opcodes that share properties. This
+  // is to handle patterns where one SelectionDAG operation maps to multiple
+  // GlobalISel ones (e.g. G_BUILD_VECTOR and G_BUILD_VECTOR_TRUNC). The first
+  // is treated as the canonical opcode.
+  SmallVector<const CodeGenInstruction *, 2> Insts;
 
   static DenseMap<const CodeGenInstruction *, unsigned> OpcodeValues;
 
- 
-  MatchTableRecord getInstValue(const CodeGenInstruction *I) const { 
-    const auto VI = OpcodeValues.find(I); 
-    if (VI != OpcodeValues.end()) 
-      return MatchTable::NamedValue(I->Namespace, I->TheDef->getName(), 
-                                    VI->second); 
-    return MatchTable::NamedValue(I->Namespace, I->TheDef->getName()); 
-  } 
- 
+
+  MatchTableRecord getInstValue(const CodeGenInstruction *I) const {
+    const auto VI = OpcodeValues.find(I);
+    if (VI != OpcodeValues.end())
+      return MatchTable::NamedValue(I->Namespace, I->TheDef->getName(),
+                                    VI->second);
+    return MatchTable::NamedValue(I->Namespace, I->TheDef->getName());
+  }
+
 public:
   static void initOpcodeValuesMap(const CodeGenTarget &Target) {
     OpcodeValues.clear();
@@ -1756,13 +1756,13 @@ public:
       OpcodeValues[I] = OpcodeValue++;
   }
 
-  InstructionOpcodeMatcher(unsigned InsnVarID, 
-                           ArrayRef<const CodeGenInstruction *> I) 
-      : InstructionPredicateMatcher(IPM_Opcode, InsnVarID), 
-        Insts(I.begin(), I.end()) { 
-    assert((Insts.size() == 1 || Insts.size() == 2) && 
-           "unexpected number of opcode alternatives"); 
-  } 
+  InstructionOpcodeMatcher(unsigned InsnVarID,
+                           ArrayRef<const CodeGenInstruction *> I)
+      : InstructionPredicateMatcher(IPM_Opcode, InsnVarID),
+        Insts(I.begin(), I.end()) {
+    assert((Insts.size() == 1 || Insts.size() == 2) &&
+           "unexpected number of opcode alternatives");
+  }
 
   static bool classof(const PredicateMatcher *P) {
     return P->getKind() == IPM_Opcode;
@@ -1770,19 +1770,19 @@ public:
 
   bool isIdentical(const PredicateMatcher &B) const override {
     return InstructionPredicateMatcher::isIdentical(B) &&
-           Insts == cast<InstructionOpcodeMatcher>(&B)->Insts; 
-  }
- 
-  bool hasValue() const override { 
-    return Insts.size() == 1 && OpcodeValues.count(Insts[0]); 
-  } 
- 
-  // TODO: This is used for the SwitchMatcher optimization. We should be able to 
-  // return a list of the opcodes to match. 
+           Insts == cast<InstructionOpcodeMatcher>(&B)->Insts;
+  }
+
+  bool hasValue() const override {
+    return Insts.size() == 1 && OpcodeValues.count(Insts[0]);
+  }
+
+  // TODO: This is used for the SwitchMatcher optimization. We should be able to
+  // return a list of the opcodes to match.
   MatchTableRecord getValue() const override {
-    assert(Insts.size() == 1); 
- 
-    const CodeGenInstruction *I = Insts[0]; 
+    assert(Insts.size() == 1);
+
+    const CodeGenInstruction *I = Insts[0];
     const auto VI = OpcodeValues.find(I);
     if (VI != OpcodeValues.end())
       return MatchTable::NamedValue(I->Namespace, I->TheDef->getName(),
@@ -1792,14 +1792,14 @@ public:
 
   void emitPredicateOpcodes(MatchTable &Table,
                             RuleMatcher &Rule) const override {
-    StringRef CheckType = Insts.size() == 1 ? 
-                          "GIM_CheckOpcode" : "GIM_CheckOpcodeIsEither"; 
-    Table << MatchTable::Opcode(CheckType) << MatchTable::Comment("MI") 
-          << MatchTable::IntValue(InsnVarID); 
- 
-    for (const CodeGenInstruction *I : Insts) 
-      Table << getInstValue(I); 
-    Table << MatchTable::LineBreak; 
+    StringRef CheckType = Insts.size() == 1 ?
+                          "GIM_CheckOpcode" : "GIM_CheckOpcodeIsEither";
+    Table << MatchTable::Opcode(CheckType) << MatchTable::Comment("MI")
+          << MatchTable::IntValue(InsnVarID);
+
+    for (const CodeGenInstruction *I : Insts)
+      Table << getInstValue(I);
+    Table << MatchTable::LineBreak;
   }
 
   /// Compare the priority of this object and B.
@@ -1817,32 +1817,32 @@ public:
     // using instruction frequency information to improve compile time.
     if (const InstructionOpcodeMatcher *BO =
             dyn_cast<InstructionOpcodeMatcher>(&B))
-      return Insts[0]->TheDef->getName() < BO->Insts[0]->TheDef->getName(); 
+      return Insts[0]->TheDef->getName() < BO->Insts[0]->TheDef->getName();
 
     return false;
   };
 
   bool isConstantInstruction() const {
-    return Insts.size() == 1 && Insts[0]->TheDef->getName() == "G_CONSTANT"; 
-  }
-
-  // The first opcode is the canonical opcode, and later are alternatives. 
-  StringRef getOpcode() const { 
-    return Insts[0]->TheDef->getName(); 
-  } 
-
-  ArrayRef<const CodeGenInstruction *> getAlternativeOpcodes() { 
-    return Insts; 
-  } 
- 
-  bool isVariadicNumOperands() const { 
-    // If one is variadic, they all should be. 
-    return Insts[0]->Operands.isVariadic; 
-  } 
- 
+    return Insts.size() == 1 && Insts[0]->TheDef->getName() == "G_CONSTANT";
+  }
+
+  // The first opcode is the canonical opcode, and later are alternatives.
+  StringRef getOpcode() const {
+    return Insts[0]->TheDef->getName();
+  }
+
+  ArrayRef<const CodeGenInstruction *> getAlternativeOpcodes() {
+    return Insts;
+  }
+
+  bool isVariadicNumOperands() const {
+    // If one is variadic, they all should be.
+    return Insts[0]->Operands.isVariadic;
+  }
+
   StringRef getOperandType(unsigned OpIdx) const {
-    // Types expected to be uniform for all alternatives. 
-    return Insts[0]->Operands[OpIdx].OperandType; 
+    // Types expected to be uniform for all alternatives.
+    return Insts[0]->Operands[OpIdx].OperandType;
   }
 };
 
@@ -2125,42 +2125,42 @@ public:
   }
 };
 
-// Matcher for immAllOnesV/immAllZerosV 
-class VectorSplatImmPredicateMatcher : public InstructionPredicateMatcher { 
-public: 
-  enum SplatKind { 
-    AllZeros, 
-    AllOnes 
-  }; 
- 
-private: 
-  SplatKind Kind; 
- 
-public: 
-  VectorSplatImmPredicateMatcher(unsigned InsnVarID, SplatKind K) 
-      : InstructionPredicateMatcher(IPM_VectorSplatImm, InsnVarID), Kind(K) {} 
- 
-  static bool classof(const PredicateMatcher *P) { 
-    return P->getKind() == IPM_VectorSplatImm; 
-  } 
- 
-  bool isIdentical(const PredicateMatcher &B) const override { 
-    return InstructionPredicateMatcher::isIdentical(B) && 
-           Kind == static_cast<const VectorSplatImmPredicateMatcher &>(B).Kind; 
-  } 
- 
-  void emitPredicateOpcodes(MatchTable &Table, 
-                            RuleMatcher &Rule) const override { 
-    if (Kind == AllOnes) 
-      Table << MatchTable::Opcode("GIM_CheckIsBuildVectorAllOnes"); 
-    else 
-      Table << MatchTable::Opcode("GIM_CheckIsBuildVectorAllZeros"); 
- 
-    Table << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID); 
-    Table << MatchTable::LineBreak; 
-  } 
-}; 
- 
+// Matcher for immAllOnesV/immAllZerosV
+class VectorSplatImmPredicateMatcher : public InstructionPredicateMatcher {
+public:
+  enum SplatKind {
+    AllZeros,
+    AllOnes
+  };
+
+private:
+  SplatKind Kind;
+
+public:
+  VectorSplatImmPredicateMatcher(unsigned InsnVarID, SplatKind K)
+      : InstructionPredicateMatcher(IPM_VectorSplatImm, InsnVarID), Kind(K) {}
+
+  static bool classof(const PredicateMatcher *P) {
+    return P->getKind() == IPM_VectorSplatImm;
+  }
+
+  bool isIdentical(const PredicateMatcher &B) const override {
+    return InstructionPredicateMatcher::isIdentical(B) &&
+           Kind == static_cast<const VectorSplatImmPredicateMatcher &>(B).Kind;
+  }
+
+  void emitPredicateOpcodes(MatchTable &Table,
+                            RuleMatcher &Rule) const override {
+    if (Kind == AllOnes)
+      Table << MatchTable::Opcode("GIM_CheckIsBuildVectorAllOnes");
+    else
+      Table << MatchTable::Opcode("GIM_CheckIsBuildVectorAllZeros");
+
+    Table << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID);
+    Table << MatchTable::LineBreak;
+  }
+};
+
 /// Generates code to check an arbitrary C++ instruction predicate.
 class GenericInstructionPredicateMatcher : public InstructionPredicateMatcher {
 protected:
@@ -2217,9 +2217,9 @@ protected:
   SmallVector<std::pair<Record *, unsigned>, 2> PhysRegInputs;
 
 public:
-  InstructionMatcher(RuleMatcher &Rule, StringRef SymbolicName, 
-                     bool NumOpsCheck = true) 
-      : Rule(Rule), NumOperandsCheck(NumOpsCheck), SymbolicName(SymbolicName) { 
+  InstructionMatcher(RuleMatcher &Rule, StringRef SymbolicName,
+                     bool NumOpsCheck = true)
+      : Rule(Rule), NumOperandsCheck(NumOpsCheck), SymbolicName(SymbolicName) {
     // We create a new instruction matcher.
     // Get a new ID for that instruction.
     InsnVarID = Rule.implicitlyDefineInsnVar(*this);
@@ -2249,10 +2249,10 @@ public:
   }
 
   OperandMatcher &getOperand(unsigned OpIdx) {
-    auto I = llvm::find_if(Operands, 
-                           [&OpIdx](const std::unique_ptr<OperandMatcher> &X) { 
-                             return X->getOpIdx() == OpIdx; 
-                           }); 
+    auto I = llvm::find_if(Operands,
+                           [&OpIdx](const std::unique_ptr<OperandMatcher> &X) {
+                             return X->getOpIdx() == OpIdx;
+                           });
     if (I != Operands.end())
       return **I;
     llvm_unreachable("Failed to lookup operand");
@@ -2408,10 +2408,10 @@ protected:
 
 public:
   InstructionOperandMatcher(unsigned InsnVarID, unsigned OpIdx,
-                            RuleMatcher &Rule, StringRef SymbolicName, 
-                            bool NumOpsCheck = true) 
+                            RuleMatcher &Rule, StringRef SymbolicName,
+                            bool NumOpsCheck = true)
       : OperandPredicateMatcher(OPM_Instruction, InsnVarID, OpIdx),
-        InsnMatcher(new InstructionMatcher(Rule, SymbolicName, NumOpsCheck)) {} 
+        InsnMatcher(new InstructionMatcher(Rule, SymbolicName, NumOpsCheck)) {}
 
   static bool classof(const PredicateMatcher *P) {
     return P->getKind() == OPM_Instruction;
@@ -2537,7 +2537,7 @@ public:
     return R->getKind() == OR_Copy;
   }
 
-  StringRef getSymbolicName() const { return SymbolicName; } 
+  StringRef getSymbolicName() const { return SymbolicName; }
 
   void emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const override {
     const OperandMatcher &Operand = Rule.getOperandMatcher(SymbolicName);
@@ -2604,7 +2604,7 @@ public:
     return R->getKind() == OR_CopyOrAddZeroReg;
   }
 
-  StringRef getSymbolicName() const { return SymbolicName; } 
+  StringRef getSymbolicName() const { return SymbolicName; }
 
   void emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const override {
     const OperandMatcher &Operand = Rule.getOperandMatcher(SymbolicName);
@@ -2641,7 +2641,7 @@ public:
     return R->getKind() == OR_CopyConstantAsImm;
   }
 
-  StringRef getSymbolicName() const { return SymbolicName; } 
+  StringRef getSymbolicName() const { return SymbolicName; }
 
   void emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const override {
     InstructionMatcher &InsnMatcher = Rule.getInstructionMatcher(SymbolicName);
@@ -2672,7 +2672,7 @@ public:
     return R->getKind() == OR_CopyFConstantAsFPImm;
   }
 
-  StringRef getSymbolicName() const { return SymbolicName; } 
+  StringRef getSymbolicName() const { return SymbolicName; }
 
   void emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const override {
     InstructionMatcher &InsnMatcher = Rule.getInstructionMatcher(SymbolicName);
@@ -2706,7 +2706,7 @@ public:
     return R->getKind() == OR_CopySubReg;
   }
 
-  StringRef getSymbolicName() const { return SymbolicName; } 
+  StringRef getSymbolicName() const { return SymbolicName; }
 
   void emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const override {
     const OperandMatcher &Operand = Rule.getOperandMatcher(SymbolicName);
@@ -2729,13 +2729,13 @@ protected:
   unsigned InsnID;
   const Record *RegisterDef;
   bool IsDef;
-  const CodeGenTarget &Target; 
+  const CodeGenTarget &Target;
 
 public:
-  AddRegisterRenderer(unsigned InsnID, const CodeGenTarget &Target, 
-                      const Record *RegisterDef, bool IsDef = false) 
+  AddRegisterRenderer(unsigned InsnID, const CodeGenTarget &Target,
+                      const Record *RegisterDef, bool IsDef = false)
       : OperandRenderer(OR_Register), InsnID(InsnID), RegisterDef(RegisterDef),
-        IsDef(IsDef), Target(Target) {} 
+        IsDef(IsDef), Target(Target) {}
 
   static bool classof(const OperandRenderer *R) {
     return R->getKind() == OR_Register;
@@ -2743,17 +2743,17 @@ public:
 
   void emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const override {
     Table << MatchTable::Opcode("GIR_AddRegister")
-          << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID); 
-    if (RegisterDef->getName() != "zero_reg") { 
-      Table << MatchTable::NamedValue( 
-                   (RegisterDef->getValue("Namespace") 
-                        ? RegisterDef->getValueAsString("Namespace") 
-                        : ""), 
-                   RegisterDef->getName()); 
-    } else { 
-      Table << MatchTable::NamedValue(Target.getRegNamespace(), "NoRegister"); 
-    } 
-    Table << MatchTable::Comment("AddRegisterRegFlags"); 
+          << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID);
+    if (RegisterDef->getName() != "zero_reg") {
+      Table << MatchTable::NamedValue(
+                   (RegisterDef->getValue("Namespace")
+                        ? RegisterDef->getValueAsString("Namespace")
+                        : ""),
+                   RegisterDef->getName());
+    } else {
+      Table << MatchTable::NamedValue(Target.getRegNamespace(), "NoRegister");
+    }
+    Table << MatchTable::Comment("AddRegisterRegFlags");
 
     // TODO: This is encoded as a 64-bit element, but only 16 or 32-bits are
     // really needed for a physical register reference. We can pack the
@@ -2775,14 +2775,14 @@ protected:
   unsigned TempRegID;
   const CodeGenSubRegIndex *SubRegIdx;
   bool IsDef;
-  bool IsDead; 
+  bool IsDead;
 
 public:
   TempRegRenderer(unsigned InsnID, unsigned TempRegID, bool IsDef = false,
-                  const CodeGenSubRegIndex *SubReg = nullptr, 
-                  bool IsDead = false) 
+                  const CodeGenSubRegIndex *SubReg = nullptr,
+                  bool IsDead = false)
       : OperandRenderer(OR_Register), InsnID(InsnID), TempRegID(TempRegID),
-        SubRegIdx(SubReg), IsDef(IsDef), IsDead(IsDead) {} 
+        SubRegIdx(SubReg), IsDef(IsDef), IsDead(IsDead) {}
 
   static bool classof(const OperandRenderer *R) {
     return R->getKind() == OR_TempRegister;
@@ -2799,13 +2799,13 @@ public:
           << MatchTable::Comment("TempRegID") << MatchTable::IntValue(TempRegID)
           << MatchTable::Comment("TempRegFlags");
 
-    if (IsDef) { 
-      SmallString<32> RegFlags; 
-      RegFlags += "RegState::Define"; 
-      if (IsDead) 
-        RegFlags += "|RegState::Dead"; 
-      Table << MatchTable::NamedValue(RegFlags); 
-    } else 
+    if (IsDef) {
+      SmallString<32> RegFlags;
+      RegFlags += "RegState::Define";
+      if (IsDead)
+        RegFlags += "|RegState::Dead";
+      Table << MatchTable::NamedValue(RegFlags);
+    } else
       Table << MatchTable::IntValue(0);
 
     if (SubRegIdx)
@@ -3518,16 +3518,16 @@ private:
   // Rule coverage information.
   Optional<CodeGenCoverage> RuleCoverage;
 
-  /// Variables used to help with collecting of named operands for predicates 
-  /// with 'let PredicateCodeUsesOperands = 1'. WaitingForNamedOperands is set 
-  /// to the number of named operands that predicate expects. Store locations in 
-  /// StoreIdxForName correspond to the order in which operand names appear in 
-  /// predicate's argument list. 
-  /// When we visit named leaf operand and WaitingForNamedOperands is not zero, 
-  /// add matcher that will record operand and decrease counter. 
-  unsigned WaitingForNamedOperands = 0; 
-  StringMap<unsigned> StoreIdxForName; 
- 
+  /// Variables used to help with collecting of named operands for predicates
+  /// with 'let PredicateCodeUsesOperands = 1'. WaitingForNamedOperands is set
+  /// to the number of named operands that predicate expects. Store locations in
+  /// StoreIdxForName correspond to the order in which operand names appear in
+  /// predicate's argument list.
+  /// When we visit named leaf operand and WaitingForNamedOperands is not zero,
+  /// add matcher that will record operand and decrease counter.
+  unsigned WaitingForNamedOperands = 0;
+  StringMap<unsigned> StoreIdxForName;
+
   void gatherOpcodeValues();
   void gatherTypeIDValues();
   void gatherNodeEquivs();
@@ -3559,11 +3559,11 @@ private:
                             const TreePatternNode *Dst);
 
   Expected<action_iterator>
-  importExplicitDefRenderers(action_iterator InsertPt, RuleMatcher &M, 
-                             BuildMIAction &DstMIBuilder, 
-                             const TreePatternNode *Dst); 
- 
-  Expected<action_iterator> 
+  importExplicitDefRenderers(action_iterator InsertPt, RuleMatcher &M,
+                             BuildMIAction &DstMIBuilder,
+                             const TreePatternNode *Dst);
+
+  Expected<action_iterator>
   importExplicitUseRenderers(action_iterator InsertPt, RuleMatcher &M,
                              BuildMIAction &DstMIBuilder,
                              const llvm::TreePatternNode *Dst);
@@ -3580,8 +3580,8 @@ private:
 
   void emitCxxPredicateFns(raw_ostream &OS, StringRef CodeFieldName,
                            StringRef TypeIdentifier, StringRef ArgType,
-                           StringRef ArgName, StringRef AdditionalArgs, 
-                           StringRef AdditionalDeclarations, 
+                           StringRef ArgName, StringRef AdditionalArgs,
+                           StringRef AdditionalDeclarations,
                            std::function<bool(const Record *R)> Filter);
   void emitImmPredicateFns(raw_ostream &OS, StringRef TypeIdentifier,
                            StringRef ArgType,
@@ -3623,12 +3623,12 @@ private:
   Optional<const CodeGenRegisterClass *>
   inferRegClassFromPattern(TreePatternNode *N);
 
-  // Add builtin predicates. 
-  Expected<InstructionMatcher &> 
-  addBuiltinPredicates(const Record *SrcGIEquivOrNull, 
-                       const TreePredicateFn &Predicate, 
-                       InstructionMatcher &InsnMatcher, bool &HasAddedMatcher); 
- 
+  // Add builtin predicates.
+  Expected<InstructionMatcher &>
+  addBuiltinPredicates(const Record *SrcGIEquivOrNull,
+                       const TreePredicateFn &Predicate,
+                       InstructionMatcher &InsnMatcher, bool &HasAddedMatcher);
+
 public:
   /// Takes a sequence of \p Rules and group them based on the predicates
   /// they share. \p MatcherStorage is used as a memory container
@@ -3736,147 +3736,147 @@ GlobalISelEmitter::importRulePredicates(RuleMatcher &M,
   return Error::success();
 }
 
-Expected<InstructionMatcher &> GlobalISelEmitter::addBuiltinPredicates( 
-    const Record *SrcGIEquivOrNull, const TreePredicateFn &Predicate, 
-    InstructionMatcher &InsnMatcher, bool &HasAddedMatcher) { 
-  if (Predicate.isLoad() || Predicate.isStore() || Predicate.isAtomic()) { 
-    if (const ListInit *AddrSpaces = Predicate.getAddressSpaces()) { 
-      SmallVector<unsigned, 4> ParsedAddrSpaces; 
- 
-      for (Init *Val : AddrSpaces->getValues()) { 
-        IntInit *IntVal = dyn_cast<IntInit>(Val); 
-        if (!IntVal) 
-          return failedImport("Address space is not an integer"); 
-        ParsedAddrSpaces.push_back(IntVal->getValue()); 
-      } 
- 
-      if (!ParsedAddrSpaces.empty()) { 
-        InsnMatcher.addPredicate<MemoryAddressSpacePredicateMatcher>( 
-            0, ParsedAddrSpaces); 
-      } 
-    } 
- 
-    int64_t MinAlign = Predicate.getMinAlignment(); 
-    if (MinAlign > 0) 
-      InsnMatcher.addPredicate<MemoryAlignmentPredicateMatcher>(0, MinAlign); 
-  } 
- 
-  // G_LOAD is used for both non-extending and any-extending loads. 
-  if (Predicate.isLoad() && Predicate.isNonExtLoad()) { 
-    InsnMatcher.addPredicate<MemoryVsLLTSizePredicateMatcher>( 
-        0, MemoryVsLLTSizePredicateMatcher::EqualTo, 0); 
-    return InsnMatcher; 
-  } 
-  if (Predicate.isLoad() && Predicate.isAnyExtLoad()) { 
-    InsnMatcher.addPredicate<MemoryVsLLTSizePredicateMatcher>( 
-        0, MemoryVsLLTSizePredicateMatcher::LessThan, 0); 
-    return InsnMatcher; 
-  } 
- 
-  if (Predicate.isStore()) { 
-    if (Predicate.isTruncStore()) { 
-      // FIXME: If MemoryVT is set, we end up with 2 checks for the MMO size. 
-      InsnMatcher.addPredicate<MemoryVsLLTSizePredicateMatcher>( 
-          0, MemoryVsLLTSizePredicateMatcher::LessThan, 0); 
-      return InsnMatcher; 
-    } 
-    if (Predicate.isNonTruncStore()) { 
-      // We need to check the sizes match here otherwise we could incorrectly 
-      // match truncating stores with non-truncating ones. 
-      InsnMatcher.addPredicate<MemoryVsLLTSizePredicateMatcher>( 
-          0, MemoryVsLLTSizePredicateMatcher::EqualTo, 0); 
-    } 
-  } 
- 
-  // No check required. We already did it by swapping the opcode. 
-  if (!SrcGIEquivOrNull->isValueUnset("IfSignExtend") && 
-      Predicate.isSignExtLoad()) 
-    return InsnMatcher; 
- 
-  // No check required. We already did it by swapping the opcode. 
-  if (!SrcGIEquivOrNull->isValueUnset("IfZeroExtend") && 
-      Predicate.isZeroExtLoad()) 
-    return InsnMatcher; 
- 
-  // No check required. G_STORE by itself is a non-extending store. 
-  if (Predicate.isNonTruncStore()) 
-    return InsnMatcher; 
- 
-  if (Predicate.isLoad() || Predicate.isStore() || Predicate.isAtomic()) { 
-    if (Predicate.getMemoryVT() != nullptr) { 
-      Optional<LLTCodeGen> MemTyOrNone = 
-          MVTToLLT(getValueType(Predicate.getMemoryVT())); 
- 
-      if (!MemTyOrNone) 
-        return failedImport("MemVT could not be converted to LLT"); 
- 
-      // MMO's work in bytes so we must take care of unusual types like i1 
-      // don't round down. 
-      unsigned MemSizeInBits = 
-          llvm::alignTo(MemTyOrNone->get().getSizeInBits(), 8); 
- 
-      InsnMatcher.addPredicate<MemorySizePredicateMatcher>(0, 
-                                                           MemSizeInBits / 8); 
-      return InsnMatcher; 
-    } 
-  } 
- 
-  if (Predicate.isLoad() || Predicate.isStore()) { 
-    // No check required. A G_LOAD/G_STORE is an unindexed load. 
-    if (Predicate.isUnindexed()) 
-      return InsnMatcher; 
-  } 
- 
-  if (Predicate.isAtomic()) { 
-    if (Predicate.isAtomicOrderingMonotonic()) { 
-      InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>("Monotonic"); 
-      return InsnMatcher; 
-    } 
-    if (Predicate.isAtomicOrderingAcquire()) { 
-      InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>("Acquire"); 
-      return InsnMatcher; 
-    } 
-    if (Predicate.isAtomicOrderingRelease()) { 
-      InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>("Release"); 
-      return InsnMatcher; 
-    } 
-    if (Predicate.isAtomicOrderingAcquireRelease()) { 
-      InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>( 
-          "AcquireRelease"); 
-      return InsnMatcher; 
-    } 
-    if (Predicate.isAtomicOrderingSequentiallyConsistent()) { 
-      InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>( 
-          "SequentiallyConsistent"); 
-      return InsnMatcher; 
-    } 
-  } 
- 
-  if (Predicate.isAtomicOrderingAcquireOrStronger()) { 
-    InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>( 
-        "Acquire", AtomicOrderingMMOPredicateMatcher::AO_OrStronger); 
-    return InsnMatcher; 
-  } 
-  if (Predicate.isAtomicOrderingWeakerThanAcquire()) { 
-    InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>( 
-        "Acquire", AtomicOrderingMMOPredicateMatcher::AO_WeakerThan); 
-    return InsnMatcher; 
-  } 
- 
-  if (Predicate.isAtomicOrderingReleaseOrStronger()) { 
-    InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>( 
-        "Release", AtomicOrderingMMOPredicateMatcher::AO_OrStronger); 
-    return InsnMatcher; 
-  } 
-  if (Predicate.isAtomicOrderingWeakerThanRelease()) { 
-    InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>( 
-        "Release", AtomicOrderingMMOPredicateMatcher::AO_WeakerThan); 
-    return InsnMatcher; 
-  } 
-  HasAddedMatcher = false; 
-  return InsnMatcher; 
-} 
- 
+Expected<InstructionMatcher &> GlobalISelEmitter::addBuiltinPredicates(
+    const Record *SrcGIEquivOrNull, const TreePredicateFn &Predicate,
+    InstructionMatcher &InsnMatcher, bool &HasAddedMatcher) {
+  if (Predicate.isLoad() || Predicate.isStore() || Predicate.isAtomic()) {
+    if (const ListInit *AddrSpaces = Predicate.getAddressSpaces()) {
+      SmallVector<unsigned, 4> ParsedAddrSpaces;
+
+      for (Init *Val : AddrSpaces->getValues()) {
+        IntInit *IntVal = dyn_cast<IntInit>(Val);
+        if (!IntVal)
+          return failedImport("Address space is not an integer");
+        ParsedAddrSpaces.push_back(IntVal->getValue());
+      }
+
+      if (!ParsedAddrSpaces.empty()) {
+        InsnMatcher.addPredicate<MemoryAddressSpacePredicateMatcher>(
+            0, ParsedAddrSpaces);
+      }
+    }
+
+    int64_t MinAlign = Predicate.getMinAlignment();
+    if (MinAlign > 0)
+      InsnMatcher.addPredicate<MemoryAlignmentPredicateMatcher>(0, MinAlign);
+  }
+
+  // G_LOAD is used for both non-extending and any-extending loads.
+  if (Predicate.isLoad() && Predicate.isNonExtLoad()) {
+    InsnMatcher.addPredicate<MemoryVsLLTSizePredicateMatcher>(
+        0, MemoryVsLLTSizePredicateMatcher::EqualTo, 0);
+    return InsnMatcher;
+  }
+  if (Predicate.isLoad() && Predicate.isAnyExtLoad()) {
+    InsnMatcher.addPredicate<MemoryVsLLTSizePredicateMatcher>(
+        0, MemoryVsLLTSizePredicateMatcher::LessThan, 0);
+    return InsnMatcher;
+  }
+
+  if (Predicate.isStore()) {
+    if (Predicate.isTruncStore()) {
+      // FIXME: If MemoryVT is set, we end up with 2 checks for the MMO size.
+      InsnMatcher.addPredicate<MemoryVsLLTSizePredicateMatcher>(
+          0, MemoryVsLLTSizePredicateMatcher::LessThan, 0);
+      return InsnMatcher;
+    }
+    if (Predicate.isNonTruncStore()) {
+      // We need to check the sizes match here otherwise we could incorrectly
+      // match truncating stores with non-truncating ones.
+      InsnMatcher.addPredicate<MemoryVsLLTSizePredicateMatcher>(
+          0, MemoryVsLLTSizePredicateMatcher::EqualTo, 0);
+    }
+  }
+
+  // No check required. We already did it by swapping the opcode.
+  if (!SrcGIEquivOrNull->isValueUnset("IfSignExtend") &&
+      Predicate.isSignExtLoad())
+    return InsnMatcher;
+
+  // No check required. We already did it by swapping the opcode.
+  if (!SrcGIEquivOrNull->isValueUnset("IfZeroExtend") &&
+      Predicate.isZeroExtLoad())
+    return InsnMatcher;
+
+  // No check required. G_STORE by itself is a non-extending store.
+  if (Predicate.isNonTruncStore())
+    return InsnMatcher;
+
+  if (Predicate.isLoad() || Predicate.isStore() || Predicate.isAtomic()) {
+    if (Predicate.getMemoryVT() != nullptr) {
+      Optional<LLTCodeGen> MemTyOrNone =
+          MVTToLLT(getValueType(Predicate.getMemoryVT()));
+
+      if (!MemTyOrNone)
+        return failedImport("MemVT could not be converted to LLT");
+
+      // MMO's work in bytes so we must take care of unusual types like i1
+      // don't round down.
+      unsigned MemSizeInBits =
+          llvm::alignTo(MemTyOrNone->get().getSizeInBits(), 8);
+
+      InsnMatcher.addPredicate<MemorySizePredicateMatcher>(0,
+                                                           MemSizeInBits / 8);
+      return InsnMatcher;
+    }
+  }
+
+  if (Predicate.isLoad() || Predicate.isStore()) {
+    // No check required. A G_LOAD/G_STORE is an unindexed load.
+    if (Predicate.isUnindexed())
+      return InsnMatcher;
+  }
+
+  if (Predicate.isAtomic()) {
+    if (Predicate.isAtomicOrderingMonotonic()) {
+      InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>("Monotonic");
+      return InsnMatcher;
+    }
+    if (Predicate.isAtomicOrderingAcquire()) {
+      InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>("Acquire");
+      return InsnMatcher;
+    }
+    if (Predicate.isAtomicOrderingRelease()) {
+      InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>("Release");
+      return InsnMatcher;
+    }
+    if (Predicate.isAtomicOrderingAcquireRelease()) {
+      InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>(
+          "AcquireRelease");
+      return InsnMatcher;
+    }
+    if (Predicate.isAtomicOrderingSequentiallyConsistent()) {
+      InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>(
+          "SequentiallyConsistent");
+      return InsnMatcher;
+    }
+  }
+
+  if (Predicate.isAtomicOrderingAcquireOrStronger()) {
+    InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>(
+        "Acquire", AtomicOrderingMMOPredicateMatcher::AO_OrStronger);
+    return InsnMatcher;
+  }
+  if (Predicate.isAtomicOrderingWeakerThanAcquire()) {
+    InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>(
+        "Acquire", AtomicOrderingMMOPredicateMatcher::AO_WeakerThan);
+    return InsnMatcher;
+  }
+
+  if (Predicate.isAtomicOrderingReleaseOrStronger()) {
+    InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>(
+        "Release", AtomicOrderingMMOPredicateMatcher::AO_OrStronger);
+    return InsnMatcher;
+  }
+  if (Predicate.isAtomicOrderingWeakerThanRelease()) {
+    InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>(
+        "Release", AtomicOrderingMMOPredicateMatcher::AO_WeakerThan);
+    return InsnMatcher;
+  }
+  HasAddedMatcher = false;
+  return InsnMatcher;
+}
+
 Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
     RuleMatcher &Rule, InstructionMatcher &InsnMatcher,
     const TreePatternNode *Src, unsigned &TempOpIdx) {
@@ -3918,7 +3918,7 @@ Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
 
   for (const TreePredicateCall &Call : Src->getPredicateCalls()) {
     const TreePredicateFn &Predicate = Call.Fn;
-    bool HasAddedBuiltinMatcher = true; 
+    bool HasAddedBuiltinMatcher = true;
     if (Predicate.isAlwaysTrue())
       continue;
 
@@ -3927,35 +3927,35 @@ Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
       continue;
     }
 
-    auto InsnMatcherOrError = addBuiltinPredicates( 
-        SrcGIEquivOrNull, Predicate, InsnMatcher, HasAddedBuiltinMatcher); 
-    if (auto Error = InsnMatcherOrError.takeError()) 
-      return std::move(Error); 
-
-    if (Predicate.hasGISelPredicateCode()) { 
-      if (Predicate.usesOperands()) { 
-        assert(WaitingForNamedOperands == 0 && 
-               "previous predicate didn't find all operands or " 
-               "nested predicate that uses operands"); 
-        TreePattern *TP = Predicate.getOrigPatFragRecord(); 
-        WaitingForNamedOperands = TP->getNumArgs(); 
-        for (unsigned i = 0; i < WaitingForNamedOperands; ++i) 
-          StoreIdxForName[getScopedName(Call.Scope, TP->getArgName(i))] = i; 
+    auto InsnMatcherOrError = addBuiltinPredicates(
+        SrcGIEquivOrNull, Predicate, InsnMatcher, HasAddedBuiltinMatcher);
+    if (auto Error = InsnMatcherOrError.takeError())
+      return std::move(Error);
+
+    if (Predicate.hasGISelPredicateCode()) {
+      if (Predicate.usesOperands()) {
+        assert(WaitingForNamedOperands == 0 &&
+               "previous predicate didn't find all operands or "
+               "nested predicate that uses operands");
+        TreePattern *TP = Predicate.getOrigPatFragRecord();
+        WaitingForNamedOperands = TP->getNumArgs();
+        for (unsigned i = 0; i < WaitingForNamedOperands; ++i)
+          StoreIdxForName[getScopedName(Call.Scope, TP->getArgName(i))] = i;
       }
-      InsnMatcher.addPredicate<GenericInstructionPredicateMatcher>(Predicate); 
+      InsnMatcher.addPredicate<GenericInstructionPredicateMatcher>(Predicate);
       continue;
     }
-    if (!HasAddedBuiltinMatcher) { 
-      return failedImport("Src pattern child has predicate (" + 
-                          explainPredicates(Src) + ")"); 
+    if (!HasAddedBuiltinMatcher) {
+      return failedImport("Src pattern child has predicate (" +
+                          explainPredicates(Src) + ")");
     }
-  } 
+  }
 
-  bool IsAtomic = false; 
+  bool IsAtomic = false;
   if (SrcGIEquivOrNull && SrcGIEquivOrNull->getValueAsBit("CheckMMOIsNonAtomic"))
     InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>("NotAtomic");
   else if (SrcGIEquivOrNull && SrcGIEquivOrNull->getValueAsBit("CheckMMOIsAtomic")) {
-    IsAtomic = true; 
+    IsAtomic = true;
     InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>(
       "Unordered", AtomicOrderingMMOPredicateMatcher::AO_OrStronger);
   }
@@ -4009,27 +4009,27 @@ Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
       }
     }
 
-    // Hack around an unfortunate mistake in how atomic store (and really 
-    // atomicrmw in general) operands were ordered. A ISD::STORE used the order 
-    // <stored value>, <pointer> order. ISD::ATOMIC_STORE used the opposite, 
-    // <pointer>, <stored value>. In GlobalISel there's just the one store 
-    // opcode, so we need to swap the operands here to get the right type check. 
-    if (IsAtomic && SrcGIOrNull->TheDef->getName() == "G_STORE") { 
-      assert(NumChildren == 2 && "wrong operands for atomic store"); 
- 
-      TreePatternNode *PtrChild = Src->getChild(0); 
-      TreePatternNode *ValueChild = Src->getChild(1); 
- 
-      if (auto Error = importChildMatcher(Rule, InsnMatcher, PtrChild, true, 
-                                          false, 1, TempOpIdx)) 
-        return std::move(Error); 
- 
-      if (auto Error = importChildMatcher(Rule, InsnMatcher, ValueChild, false, 
-                                          false, 0, TempOpIdx)) 
-        return std::move(Error); 
-      return InsnMatcher; 
-    } 
- 
+    // Hack around an unfortunate mistake in how atomic store (and really
+    // atomicrmw in general) operands were ordered. A ISD::STORE used the order
+    // <stored value>, <pointer> order. ISD::ATOMIC_STORE used the opposite,
+    // <pointer>, <stored value>. In GlobalISel there's just the one store
+    // opcode, so we need to swap the operands here to get the right type check.
+    if (IsAtomic && SrcGIOrNull->TheDef->getName() == "G_STORE") {
+      assert(NumChildren == 2 && "wrong operands for atomic store");
+
+      TreePatternNode *PtrChild = Src->getChild(0);
+      TreePatternNode *ValueChild = Src->getChild(1);
+
+      if (auto Error = importChildMatcher(Rule, InsnMatcher, PtrChild, true,
+                                          false, 1, TempOpIdx))
+        return std::move(Error);
+
+      if (auto Error = importChildMatcher(Rule, InsnMatcher, ValueChild, false,
+                                          false, 0, TempOpIdx))
+        return std::move(Error);
+      return InsnMatcher;
+    }
+
     // Match the used operands (i.e. the children of the operator).
     bool IsIntrinsic =
         SrcGIOrNull->TheDef->getName() == "G_INTRINSIC" ||
@@ -4120,22 +4120,22 @@ Error GlobalISelEmitter::importChildMatcher(
     bool OperandIsImmArg, unsigned OpIdx, unsigned &TempOpIdx) {
 
   Record *PhysReg = nullptr;
-  std::string SrcChildName = std::string(getSrcChildName(SrcChild, PhysReg)); 
-  if (!SrcChild->isLeaf() && 
-      SrcChild->getOperator()->isSubClassOf("ComplexPattern")) { 
-    // The "name" of a non-leaf complex pattern (MY_PAT $op1, $op2) is 
-    // "MY_PAT:op1:op2" and the ones with same "name" represent same operand. 
-    std::string PatternName = std::string(SrcChild->getOperator()->getName()); 
-    for (unsigned i = 0; i < SrcChild->getNumChildren(); ++i) { 
-      PatternName += ":"; 
-      PatternName += SrcChild->getChild(i)->getName(); 
-    } 
-    SrcChildName = PatternName; 
-  } 
+  std::string SrcChildName = std::string(getSrcChildName(SrcChild, PhysReg));
+  if (!SrcChild->isLeaf() &&
+      SrcChild->getOperator()->isSubClassOf("ComplexPattern")) {
+    // The "name" of a non-leaf complex pattern (MY_PAT $op1, $op2) is
+    // "MY_PAT:op1:op2" and the ones with same "name" represent same operand.
+    std::string PatternName = std::string(SrcChild->getOperator()->getName());
+    for (unsigned i = 0; i < SrcChild->getNumChildren(); ++i) {
+      PatternName += ":";
+      PatternName += SrcChild->getChild(i)->getName();
+    }
+    SrcChildName = PatternName;
+  }
 
   OperandMatcher &OM =
-      PhysReg ? InsnMatcher.addPhysRegInput(PhysReg, OpIdx, TempOpIdx) 
-              : InsnMatcher.addOperand(OpIdx, SrcChildName, TempOpIdx); 
+      PhysReg ? InsnMatcher.addPhysRegInput(PhysReg, OpIdx, TempOpIdx)
+              : InsnMatcher.addOperand(OpIdx, SrcChildName, TempOpIdx);
   if (OM.isSameAsAnotherOperand())
     return Error::success();
 
@@ -4182,9 +4182,9 @@ Error GlobalISelEmitter::importChildMatcher(
       for (unsigned i = 0, e = SrcChild->getNumChildren(); i != e; ++i) {
         auto *SubOperand = SrcChild->getChild(i);
         if (!SubOperand->getName().empty()) {
-          if (auto Error = Rule.defineComplexSubOperand( 
-                  SubOperand->getName(), SrcChild->getOperator(), RendererID, i, 
-                  SrcChildName)) 
+          if (auto Error = Rule.defineComplexSubOperand(
+                  SubOperand->getName(), SrcChild->getOperator(), RendererID, i,
+                  SrcChildName))
             return Error;
         }
       }
@@ -4230,13 +4230,13 @@ Error GlobalISelEmitter::importChildMatcher(
   if (auto *ChildDefInit = dyn_cast<DefInit>(SrcChild->getLeafValue())) {
     auto *ChildRec = ChildDefInit->getDef();
 
-    if (WaitingForNamedOperands) { 
-      auto PA = SrcChild->getNamesAsPredicateArg().begin(); 
-      std::string Name = getScopedName(PA->getScope(), PA->getIdentifier()); 
-      OM.addPredicate<RecordNamedOperandMatcher>(StoreIdxForName[Name], Name); 
-      --WaitingForNamedOperands; 
-    } 
- 
+    if (WaitingForNamedOperands) {
+      auto PA = SrcChild->getNamesAsPredicateArg().begin();
+      std::string Name = getScopedName(PA->getScope(), PA->getIdentifier());
+      OM.addPredicate<RecordNamedOperandMatcher>(StoreIdxForName[Name], Name);
+      --WaitingForNamedOperands;
+    }
+
     // Check for register classes.
     if (ChildRec->isSubClassOf("RegisterClass") ||
         ChildRec->isSubClassOf("RegisterOperand")) {
@@ -4279,40 +4279,40 @@ Error GlobalISelEmitter::importChildMatcher(
     if (ChildRec->getName() == "srcvalue")
       return Error::success();
 
-    const bool ImmAllOnesV = ChildRec->getName() == "immAllOnesV"; 
-    if (ImmAllOnesV || ChildRec->getName() == "immAllZerosV") { 
-      auto MaybeInsnOperand = OM.addPredicate<InstructionOperandMatcher>( 
-          InsnMatcher.getRuleMatcher(), SrcChild->getName(), false); 
-      InstructionOperandMatcher &InsnOperand = **MaybeInsnOperand; 
- 
-      ValueTypeByHwMode VTy = ChildTypes.front().getValueTypeByHwMode(); 
- 
-      const CodeGenInstruction &BuildVector 
-        = Target.getInstruction(RK.getDef("G_BUILD_VECTOR")); 
-      const CodeGenInstruction &BuildVectorTrunc 
-        = Target.getInstruction(RK.getDef("G_BUILD_VECTOR_TRUNC")); 
- 
-      // Treat G_BUILD_VECTOR as the canonical opcode, and G_BUILD_VECTOR_TRUNC 
-      // as an alternative. 
-      InsnOperand.getInsnMatcher().addPredicate<InstructionOpcodeMatcher>( 
-      makeArrayRef({&BuildVector, &BuildVectorTrunc})); 
- 
-      // TODO: Handle both G_BUILD_VECTOR and G_BUILD_VECTOR_TRUNC We could 
-      // theoretically not emit any opcode check, but getOpcodeMatcher currently 
-      // has to succeed. 
-      OperandMatcher &OM = 
-          InsnOperand.getInsnMatcher().addOperand(0, "", TempOpIdx); 
-      if (auto Error = 
-              OM.addTypeCheckPredicate(VTy, false /* OperandIsAPointer */)) 
-        return failedImport(toString(std::move(Error)) + 
-                            " for result of Src pattern operator"); 
- 
-      InsnOperand.getInsnMatcher().addPredicate<VectorSplatImmPredicateMatcher>( 
-          ImmAllOnesV ? VectorSplatImmPredicateMatcher::AllOnes 
-                      : VectorSplatImmPredicateMatcher::AllZeros); 
-      return Error::success(); 
-    } 
- 
+    const bool ImmAllOnesV = ChildRec->getName() == "immAllOnesV";
+    if (ImmAllOnesV || ChildRec->getName() == "immAllZerosV") {
+      auto MaybeInsnOperand = OM.addPredicate<InstructionOperandMatcher>(
+          InsnMatcher.getRuleMatcher(), SrcChild->getName(), false);
+      InstructionOperandMatcher &InsnOperand = **MaybeInsnOperand;
+
+      ValueTypeByHwMode VTy = ChildTypes.front().getValueTypeByHwMode();
+
+      const CodeGenInstruction &BuildVector
+        = Target.getInstruction(RK.getDef("G_BUILD_VECTOR"));
+      const CodeGenInstruction &BuildVectorTrunc
+        = Target.getInstruction(RK.getDef("G_BUILD_VECTOR_TRUNC"));
+
+      // Treat G_BUILD_VECTOR as the canonical opcode, and G_BUILD_VECTOR_TRUNC
+      // as an alternative.
+      InsnOperand.getInsnMatcher().addPredicate<InstructionOpcodeMatcher>(
+      makeArrayRef({&BuildVector, &BuildVectorTrunc}));
+
+      // TODO: Handle both G_BUILD_VECTOR and G_BUILD_VECTOR_TRUNC We could
+      // theoretically not emit any opcode check, but getOpcodeMatcher currently
+      // has to succeed.
+      OperandMatcher &OM =
+          InsnOperand.getInsnMatcher().addOperand(0, "", TempOpIdx);
+      if (auto Error =
+              OM.addTypeCheckPredicate(VTy, false /* OperandIsAPointer */))
+        return failedImport(toString(std::move(Error)) +
+                            " for result of Src pattern operator");
+
+      InsnOperand.getInsnMatcher().addPredicate<VectorSplatImmPredicateMatcher>(
+          ImmAllOnesV ? VectorSplatImmPredicateMatcher::AllOnes
+                      : VectorSplatImmPredicateMatcher::AllZeros);
+      return Error::success();
+    }
+
     return failedImport(
         "Src pattern child def is an unsupported tablegen class");
   }
@@ -4424,7 +4424,7 @@ Expected<action_iterator> GlobalISelEmitter::importExplicitUseRenderer(
       return failedImport("Dst operand has an unsupported type");
 
     if (ChildRec->isSubClassOf("Register")) {
-      DstMIBuilder.addRenderer<AddRegisterRenderer>(Target, ChildRec); 
+      DstMIBuilder.addRenderer<AddRegisterRenderer>(Target, ChildRec);
       return InsertPt;
     }
 
@@ -4484,15 +4484,15 @@ Expected<BuildMIAction &> GlobalISelEmitter::createAndImportInstructionRenderer(
         &Target.getInstruction(RK.getDef("COPY")));
     BuildMIAction &CopyToPhysRegMIBuilder =
         *static_cast<BuildMIAction *>(InsertPt->get());
-    CopyToPhysRegMIBuilder.addRenderer<AddRegisterRenderer>(Target, 
-                                                            PhysInput.first, 
+    CopyToPhysRegMIBuilder.addRenderer<AddRegisterRenderer>(Target,
+                                                            PhysInput.first,
                                                             true);
     CopyToPhysRegMIBuilder.addRenderer<CopyPhysRegRenderer>(PhysInput.first);
   }
 
-  if (auto Error = importExplicitDefRenderers(InsertPt, M, DstMIBuilder, Dst) 
-                       .takeError()) 
-    return std::move(Error); 
+  if (auto Error = importExplicitDefRenderers(InsertPt, M, DstMIBuilder, Dst)
+                       .takeError())
+    return std::move(Error);
 
   if (auto Error = importExplicitUseRenderers(InsertPt, M, DstMIBuilder, Dst)
                        .takeError())
@@ -4644,39 +4644,39 @@ Expected<action_iterator> GlobalISelEmitter::createInstructionRenderer(
                                        DstI);
 }
 
-Expected<action_iterator> GlobalISelEmitter::importExplicitDefRenderers( 
-    action_iterator InsertPt, RuleMatcher &M, BuildMIAction &DstMIBuilder, 
-    const TreePatternNode *Dst) { 
+Expected<action_iterator> GlobalISelEmitter::importExplicitDefRenderers(
+    action_iterator InsertPt, RuleMatcher &M, BuildMIAction &DstMIBuilder,
+    const TreePatternNode *Dst) {
   const CodeGenInstruction *DstI = DstMIBuilder.getCGI();
-  const unsigned NumDefs = DstI->Operands.NumDefs; 
-  if (NumDefs == 0) 
-    return InsertPt; 
- 
-  DstMIBuilder.addRenderer<CopyRenderer>(DstI->Operands[0].Name); 
- 
-  // Some instructions have multiple defs, but are missing a type entry 
-  // (e.g. s_cc_out operands). 
-  if (Dst->getExtTypes().size() < NumDefs) 
-    return failedImport("unhandled discarded def"); 
- 
-  // Patterns only handle a single result, so any result after the first is an 
-  // implicitly dead def. 
-  for (unsigned I = 1; I < NumDefs; ++I) { 
-    const TypeSetByHwMode &ExtTy = Dst->getExtType(I); 
-    if (!ExtTy.isMachineValueType()) 
-      return failedImport("unsupported typeset"); 
- 
-    auto OpTy = MVTToLLT(ExtTy.getMachineValueType().SimpleTy); 
-    if (!OpTy) 
-      return failedImport("unsupported type"); 
- 
-    unsigned TempRegID = M.allocateTempRegID(); 
-    InsertPt = 
-      M.insertAction<MakeTempRegisterAction>(InsertPt, *OpTy, TempRegID); 
-    DstMIBuilder.addRenderer<TempRegRenderer>(TempRegID, true, nullptr, true); 
-  }
- 
-  return InsertPt; 
+  const unsigned NumDefs = DstI->Operands.NumDefs;
+  if (NumDefs == 0)
+    return InsertPt;
+
+  DstMIBuilder.addRenderer<CopyRenderer>(DstI->Operands[0].Name);
+
+  // Some instructions have multiple defs, but are missing a type entry
+  // (e.g. s_cc_out operands).
+  if (Dst->getExtTypes().size() < NumDefs)
+    return failedImport("unhandled discarded def");
+
+  // Patterns only handle a single result, so any result after the first is an
+  // implicitly dead def.
+  for (unsigned I = 1; I < NumDefs; ++I) {
+    const TypeSetByHwMode &ExtTy = Dst->getExtType(I);
+    if (!ExtTy.isMachineValueType())
+      return failedImport("unsupported typeset");
+
+    auto OpTy = MVTToLLT(ExtTy.getMachineValueType().SimpleTy);
+    if (!OpTy)
+      return failedImport("unsupported type");
+
+    unsigned TempRegID = M.allocateTempRegID();
+    InsertPt =
+      M.insertAction<MakeTempRegisterAction>(InsertPt, *OpTy, TempRegID);
+    DstMIBuilder.addRenderer<TempRegRenderer>(TempRegID, true, nullptr, true);
+  }
+
+  return InsertPt;
 }
 
 Expected<action_iterator> GlobalISelEmitter::importExplicitUseRenderers(
@@ -4690,8 +4690,8 @@ Expected<action_iterator> GlobalISelEmitter::importExplicitUseRenderers(
 
   // EXTRACT_SUBREG needs to use a subregister COPY.
   if (Name == "EXTRACT_SUBREG") {
-    if (!Dst->getChild(1)->isLeaf()) 
-      return failedImport("EXTRACT_SUBREG child #1 is not a leaf"); 
+    if (!Dst->getChild(1)->isLeaf())
+      return failedImport("EXTRACT_SUBREG child #1 is not a leaf");
     DefInit *SubRegInit = dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue());
     if (!SubRegInit)
       return failedImport("EXTRACT_SUBREG child #1 is not a subreg index");
@@ -4878,7 +4878,7 @@ Error GlobalISelEmitter::importDefaultOperandRenderers(
         IDMIBuilder.addRenderer<TempRegRenderer>(TempRegID);
         DstMIBuilder.addRenderer<TempRegRenderer>(TempRegID);
       } else {
-        DstMIBuilder.addRenderer<AddRegisterRenderer>(Target, Def); 
+        DstMIBuilder.addRenderer<AddRegisterRenderer>(Target, Def);
       }
       continue;
     }
@@ -4953,17 +4953,17 @@ GlobalISelEmitter::inferRegClassFromPattern(TreePatternNode *N) {
       return None;
     return getRegClassFromLeaf(RCChild);
   }
-  if (InstName == "INSERT_SUBREG") { 
-    TreePatternNode *Child0 = N->getChild(0); 
-    assert(Child0->getNumTypes() == 1 && "Unexpected number of types!"); 
-    const TypeSetByHwMode &VTy = Child0->getExtType(0); 
-    return inferSuperRegisterClassForNode(VTy, Child0, N->getChild(2)); 
-  } 
-  if (InstName == "EXTRACT_SUBREG") { 
-    assert(N->getNumTypes() == 1 && "Unexpected number of types!"); 
-    const TypeSetByHwMode &VTy = N->getExtType(0); 
-    return inferSuperRegisterClass(VTy, N->getChild(1)); 
-  } 
+  if (InstName == "INSERT_SUBREG") {
+    TreePatternNode *Child0 = N->getChild(0);
+    assert(Child0->getNumTypes() == 1 && "Unexpected number of types!");
+    const TypeSetByHwMode &VTy = Child0->getExtType(0);
+    return inferSuperRegisterClassForNode(VTy, Child0, N->getChild(2));
+  }
+  if (InstName == "EXTRACT_SUBREG") {
+    assert(N->getNumTypes() == 1 && "Unexpected number of types!");
+    const TypeSetByHwMode &VTy = N->getExtType(0);
+    return inferSuperRegisterClass(VTy, N->getChild(1));
+  }
 
   // Handle destination record types that we can safely infer a register class
   // from.
@@ -5000,8 +5000,8 @@ GlobalISelEmitter::inferSuperRegisterClass(const TypeSetByHwMode &Ty,
   // Use the information we found above to find a minimal register class which
   // supports the subregister and type we want.
   auto RC =
-      Target.getSuperRegForSubReg(Ty.getValueTypeByHwMode(), CGRegs, SubIdx, 
-                                  /* MustBeAllocatable */ true); 
+      Target.getSuperRegForSubReg(Ty.getValueTypeByHwMode(), CGRegs, SubIdx,
+                                  /* MustBeAllocatable */ true);
   if (!RC)
     return None;
   return *RC;
@@ -5089,8 +5089,8 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
 
   if (Dst->isLeaf()) {
     Record *RCDef = getInitValueAsRegClass(Dst->getLeafValue());
-    if (RCDef) { 
-      const CodeGenRegisterClass &RC = Target.getRegisterClass(RCDef); 
+    if (RCDef) {
+      const CodeGenRegisterClass &RC = Target.getRegisterClass(RCDef);
 
       // We need to replace the def and all its uses with the specified
       // operand. However, we must also insert COPY's wherever needed.
@@ -5126,8 +5126,8 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
   auto &DstI = Target.getInstruction(DstOp);
   StringRef DstIName = DstI.TheDef->getName();
 
-  if (DstI.Operands.NumDefs < Src->getExtTypes().size()) 
-    return failedImport("Src pattern result has more defs than dst MI (" + 
+  if (DstI.Operands.NumDefs < Src->getExtTypes().size())
+    return failedImport("Src pattern result has more defs than dst MI (" +
                         to_string(Src->getExtTypes().size()) + " def(s) vs " +
                         to_string(DstI.Operands.NumDefs) + " def(s))");
 
@@ -5347,8 +5347,8 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
 // trouble than it's worth.
 void GlobalISelEmitter::emitCxxPredicateFns(
     raw_ostream &OS, StringRef CodeFieldName, StringRef TypeIdentifier,
-    StringRef ArgType, StringRef ArgName, StringRef AdditionalArgs, 
-    StringRef AdditionalDeclarations, 
+    StringRef ArgType, StringRef ArgName, StringRef AdditionalArgs,
+    StringRef AdditionalDeclarations,
     std::function<bool(const Record *R)> Filter) {
   std::vector<const Record *> MatchedRecords;
   const auto &Defs = RK.getAllDerivedDefinitions("PatFrag");
@@ -5373,7 +5373,7 @@ void GlobalISelEmitter::emitCxxPredicateFns(
 
   OS << "bool " << Target.getName() << "InstructionSelector::test" << ArgName
      << "Predicate_" << TypeIdentifier << "(unsigned PredicateID, " << ArgType << " "
-     << ArgName << AdditionalArgs <<") const {\n" 
+     << ArgName << AdditionalArgs <<") const {\n"
      << AdditionalDeclarations;
   if (!AdditionalDeclarations.empty())
     OS << "\n";
@@ -5399,13 +5399,13 @@ void GlobalISelEmitter::emitImmPredicateFns(
     raw_ostream &OS, StringRef TypeIdentifier, StringRef ArgType,
     std::function<bool(const Record *R)> Filter) {
   return emitCxxPredicateFns(OS, "ImmediateCode", TypeIdentifier, ArgType,
-                             "Imm", "", "", Filter); 
+                             "Imm", "", "", Filter);
 }
 
 void GlobalISelEmitter::emitMIPredicateFns(raw_ostream &OS) {
   return emitCxxPredicateFns(
       OS, "GISelPredicateCode", "MI", "const MachineInstr &", "MI",
-      ", const std::array<const MachineOperand *, 3> &Operands", 
+      ", const std::array<const MachineOperand *, 3> &Operands",
       "  const MachineFunction &MF = *MI.getParent()->getParent();\n"
       "  const MachineRegisterInfo &MRI = MF.getRegInfo();\n"
       "  (void)MRI;",
@@ -5431,7 +5431,7 @@ std::vector<Matcher *> GlobalISelEmitter::optimizeRules(
     // added rules out of it and make sure to re-create the group to properly
     // re-initialize it:
     if (CurrentGroup->size() < 2)
-      append_range(OptRules, CurrentGroup->matchers()); 
+      append_range(OptRules, CurrentGroup->matchers());
     else {
       CurrentGroup->finalize();
       OptRules.push_back(CurrentGroup.get());
@@ -5480,13 +5480,13 @@ GlobalISelEmitter::buildMatchTable(MutableArrayRef<RuleMatcher> Rules,
       OpcodeOrder[Opcode] = CurrentOrdering++;
   }
 
-  llvm::stable_sort(InputRules, [&OpcodeOrder](const Matcher *A, 
-                                               const Matcher *B) { 
-    auto *L = static_cast<const RuleMatcher *>(A); 
-    auto *R = static_cast<const RuleMatcher *>(B); 
-    return std::make_tuple(OpcodeOrder[L->getOpcode()], L->getNumOperands()) < 
-           std::make_tuple(OpcodeOrder[R->getOpcode()], R->getNumOperands()); 
-  }); 
+  llvm::stable_sort(InputRules, [&OpcodeOrder](const Matcher *A,
+                                               const Matcher *B) {
+    auto *L = static_cast<const RuleMatcher *>(A);
+    auto *R = static_cast<const RuleMatcher *>(B);
+    return std::make_tuple(OpcodeOrder[L->getOpcode()], L->getNumOperands()) <
+           std::make_tuple(OpcodeOrder[R->getOpcode()], R->getNumOperands());
+  });
 
   for (Matcher *Rule : InputRules)
     Rule->optimize();
@@ -5619,7 +5619,7 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
 
      << "  typedef void(" << Target.getName()
      << "InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const "
-        "MachineInstr &, int) " 
+        "MachineInstr &, int) "
         "const;\n"
      << "  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, "
         "CustomRendererFn> "
@@ -5635,8 +5635,8 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
      << "  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat "
         "&Imm) const override;\n"
      << "  const int64_t *getMatchTable() const override;\n"
-     << "  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI" 
-        ", const std::array<const MachineOperand *, 3> &Operands) " 
+     << "  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI"
+        ", const std::array<const MachineOperand *, 3> &Operands) "
         "const override;\n"
      << "#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL\n\n";
 
@@ -5672,7 +5672,7 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
   OS << "void " << Target.getName() << "InstructionSelector"
     "::setupGeneratedPerFunctionState(MachineFunction &MF) {\n"
     "  AvailableFunctionFeatures = computeAvailableFunctionFeatures("
-    "(const " << Target.getName() << "Subtarget *)&MF.getSubtarget(), &MF);\n" 
+    "(const " << Target.getName() << "Subtarget *)&MF.getSubtarget(), &MF);\n"
     "}\n";
 
   if (Target.getName() == "X86" || Target.getName() == "AArch64") {
@@ -5690,7 +5690,7 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
   // Emit a table containing the LLT objects needed by the matcher and an enum
   // for the matcher to reference them with.
   std::vector<LLTCodeGen> TypeObjects;
-  append_range(TypeObjects, KnownTypes); 
+  append_range(TypeObjects, KnownTypes);
   llvm::sort(TypeObjects);
   OS << "// LLT Objects.\n"
      << "enum {\n";
@@ -5792,7 +5792,7 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
      << "enum {\n"
      << "  GICR_Invalid,\n";
   for (const auto &Record : CustomRendererFns)
-    OS << "  GICR_" << Record->getValueAsString("RendererFn") << ",\n"; 
+    OS << "  GICR_" << Record->getValueAsString("RendererFn") << ",\n";
   OS << "};\n";
 
   OS << Target.getName() << "InstructionSelector::CustomRendererFn\n"
@@ -6085,10 +6085,10 @@ void SwitchMatcher::finalize() {
   if (empty())
     return;
 
-  llvm::stable_sort(Matchers, [](const Matcher *L, const Matcher *R) { 
-    return L->getFirstCondition().getValue() < 
-           R->getFirstCondition().getValue(); 
-  }); 
+  llvm::stable_sort(Matchers, [](const Matcher *L, const Matcher *R) {
+    return L->getFirstCondition().getValue() <
+           R->getFirstCondition().getValue();
+  });
   Condition = Matchers[0]->popFirstCondition();
   for (unsigned I = 1, E = Values.size(); I < E; ++I)
     Matchers[I]->popFirstCondition();
diff --git a/contrib/libs/llvm12/utils/TableGen/InstrInfoEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/InstrInfoEmitter.cpp
index 8199a9839f..9ff385faec 100644
--- a/contrib/libs/llvm12/utils/TableGen/InstrInfoEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/InstrInfoEmitter.cpp
@@ -182,10 +182,10 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
       if (Constraint.isNone())
         Res += "0";
       else if (Constraint.isEarlyClobber())
-        Res += "MCOI_EARLY_CLOBBER"; 
+        Res += "MCOI_EARLY_CLOBBER";
       else {
         assert(Constraint.isTied());
-        Res += "MCOI_TIED_TO(" + utostr(Constraint.getTiedOperand()) + ")"; 
+        Res += "MCOI_TIED_TO(" + utostr(Constraint.getTiedOperand()) + ")";
       }
 
       Result.push_back(Res);
@@ -279,7 +279,7 @@ void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS,
   for (const auto &Op : Operands)
     OS << "  " << Op.first << " = " << Op.second << ",\n";
 
-  OS << "  OPERAND_LAST"; 
+  OS << "  OPERAND_LAST";
   OS << "\n};\n";
   OS << "} // end namespace OpName\n";
   OS << "} // end namespace " << Namespace << "\n";
@@ -315,7 +315,7 @@ void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS,
 
       OS << "    return OperandMap[" << TableIndex++ << "][NamedIdx];\n";
     }
-    OS << "  default: return -1;\n"; 
+    OS << "  default: return -1;\n";
     OS << "  }\n";
   } else {
     // There are no operands, so no need to emit anything
@@ -370,7 +370,7 @@ void InstrInfoEmitter::emitOperandTypeMappings(
   OS << "namespace " << Namespace << " {\n";
   OS << "LLVM_READONLY\n";
   OS << "static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {\n";
-  // TODO: Factor out duplicate operand lists to compress the tables. 
+  // TODO: Factor out duplicate operand lists to compress the tables.
   if (!NumberedInstructions.empty()) {
     std::vector<int> OperandOffsets;
     std::vector<Record *> OperandRecords;
@@ -384,7 +384,7 @@ void InstrInfoEmitter::emitOperandTypeMappings(
           OperandRecords.push_back(Op.Rec);
           ++CurrentOffset;
         } else {
-          for (Init *Arg : MIOI->getArgs()) { 
+          for (Init *Arg : MIOI->getArgs()) {
             OperandRecords.push_back(cast<DefInit>(Arg)->getDef());
             ++CurrentOffset;
           }
@@ -392,26 +392,26 @@ void InstrInfoEmitter::emitOperandTypeMappings(
       }
     }
 
-    // Emit the table of offsets (indexes) into the operand type table. 
-    // Size the unsigned integer offset to save space. 
-    assert(OperandRecords.size() <= UINT32_MAX && 
-           "Too many operands for offset table"); 
-    OS << ((OperandRecords.size() <= UINT16_MAX) ? "  const uint16_t" 
-                                                 : "  const uint32_t"); 
-    OS << " Offsets[] = {\n"; 
+    // Emit the table of offsets (indexes) into the operand type table.
+    // Size the unsigned integer offset to save space.
+    assert(OperandRecords.size() <= UINT32_MAX &&
+           "Too many operands for offset table");
+    OS << ((OperandRecords.size() <= UINT16_MAX) ? "  const uint16_t"
+                                                 : "  const uint32_t");
+    OS << " Offsets[] = {\n";
     for (int I = 0, E = OperandOffsets.size(); I != E; ++I)
       OS << "    " << OperandOffsets[I] << ",\n";
     OS << "  };\n";
 
     // Add an entry for the end so that we don't need to special case it below.
     OperandOffsets.push_back(OperandRecords.size());
- 
+
     // Emit the actual operand types in a flat table.
-    // Size the signed integer operand type to save space. 
-    assert(EnumVal <= INT16_MAX && 
-           "Too many operand types for operand types table"); 
-    OS << ((EnumVal <= INT8_MAX) ? "  const int8_t" : "  const int16_t"); 
-    OS << " OpcodeOperandTypes[] = {\n    "; 
+    // Size the signed integer operand type to save space.
+    assert(EnumVal <= INT16_MAX &&
+           "Too many operand types for operand types table");
+    OS << ((EnumVal <= INT8_MAX) ? "  const int8_t" : "  const int16_t");
+    OS << " OpcodeOperandTypes[] = {\n    ";
     for (int I = 0, E = OperandRecords.size(), CurOffset = 1; I != E; ++I) {
       // We print each Opcode's operands in its own row.
       if (I == OperandOffsets[CurOffset]) {
@@ -541,7 +541,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
   unsigned ListNumber = 0;
 
   // Emit all of the instruction's implicit uses and defs.
-  Records.startTimer("Emit uses/defs"); 
+  Records.startTimer("Emit uses/defs");
   for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
     Record *Inst = II->TheDef;
     std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
@@ -559,12 +559,12 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
   OperandInfoMapTy OperandInfoIDs;
 
   // Emit all of the operand info records.
-  Records.startTimer("Emit operand info"); 
+  Records.startTimer("Emit operand info");
   EmitOperandInfo(OS, OperandInfoIDs);
 
   // Emit all of the MCInstrDesc records in their ENUM ordering.
   //
-  Records.startTimer("Emit InstrDesc records"); 
+  Records.startTimer("Emit InstrDesc records");
   OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
   ArrayRef<const CodeGenInstruction*> NumberedInstructions =
     Target.getInstructionsByEnumValue();
@@ -580,7 +580,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
   OS << "};\n\n";
 
   // Emit the array of instruction names.
-  Records.startTimer("Emit instruction names"); 
+  Records.startTimer("Emit instruction names");
   InstrNames.layout();
   InstrNames.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName +
                                           "InstrNameData[]");
@@ -641,7 +641,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
   }
 
   // MCInstrInfo initialization routine.
-  Records.startTimer("Emit initialization routine"); 
+  Records.startTimer("Emit initialization routine");
   OS << "static inline void Init" << TargetName
      << "MCInstrInfo(MCInstrInfo *II) {\n";
   OS << "  II->InitMCInstrInfo(" << TargetName << "Insts, " << TargetName
@@ -720,13 +720,13 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
 
   OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n";
 
-  Records.startTimer("Emit operand name mappings"); 
+  Records.startTimer("Emit operand name mappings");
   emitOperandNameMappings(OS, Target, NumberedInstructions);
 
-  Records.startTimer("Emit operand type mappings"); 
+  Records.startTimer("Emit operand type mappings");
   emitOperandTypeMappings(OS, Target, NumberedInstructions);
 
-  Records.startTimer("Emit helper methods"); 
+  Records.startTimer("Emit helper methods");
   emitMCIIHelperMethods(OS, TargetName);
 }
 
@@ -879,9 +879,9 @@ void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
 namespace llvm {
 
 void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
-  RK.startTimer("Analyze DAG patterns"); 
+  RK.startTimer("Analyze DAG patterns");
   InstrInfoEmitter(RK).run(OS);
-  RK.startTimer("Emit map table"); 
+  RK.startTimer("Emit map table");
   EmitMapTable(RK, OS);
 }
 
diff --git a/contrib/libs/llvm12/utils/TableGen/IntrinsicEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/IntrinsicEmitter.cpp
index 5b199c55a3..978d24c830 100644
--- a/contrib/libs/llvm12/utils/TableGen/IntrinsicEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/IntrinsicEmitter.cpp
@@ -246,16 +246,16 @@ enum IIT_Info {
   IIT_SUBDIVIDE4_ARG = 45,
   IIT_VEC_OF_BITCASTS_TO_INT = 46,
   IIT_V128 = 47,
-  IIT_BF16 = 48, 
-  IIT_STRUCT9 = 49, 
-  IIT_V256 = 50, 
-  IIT_AMX  = 51 
+  IIT_BF16 = 48,
+  IIT_STRUCT9 = 49,
+  IIT_V256 = 50,
+  IIT_AMX  = 51
 };
 
 static void EncodeFixedValueType(MVT::SimpleValueType VT,
                                  std::vector<unsigned char> &Sig) {
   if (MVT(VT).isInteger()) {
-    unsigned BitWidth = MVT(VT).getFixedSizeInBits(); 
+    unsigned BitWidth = MVT(VT).getFixedSizeInBits();
     switch (BitWidth) {
     default: PrintFatalError("unhandled integer type width in intrinsic!");
     case 1: return Sig.push_back(IIT_I1);
@@ -277,7 +277,7 @@ static void EncodeFixedValueType(MVT::SimpleValueType VT,
   case MVT::token: return Sig.push_back(IIT_TOKEN);
   case MVT::Metadata: return Sig.push_back(IIT_METADATA);
   case MVT::x86mmx: return Sig.push_back(IIT_MMX);
-  case MVT::x86amx: return Sig.push_back(IIT_AMX); 
+  case MVT::x86amx: return Sig.push_back(IIT_AMX);
   // MVT::OtherVT is used to mean the empty struct type here.
   case MVT::Other: return Sig.push_back(IIT_EMPTYSTRUCT);
   // MVT::isVoid is used to represent varargs here.
@@ -388,7 +388,7 @@ static void EncodeFixedType(Record *R, std::vector<unsigned char> &ArgCodes,
     case 32: Sig.push_back(IIT_V32); break;
     case 64: Sig.push_back(IIT_V64); break;
     case 128: Sig.push_back(IIT_V128); break;
-    case 256: Sig.push_back(IIT_V256); break; 
+    case 256: Sig.push_back(IIT_V256); break;
     case 512: Sig.push_back(IIT_V512); break;
     case 1024: Sig.push_back(IIT_V1024); break;
     }
@@ -474,7 +474,7 @@ static void ComputeFixedEncoding(const CodeGenIntrinsic &Int,
       case 6: TypeSig.push_back(IIT_STRUCT6); break;
       case 7: TypeSig.push_back(IIT_STRUCT7); break;
       case 8: TypeSig.push_back(IIT_STRUCT8); break;
-      case 9: TypeSig.push_back(IIT_STRUCT9); break; 
+      case 9: TypeSig.push_back(IIT_STRUCT9); break;
       default: llvm_unreachable("Unhandled case in struct");
     }
 
@@ -639,12 +639,12 @@ void IntrinsicEmitter::EmitAttributes(const CodeGenIntrinsicTable &Ints,
     unsigned &N = UniqAttributes[&intrinsic];
     if (N) continue;
     N = ++AttrNum;
-    assert(N < 65536 && "Too many unique attributes for table!"); 
+    assert(N < 65536 && "Too many unique attributes for table!");
   }
 
   // Emit an array of AttributeList.  Most intrinsics will have at least one
   // entry, for the function itself (index ~1), which is usually nounwind.
-  OS << "  static const uint16_t IntrinsicsToAttributesMap[] = {\n"; 
+  OS << "  static const uint16_t IntrinsicsToAttributesMap[] = {\n";
 
   for (unsigned i = 0, e = Ints.size(); i != e; ++i) {
     const CodeGenIntrinsic &intrinsic = Ints[i];
@@ -693,12 +693,12 @@ void IntrinsicEmitter::EmitAttributes(const CodeGenIntrinsicTable &Ints,
             OS << "Attribute::NoAlias";
             addComma = true;
             break;
-          case CodeGenIntrinsic::NoUndef: 
-            if (addComma) 
-              OS << ","; 
-            OS << "Attribute::NoUndef"; 
-            addComma = true; 
-            break; 
+          case CodeGenIntrinsic::NoUndef:
+            if (addComma)
+              OS << ",";
+            OS << "Attribute::NoUndef";
+            addComma = true;
+            break;
           case CodeGenIntrinsic::Returned:
             if (addComma)
               OS << ",";
diff --git a/contrib/libs/llvm12/utils/TableGen/OptParserEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/OptParserEmitter.cpp
index 292ee49a8a..8e6c05885e 100644
--- a/contrib/libs/llvm12/utils/TableGen/OptParserEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/OptParserEmitter.cpp
@@ -20,7 +20,7 @@
 
 using namespace llvm;
 
-static std::string getOptionName(const Record &R) { 
+static std::string getOptionName(const Record &R) {
   // Use the record name unless EnumName is defined.
   if (isa<UnsetInit>(R.getValueInit("EnumName")))
     return std::string(R.getName());
@@ -35,20 +35,20 @@ static raw_ostream &write_cstring(raw_ostream &OS, llvm::StringRef Str) {
   return OS;
 }
 
-static std::string getOptionSpelling(const Record &R, size_t &PrefixLength) { 
+static std::string getOptionSpelling(const Record &R, size_t &PrefixLength) {
   std::vector<StringRef> Prefixes = R.getValueAsListOfStrings("Prefixes");
   StringRef Name = R.getValueAsString("Name");
- 
+
   if (Prefixes.empty()) {
     PrefixLength = 0;
     return Name.str();
   }
- 
+
   PrefixLength = Prefixes[0].size();
   return (Twine(Prefixes[0]) + Twine(Name)).str();
 }
 
-static std::string getOptionSpelling(const Record &R) { 
+static std::string getOptionSpelling(const Record &R) {
   size_t PrefixLength;
   return getOptionSpelling(R, PrefixLength);
 }
@@ -60,29 +60,29 @@ static void emitNameUsingSpelling(raw_ostream &OS, const Record &R) {
   OS << "[" << PrefixLength << "]";
 }
 
-class MarshallingInfo { 
+class MarshallingInfo {
 public:
-  static constexpr const char *MacroName = "OPTION_WITH_MARSHALLING"; 
+  static constexpr const char *MacroName = "OPTION_WITH_MARSHALLING";
   const Record &R;
   bool ShouldAlwaysEmit;
-  StringRef MacroPrefix; 
+  StringRef MacroPrefix;
   StringRef KeyPath;
   StringRef DefaultValue;
   StringRef NormalizedValuesScope;
-  StringRef ImpliedCheck; 
-  StringRef ImpliedValue; 
-  StringRef ShouldParse; 
+  StringRef ImpliedCheck;
+  StringRef ImpliedValue;
+  StringRef ShouldParse;
   StringRef Normalizer;
   StringRef Denormalizer;
-  StringRef ValueMerger; 
-  StringRef ValueExtractor; 
+  StringRef ValueMerger;
+  StringRef ValueExtractor;
   int TableIndex = -1;
   std::vector<StringRef> Values;
   std::vector<StringRef> NormalizedValues;
   std::string ValueTableName;
 
-  static size_t NextTableIndex; 
- 
+  static size_t NextTableIndex;
+
   static constexpr const char *ValueTablePreamble = R"(
 struct SimpleEnumValue {
   const char *Name;
@@ -98,39 +98,39 @@ struct SimpleEnumValueTable {
   static constexpr const char *ValueTablesDecl =
       "static const SimpleEnumValueTable SimpleEnumValueTables[] = ";
 
-  MarshallingInfo(const Record &R) : R(R) {} 
- 
-  std::string getMacroName() const { 
-    return (MacroPrefix + MarshallingInfo::MacroName).str(); 
-  } 
- 
-  void emit(raw_ostream &OS) const { 
-    write_cstring(OS, StringRef(getOptionSpelling(R))); 
+  MarshallingInfo(const Record &R) : R(R) {}
+
+  std::string getMacroName() const {
+    return (MacroPrefix + MarshallingInfo::MacroName).str();
+  }
+
+  void emit(raw_ostream &OS) const {
+    write_cstring(OS, StringRef(getOptionSpelling(R)));
+    OS << ", ";
+    OS << ShouldParse;
+    OS << ", ";
+    OS << ShouldAlwaysEmit;
+    OS << ", ";
+    OS << KeyPath;
+    OS << ", ";
+    emitScopedNormalizedValue(OS, DefaultValue);
+    OS << ", ";
+    OS << ImpliedCheck;
+    OS << ", ";
+    emitScopedNormalizedValue(OS, ImpliedValue);
     OS << ", ";
-    OS << ShouldParse; 
-    OS << ", "; 
-    OS << ShouldAlwaysEmit; 
-    OS << ", "; 
-    OS << KeyPath; 
-    OS << ", "; 
-    emitScopedNormalizedValue(OS, DefaultValue); 
-    OS << ", "; 
-    OS << ImpliedCheck; 
-    OS << ", "; 
-    emitScopedNormalizedValue(OS, ImpliedValue); 
-    OS << ", "; 
     OS << Normalizer;
     OS << ", ";
     OS << Denormalizer;
     OS << ", ";
-    OS << ValueMerger; 
-    OS << ", "; 
-    OS << ValueExtractor; 
-    OS << ", "; 
+    OS << ValueMerger;
+    OS << ", ";
+    OS << ValueExtractor;
+    OS << ", ";
     OS << TableIndex;
   }
 
-  Optional<StringRef> emitValueTable(raw_ostream &OS) const { 
+  Optional<StringRef> emitValueTable(raw_ostream &OS) const {
     if (TableIndex == -1)
       return {};
     OS << "static const SimpleEnumValue " << ValueTableName << "[] = {\n";
@@ -146,64 +146,64 @@ struct SimpleEnumValueTable {
     return StringRef(ValueTableName);
   }
 
-private: 
-  void emitScopedNormalizedValue(raw_ostream &OS, 
-                                 StringRef NormalizedValue) const { 
-    if (!NormalizedValuesScope.empty()) 
-      OS << NormalizedValuesScope << "::"; 
-    OS << NormalizedValue; 
-  } 
-}; 
-
-size_t MarshallingInfo::NextTableIndex = 0; 
-
-static MarshallingInfo createMarshallingInfo(const Record &R) { 
-  assert(!isa<UnsetInit>(R.getValueInit("KeyPath")) && 
-         !isa<UnsetInit>(R.getValueInit("DefaultValue")) && 
-         !isa<UnsetInit>(R.getValueInit("ValueMerger")) && 
-         "MarshallingInfo must have a provide a keypath, default value and a " 
-         "value merger"); 
-
-  MarshallingInfo Ret(R); 
-
-  Ret.ShouldAlwaysEmit = R.getValueAsBit("ShouldAlwaysEmit"); 
-  Ret.MacroPrefix = R.getValueAsString("MacroPrefix"); 
-  Ret.KeyPath = R.getValueAsString("KeyPath"); 
-  Ret.DefaultValue = R.getValueAsString("DefaultValue"); 
-  Ret.NormalizedValuesScope = R.getValueAsString("NormalizedValuesScope"); 
-  Ret.ImpliedCheck = R.getValueAsString("ImpliedCheck"); 
-  Ret.ImpliedValue = 
-      R.getValueAsOptionalString("ImpliedValue").getValueOr(Ret.DefaultValue); 
-
-  Ret.ShouldParse = R.getValueAsString("ShouldParse"); 
-  Ret.Normalizer = R.getValueAsString("Normalizer"); 
-  Ret.Denormalizer = R.getValueAsString("Denormalizer"); 
-  Ret.ValueMerger = R.getValueAsString("ValueMerger"); 
-  Ret.ValueExtractor = R.getValueAsString("ValueExtractor"); 
- 
-  if (!isa<UnsetInit>(R.getValueInit("NormalizedValues"))) { 
-    assert(!isa<UnsetInit>(R.getValueInit("Values")) && 
-           "Cannot provide normalized values for value-less options"); 
-    Ret.TableIndex = MarshallingInfo::NextTableIndex++; 
-    Ret.NormalizedValues = R.getValueAsListOfStrings("NormalizedValues"); 
-    Ret.Values.reserve(Ret.NormalizedValues.size()); 
-    Ret.ValueTableName = getOptionName(R) + "ValueTable"; 
- 
-    StringRef ValuesStr = R.getValueAsString("Values"); 
-    for (;;) { 
-      size_t Idx = ValuesStr.find(','); 
-      if (Idx == StringRef::npos) 
-        break; 
-      if (Idx > 0) 
-        Ret.Values.push_back(ValuesStr.slice(0, Idx)); 
-      ValuesStr = ValuesStr.slice(Idx + 1, StringRef::npos); 
+private:
+  void emitScopedNormalizedValue(raw_ostream &OS,
+                                 StringRef NormalizedValue) const {
+    if (!NormalizedValuesScope.empty())
+      OS << NormalizedValuesScope << "::";
+    OS << NormalizedValue;
+  }
+};
+
+size_t MarshallingInfo::NextTableIndex = 0;
+
+static MarshallingInfo createMarshallingInfo(const Record &R) {
+  assert(!isa<UnsetInit>(R.getValueInit("KeyPath")) &&
+         !isa<UnsetInit>(R.getValueInit("DefaultValue")) &&
+         !isa<UnsetInit>(R.getValueInit("ValueMerger")) &&
+         "MarshallingInfo must have a provide a keypath, default value and a "
+         "value merger");
+
+  MarshallingInfo Ret(R);
+
+  Ret.ShouldAlwaysEmit = R.getValueAsBit("ShouldAlwaysEmit");
+  Ret.MacroPrefix = R.getValueAsString("MacroPrefix");
+  Ret.KeyPath = R.getValueAsString("KeyPath");
+  Ret.DefaultValue = R.getValueAsString("DefaultValue");
+  Ret.NormalizedValuesScope = R.getValueAsString("NormalizedValuesScope");
+  Ret.ImpliedCheck = R.getValueAsString("ImpliedCheck");
+  Ret.ImpliedValue =
+      R.getValueAsOptionalString("ImpliedValue").getValueOr(Ret.DefaultValue);
+
+  Ret.ShouldParse = R.getValueAsString("ShouldParse");
+  Ret.Normalizer = R.getValueAsString("Normalizer");
+  Ret.Denormalizer = R.getValueAsString("Denormalizer");
+  Ret.ValueMerger = R.getValueAsString("ValueMerger");
+  Ret.ValueExtractor = R.getValueAsString("ValueExtractor");
+
+  if (!isa<UnsetInit>(R.getValueInit("NormalizedValues"))) {
+    assert(!isa<UnsetInit>(R.getValueInit("Values")) &&
+           "Cannot provide normalized values for value-less options");
+    Ret.TableIndex = MarshallingInfo::NextTableIndex++;
+    Ret.NormalizedValues = R.getValueAsListOfStrings("NormalizedValues");
+    Ret.Values.reserve(Ret.NormalizedValues.size());
+    Ret.ValueTableName = getOptionName(R) + "ValueTable";
+
+    StringRef ValuesStr = R.getValueAsString("Values");
+    for (;;) {
+      size_t Idx = ValuesStr.find(',');
+      if (Idx == StringRef::npos)
+        break;
+      if (Idx > 0)
+        Ret.Values.push_back(ValuesStr.slice(0, Idx));
+      ValuesStr = ValuesStr.slice(Idx + 1, StringRef::npos);
     }
-    if (!ValuesStr.empty()) 
-      Ret.Values.push_back(ValuesStr); 
+    if (!ValuesStr.empty())
+      Ret.Values.push_back(ValuesStr);
 
-    assert(Ret.Values.size() == Ret.NormalizedValues.size() && 
-           "The number of normalized values doesn't match the number of " 
-           "values"); 
+    assert(Ret.Values.size() == Ret.NormalizedValues.size() &&
+           "The number of normalized values doesn't match the number of "
+           "values");
   }
 
   return Ret;
@@ -228,12 +228,12 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
   PrefixesT Prefixes;
   Prefixes.insert(std::make_pair(PrefixKeyT(), "prefix_0"));
   unsigned CurPrefix = 0;
-  for (const Record &R : llvm::make_pointee_range(Opts)) { 
-    std::vector<StringRef> RPrefixes = R.getValueAsListOfStrings("Prefixes"); 
-    PrefixKeyT PrefixKey(RPrefixes.begin(), RPrefixes.end()); 
+  for (const Record &R : llvm::make_pointee_range(Opts)) {
+    std::vector<StringRef> RPrefixes = R.getValueAsListOfStrings("Prefixes");
+    PrefixKeyT PrefixKey(RPrefixes.begin(), RPrefixes.end());
     unsigned NewPrefix = CurPrefix + 1;
-    std::string Prefix = (Twine("prefix_") + Twine(NewPrefix)).str(); 
-    if (Prefixes.insert(std::make_pair(PrefixKey, Prefix)).second) 
+    std::string Prefix = (Twine("prefix_") + Twine(NewPrefix)).str();
+    if (Prefixes.insert(std::make_pair(PrefixKey, Prefix)).second)
       CurPrefix = NewPrefix;
   }
 
@@ -243,16 +243,16 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
   OS << "// Prefixes\n\n";
   OS << "#ifdef PREFIX\n";
   OS << "#define COMMA ,\n";
-  for (const auto &Prefix : Prefixes) { 
+  for (const auto &Prefix : Prefixes) {
     OS << "PREFIX(";
 
     // Prefix name.
-    OS << Prefix.second; 
+    OS << Prefix.second;
 
     // Prefix values.
     OS << ", {";
-    for (StringRef PrefixKey : Prefix.first) 
-      OS << "\"" << PrefixKey << "\" COMMA "; 
+    for (StringRef PrefixKey : Prefix.first)
+      OS << "\"" << PrefixKey << "\" COMMA ";
     OS << "nullptr})\n";
   }
   OS << "#undef COMMA\n";
@@ -261,7 +261,7 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
   OS << "/////////\n";
   OS << "// Groups\n\n";
   OS << "#ifdef OPTION\n";
-  for (const Record &R : llvm::make_pointee_range(Groups)) { 
+  for (const Record &R : llvm::make_pointee_range(Groups)) {
     // Start a single option entry.
     OS << "OPTION(";
 
@@ -308,8 +308,8 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
 
   auto WriteOptRecordFields = [&](raw_ostream &OS, const Record &R) {
     // The option prefix;
-    std::vector<StringRef> RPrefixes = R.getValueAsListOfStrings("Prefixes"); 
-    OS << Prefixes[PrefixKeyT(RPrefixes.begin(), RPrefixes.end())] << ", "; 
+    std::vector<StringRef> RPrefixes = R.getValueAsListOfStrings("Prefixes");
+    OS << Prefixes[PrefixKeyT(RPrefixes.begin(), RPrefixes.end())] << ", ";
 
     // The option string.
     emitNameUsingSpelling(OS, R);
@@ -346,8 +346,8 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
       OS << "nullptr";
     } else {
       OS << "\"";
-      for (StringRef AliasArg : AliasArgs) 
-        OS << AliasArg << "\\0"; 
+      for (StringRef AliasArg : AliasArgs)
+        OS << AliasArg << "\\0";
       OS << "\"";
     }
 
@@ -391,63 +391,63 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
       OS << "nullptr";
   };
 
-  auto IsMarshallingOption = [](const Record &R) { 
-    return !isa<UnsetInit>(R.getValueInit("KeyPath")) && 
-           !R.getValueAsString("KeyPath").empty(); 
-  }; 
+  auto IsMarshallingOption = [](const Record &R) {
+    return !isa<UnsetInit>(R.getValueInit("KeyPath")) &&
+           !R.getValueAsString("KeyPath").empty();
+  };
 
-  std::vector<const Record *> OptsWithMarshalling; 
-  for (const Record &R : llvm::make_pointee_range(Opts)) { 
+  std::vector<const Record *> OptsWithMarshalling;
+  for (const Record &R : llvm::make_pointee_range(Opts)) {
     // Start a single option entry.
     OS << "OPTION(";
     WriteOptRecordFields(OS, R);
     OS << ")\n";
-    if (IsMarshallingOption(R)) 
-      OptsWithMarshalling.push_back(&R); 
+    if (IsMarshallingOption(R))
+      OptsWithMarshalling.push_back(&R);
   }
   OS << "#endif // OPTION\n";
 
-  auto CmpMarshallingOpts = [](const Record *const *A, const Record *const *B) { 
-    unsigned AID = (*A)->getID(); 
-    unsigned BID = (*B)->getID(); 
- 
-    if (AID < BID) 
-      return -1; 
-    if (AID > BID) 
-      return 1; 
-    return 0; 
-  }; 
-  // The RecordKeeper stores records (options) in lexicographical order, and we 
-  // have reordered the options again when generating prefix groups. We need to 
-  // restore the original definition order of options with marshalling to honor 
-  // the topology of the dependency graph implied by `DefaultAnyOf`. 
-  array_pod_sort(OptsWithMarshalling.begin(), OptsWithMarshalling.end(), 
-                 CmpMarshallingOpts); 
- 
-  std::vector<MarshallingInfo> MarshallingInfos; 
-  for (const auto *R : OptsWithMarshalling) 
-    MarshallingInfos.push_back(createMarshallingInfo(*R)); 
- 
-  for (const auto &MI : MarshallingInfos) { 
-    OS << "#ifdef " << MI.getMacroName() << "\n"; 
-    OS << MI.getMacroName() << "("; 
-    WriteOptRecordFields(OS, MI.R); 
+  auto CmpMarshallingOpts = [](const Record *const *A, const Record *const *B) {
+    unsigned AID = (*A)->getID();
+    unsigned BID = (*B)->getID();
+
+    if (AID < BID)
+      return -1;
+    if (AID > BID)
+      return 1;
+    return 0;
+  };
+  // The RecordKeeper stores records (options) in lexicographical order, and we
+  // have reordered the options again when generating prefix groups. We need to
+  // restore the original definition order of options with marshalling to honor
+  // the topology of the dependency graph implied by `DefaultAnyOf`.
+  array_pod_sort(OptsWithMarshalling.begin(), OptsWithMarshalling.end(),
+                 CmpMarshallingOpts);
+
+  std::vector<MarshallingInfo> MarshallingInfos;
+  for (const auto *R : OptsWithMarshalling)
+    MarshallingInfos.push_back(createMarshallingInfo(*R));
+
+  for (const auto &MI : MarshallingInfos) {
+    OS << "#ifdef " << MI.getMacroName() << "\n";
+    OS << MI.getMacroName() << "(";
+    WriteOptRecordFields(OS, MI.R);
     OS << ", ";
-    MI.emit(OS); 
+    MI.emit(OS);
     OS << ")\n";
-    OS << "#endif // " << MI.getMacroName() << "\n"; 
+    OS << "#endif // " << MI.getMacroName() << "\n";
   }
 
   OS << "\n";
   OS << "#ifdef SIMPLE_ENUM_VALUE_TABLE";
   OS << "\n";
-  OS << MarshallingInfo::ValueTablePreamble; 
+  OS << MarshallingInfo::ValueTablePreamble;
   std::vector<StringRef> ValueTableNames;
-  for (const auto &MI : MarshallingInfos) 
-    if (auto MaybeValueTableName = MI.emitValueTable(OS)) 
+  for (const auto &MI : MarshallingInfos)
+    if (auto MaybeValueTableName = MI.emitValueTable(OS))
       ValueTableNames.push_back(*MaybeValueTableName);
 
-  OS << MarshallingInfo::ValueTablesDecl << "{"; 
+  OS << MarshallingInfo::ValueTablesDecl << "{";
   for (auto ValueTableName : ValueTableNames)
     OS << "{" << ValueTableName << ", sizeof(" << ValueTableName
        << ") / sizeof(SimpleEnumValue)"
@@ -463,7 +463,7 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
   OS << "#ifdef OPTTABLE_ARG_INIT\n";
   OS << "//////////\n";
   OS << "// Option Values\n\n";
-  for (const Record &R : llvm::make_pointee_range(Opts)) { 
+  for (const Record &R : llvm::make_pointee_range(Opts)) {
     if (isa<UnsetInit>(R.getValueInit("ValuesCode")))
       continue;
     OS << "{\n";
diff --git a/contrib/libs/llvm12/utils/TableGen/PredicateExpander.cpp b/contrib/libs/llvm12/utils/TableGen/PredicateExpander.cpp
index 1bff258abd..a76640f6d1 100644
--- a/contrib/libs/llvm12/utils/TableGen/PredicateExpander.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/PredicateExpander.cpp
@@ -198,18 +198,18 @@ void PredicateExpander::expandCheckIsImmOperand(raw_ostream &OS, int OpIndex) {
      << "getOperand(" << OpIndex << ").isImm() ";
 }
 
-void PredicateExpander::expandCheckFunctionPredicateWithTII( 
-    raw_ostream &OS, StringRef MCInstFn, StringRef MachineInstrFn, 
-    StringRef TIIPtr) { 
-  if (!shouldExpandForMC()) { 
-    OS << (TIIPtr.empty() ? "TII" : TIIPtr) << "->" << MachineInstrFn; 
-    OS << (isByRef() ? "(MI)" : "(*MI)"); 
-    return; 
-  } 
- 
-  OS << MCInstFn << (isByRef() ? "(MI" : "(*MI") << ", MCII)"; 
-} 
- 
+void PredicateExpander::expandCheckFunctionPredicateWithTII(
+    raw_ostream &OS, StringRef MCInstFn, StringRef MachineInstrFn,
+    StringRef TIIPtr) {
+  if (!shouldExpandForMC()) {
+    OS << (TIIPtr.empty() ? "TII" : TIIPtr) << "->" << MachineInstrFn;
+    OS << (isByRef() ? "(MI)" : "(*MI)");
+    return;
+  }
+
+  OS << MCInstFn << (isByRef() ? "(MI" : "(*MI") << ", MCII)";
+}
+
 void PredicateExpander::expandCheckFunctionPredicate(raw_ostream &OS,
                                                      StringRef MCInstFn,
                                                      StringRef MachineInstrFn) {
@@ -370,19 +370,19 @@ void PredicateExpander::expandPredicate(raw_ostream &OS, const Record *Rec) {
     return expandPredicateSequence(OS, Rec->getValueAsListOfDefs("Predicates"),
                                    /* AllOf */ false);
 
-  if (Rec->isSubClassOf("CheckFunctionPredicate")) { 
+  if (Rec->isSubClassOf("CheckFunctionPredicate")) {
     return expandCheckFunctionPredicate(
         OS, Rec->getValueAsString("MCInstFnName"),
         Rec->getValueAsString("MachineInstrFnName"));
-  } 
-
-  if (Rec->isSubClassOf("CheckFunctionPredicateWithTII")) { 
-    return expandCheckFunctionPredicateWithTII( 
-        OS, Rec->getValueAsString("MCInstFnName"), 
-        Rec->getValueAsString("MachineInstrFnName"), 
-        Rec->getValueAsString("TIIPtrName")); 
-  } 
- 
+  }
+
+  if (Rec->isSubClassOf("CheckFunctionPredicateWithTII")) {
+    return expandCheckFunctionPredicateWithTII(
+        OS, Rec->getValueAsString("MCInstFnName"),
+        Rec->getValueAsString("MachineInstrFnName"),
+        Rec->getValueAsString("TIIPtrName"));
+  }
+
   if (Rec->isSubClassOf("CheckNonPortable"))
     return expandCheckNonPortable(OS, Rec->getValueAsString("CodeBlock"));
 
diff --git a/contrib/libs/llvm12/utils/TableGen/PredicateExpander.h b/contrib/libs/llvm12/utils/TableGen/PredicateExpander.h
index 06925d413d..29cca92d90 100644
--- a/contrib/libs/llvm12/utils/TableGen/PredicateExpander.h
+++ b/contrib/libs/llvm12/utils/TableGen/PredicateExpander.h
@@ -79,9 +79,9 @@ public:
   void expandCheckInvalidRegOperand(raw_ostream &OS, int OpIndex);
   void expandCheckFunctionPredicate(raw_ostream &OS, StringRef MCInstFn,
                                     StringRef MachineInstrFn);
-  void expandCheckFunctionPredicateWithTII(raw_ostream &OS, StringRef MCInstFn, 
-                                           StringRef MachineInstrFn, 
-                                           StringRef TIIPtr); 
+  void expandCheckFunctionPredicateWithTII(raw_ostream &OS, StringRef MCInstFn,
+                                           StringRef MachineInstrFn,
+                                           StringRef TIIPtr);
   void expandCheckNonPortable(raw_ostream &OS, StringRef CodeBlock);
   void expandPredicate(raw_ostream &OS, const Record *Rec);
   void expandReturnStatement(raw_ostream &OS, const Record *Rec);
diff --git a/contrib/libs/llvm12/utils/TableGen/PseudoLoweringEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/PseudoLoweringEmitter.cpp
index 7569326cb3..e05409db67 100644
--- a/contrib/libs/llvm12/utils/TableGen/PseudoLoweringEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/PseudoLoweringEmitter.cpp
@@ -89,15 +89,15 @@ addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
       // problem.
       // FIXME: We probably shouldn't ever get a non-zero BaseIdx here.
       assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!");
-      // FIXME: Are the message operand types backward? 
-      if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) { 
-        PrintError(Rec, "In pseudo instruction '" + Rec->getName() + 
-                        "', operand type '" + DI->getDef()->getName() + 
-                        "' does not match expansion operand type '" + 
-                        Insn.Operands[BaseIdx + i].Rec->getName() + "'"); 
-        PrintFatalNote(DI->getDef(), 
-                       "Value was assigned at the following location:"); 
-      } 
+      // FIXME: Are the message operand types backward?
+      if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) {
+        PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
+                        "', operand type '" + DI->getDef()->getName() +
+                        "' does not match expansion operand type '" +
+                        Insn.Operands[BaseIdx + i].Rec->getName() + "'");
+        PrintFatalNote(DI->getDef(),
+                       "Value was assigned at the following location:");
+      }
       // Source operand maps to destination operand. The Data element
       // will be filled in later, just set the Kind for now. Do it
       // for each corresponding MachineInstr operand, not just the first.
@@ -132,38 +132,38 @@ void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) {
   LLVM_DEBUG(dbgs() << "  Result: " << *Dag << "\n");
 
   DefInit *OpDef = dyn_cast<DefInit>(Dag->getOperator());
-  if (!OpDef) { 
-    PrintError(Rec, "In pseudo instruction '" + Rec->getName() + 
-                    "', result operator is not a record"); 
-    PrintFatalNote(Rec->getValue("ResultInst"), 
-                   "Result was assigned at the following location:"); 
-  } 
+  if (!OpDef) {
+    PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
+                    "', result operator is not a record");
+    PrintFatalNote(Rec->getValue("ResultInst"),
+                   "Result was assigned at the following location:");
+  }
   Record *Operator = OpDef->getDef();
-  if (!Operator->isSubClassOf("Instruction")) { 
-    PrintError(Rec, "In pseudo instruction '" + Rec->getName() + 
-                    "', result operator '" + Operator->getName() + 
-                    "' is not an instruction"); 
-    PrintFatalNote(Rec->getValue("ResultInst"), 
-                   "Result was assigned at the following location:"); 
-  } 
+  if (!Operator->isSubClassOf("Instruction")) {
+    PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
+                    "', result operator '" + Operator->getName() +
+                    "' is not an instruction");
+    PrintFatalNote(Rec->getValue("ResultInst"),
+                   "Result was assigned at the following location:");
+  }
 
   CodeGenInstruction Insn(Operator);
 
-  if (Insn.isCodeGenOnly || Insn.isPseudo) { 
-    PrintError(Rec, "In pseudo instruction '" + Rec->getName() + 
-                    "', result operator '" + Operator->getName() + 
-                    "' cannot be a pseudo instruction"); 
-    PrintFatalNote(Rec->getValue("ResultInst"), 
-                   "Result was assigned at the following location:"); 
-  } 
-
-  if (Insn.Operands.size() != Dag->getNumArgs()) { 
-    PrintError(Rec, "In pseudo instruction '" + Rec->getName() + 
-                    "', result operator '" + Operator->getName() + 
-                    "' has the wrong number of operands"); 
-    PrintFatalNote(Rec->getValue("ResultInst"), 
-                   "Result was assigned at the following location:"); 
-  } 
+  if (Insn.isCodeGenOnly || Insn.isPseudo) {
+    PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
+                    "', result operator '" + Operator->getName() +
+                    "' cannot be a pseudo instruction");
+    PrintFatalNote(Rec->getValue("ResultInst"),
+                   "Result was assigned at the following location:");
+  }
+
+  if (Insn.Operands.size() != Dag->getNumArgs()) {
+    PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
+                    "', result operator '" + Operator->getName() +
+                    "' has the wrong number of operands");
+    PrintFatalNote(Rec->getValue("ResultInst"),
+                   "Result was assigned at the following location:");
+  }
 
   unsigned NumMIOperands = 0;
   for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
@@ -196,13 +196,13 @@ void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) {
       continue;
     StringMap<unsigned>::iterator SourceOp =
       SourceOperands.find(Dag->getArgNameStr(i));
-    if (SourceOp == SourceOperands.end()) { 
-      PrintError(Rec, "In pseudo instruction '" + Rec->getName() + 
-                      "', output operand '" + Dag->getArgNameStr(i) + 
-                      "' has no matching source operand"); 
-      PrintFatalNote(Rec->getValue("ResultInst"), 
-                     "Value was assigned at the following location:"); 
-    } 
+    if (SourceOp == SourceOperands.end()) {
+      PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
+                      "', output operand '" + Dag->getArgNameStr(i) +
+                      "' has no matching source operand");
+      PrintFatalNote(Rec->getValue("ResultInst"),
+                     "Value was assigned at the following location:");
+    }
     // Map the source operand to the destination operand index for each
     // MachineInstr operand.
     for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
@@ -226,15 +226,15 @@ void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
 
   if (!Expansions.empty()) {
     o << "  switch (MI->getOpcode()) {\n"
-      << "  default: return false;\n"; 
+      << "  default: return false;\n";
     for (auto &Expansion : Expansions) {
       CodeGenInstruction &Source = Expansion.Source;
       CodeGenInstruction &Dest = Expansion.Dest;
-      o << "  case " << Source.Namespace << "::" 
+      o << "  case " << Source.Namespace << "::"
         << Source.TheDef->getName() << ": {\n"
-        << "    MCInst TmpInst;\n" 
-        << "    MCOperand MCOp;\n" 
-        << "    TmpInst.setOpcode(" << Dest.Namespace << "::" 
+        << "    MCInst TmpInst;\n"
+        << "    MCOperand MCOp;\n"
+        << "    TmpInst.setOpcode(" << Dest.Namespace << "::"
         << Dest.TheDef->getName() << ");\n";
 
       // Copy the operands from the source instruction.
@@ -243,23 +243,23 @@ void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
       //        expansion DAG.
       unsigned MIOpNo = 0;
       for (const auto &DestOperand : Dest.Operands) {
-        o << "    // Operand: " << DestOperand.Name << "\n"; 
+        o << "    // Operand: " << DestOperand.Name << "\n";
         for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) {
           switch (Expansion.OperandMap[MIOpNo + i].Kind) {
             case OpData::Operand:
-            o << "    lowerOperand(MI->getOperand(" 
+            o << "    lowerOperand(MI->getOperand("
               << Source.Operands[Expansion.OperandMap[MIOpNo].Data
               .Operand].MIOperandNo + i
               << "), MCOp);\n"
-              << "    TmpInst.addOperand(MCOp);\n"; 
+              << "    TmpInst.addOperand(MCOp);\n";
             break;
             case OpData::Imm:
-            o << "    TmpInst.addOperand(MCOperand::createImm(" 
+            o << "    TmpInst.addOperand(MCOperand::createImm("
               << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
             break;
             case OpData::Reg: {
               Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
-              o << "    TmpInst.addOperand(MCOperand::createReg("; 
+              o << "    TmpInst.addOperand(MCOperand::createReg(";
               // "zero_reg" is special.
               if (Reg->getName() == "zero_reg")
                 o << "0";
@@ -275,15 +275,15 @@ void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
       }
       if (Dest.Operands.isVariadic) {
         MIOpNo = Source.Operands.size() + 1;
-        o << "    // variable_ops\n"; 
-        o << "    for (unsigned i = " << MIOpNo 
+        o << "    // variable_ops\n";
+        o << "    for (unsigned i = " << MIOpNo
           << ", e = MI->getNumOperands(); i != e; ++i)\n"
-          << "      if (lowerOperand(MI->getOperand(i), MCOp))\n" 
-          << "        TmpInst.addOperand(MCOp);\n"; 
+          << "      if (lowerOperand(MI->getOperand(i), MCOp))\n"
+          << "        TmpInst.addOperand(MCOp);\n";
       }
-      o << "    EmitToStreamer(OutStreamer, TmpInst);\n" 
-        << "    break;\n" 
-        << "  }\n"; 
+      o << "    EmitToStreamer(OutStreamer, TmpInst);\n"
+        << "    break;\n"
+        << "  }\n";
     }
     o << "  }\n  return true;";
   } else
@@ -293,18 +293,18 @@ void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
 }
 
 void PseudoLoweringEmitter::run(raw_ostream &o) {
-  StringRef Classes[] = {"PseudoInstExpansion", "Instruction"}; 
-  std::vector<Record *> Insts = 
-      Records.getAllDerivedDefinitions(makeArrayRef(Classes)); 
+  StringRef Classes[] = {"PseudoInstExpansion", "Instruction"};
+  std::vector<Record *> Insts =
+      Records.getAllDerivedDefinitions(makeArrayRef(Classes));
 
   // Process the pseudo expansion definitions, validating them as we do so.
-  Records.startTimer("Process definitions"); 
+  Records.startTimer("Process definitions");
   for (unsigned i = 0, e = Insts.size(); i != e; ++i)
     evaluateExpansion(Insts[i]);
 
   // Generate expansion code to lower the pseudo to an MCInst of the real
   // instruction.
-  Records.startTimer("Emit expansion code"); 
+  Records.startTimer("Emit expansion code");
   emitLoweringEmitter(o);
 }
 
diff --git a/contrib/libs/llvm12/utils/TableGen/RISCVCompressInstEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/RISCVCompressInstEmitter.cpp
index e3ec2c7f21..183c8f9494 100644
--- a/contrib/libs/llvm12/utils/TableGen/RISCVCompressInstEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -37,11 +37,11 @@
 // compressing/uncompressing MCInst instructions, plus
 // some helper functions:
 //
-// bool compressInst(MCInst &OutInst, const MCInst &MI, 
+// bool compressInst(MCInst &OutInst, const MCInst &MI,
 //                   const MCSubtargetInfo &STI,
 //                   MCContext &Context);
 //
-// bool uncompressInst(MCInst &OutInst, const MCInst &MI, 
+// bool uncompressInst(MCInst &OutInst, const MCInst &MI,
 //                     const MCRegisterInfo &MRI,
 //                     const MCSubtargetInfo &STI);
 //
@@ -101,12 +101,12 @@ class RISCVCompressInstEmitter {
     IndexedMap<OpData>
         DestOperandMap; // Maps operands in the Dest Instruction
                         // to the corresponding Source instruction operand.
-    bool IsCompressOnly; 
+    bool IsCompressOnly;
     CompressPat(CodeGenInstruction &S, CodeGenInstruction &D,
                 std::vector<Record *> RF, IndexedMap<OpData> &SourceMap,
-                IndexedMap<OpData> &DestMap, bool IsCompressOnly) 
+                IndexedMap<OpData> &DestMap, bool IsCompressOnly)
         : Source(S), Dest(D), PatReqFeatures(RF), SourceOperandMap(SourceMap),
-          DestOperandMap(DestMap), IsCompressOnly(IsCompressOnly) {} 
+          DestOperandMap(DestMap), IsCompressOnly(IsCompressOnly) {}
   };
   enum EmitterType { Compress, Uncompress, CheckCompress };
   RecordKeeper &Records;
@@ -139,12 +139,12 @@ public:
 } // End anonymous namespace.
 
 bool RISCVCompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) {
-  assert(Reg->isSubClassOf("Register") && "Reg record should be a Register"); 
-  assert(RegClass->isSubClassOf("RegisterClass") && 
-         "RegClass record should be a RegisterClass"); 
+  assert(Reg->isSubClassOf("Register") && "Reg record should be a Register");
+  assert(RegClass->isSubClassOf("RegisterClass") &&
+         "RegClass record should be a RegisterClass");
   const CodeGenRegisterClass &RC = Target.getRegisterClass(RegClass);
   const CodeGenRegister *R = Target.getRegisterByName(Reg->getName().lower());
-  assert((R != nullptr) && "Register not defined!!"); 
+  assert((R != nullptr) && "Register not defined!!");
   return RC.contains(R);
 }
 
@@ -237,9 +237,9 @@ void RISCVCompressInstEmitter::addDagOperandMapping(
       if (Inst.Operands[i].Rec->isSubClassOf("RegisterClass"))
         PrintFatalError(
             Rec->getLoc(),
-            "Error in Dag '" + Dag->getAsString() + "' Found immediate: '" + 
-                II->getAsString() + 
-                "' but corresponding instruction operand expected a register!"); 
+            "Error in Dag '" + Dag->getAsString() + "' Found immediate: '" +
+                II->getAsString() +
+                "' but corresponding instruction operand expected a register!");
       // No pattern validation check possible for values of fixed immediate.
       OperandMap[i].Kind = OpData::Imm;
       OperandMap[i].Data.Imm = II->getValue();
@@ -285,7 +285,7 @@ static bool verifyDagOpCount(CodeGenInstruction &Inst, DagInit *Dag,
 }
 
 static bool validateArgsTypes(Init *Arg1, Init *Arg2) {
-  return cast<DefInit>(Arg1)->getDef() == cast<DefInit>(Arg2)->getDef(); 
+  return cast<DefInit>(Arg1)->getDef() == cast<DefInit>(Arg2)->getDef();
 }
 
 // Creates a mapping between the operand name in the Dag (e.g. $rs1) and
@@ -467,8 +467,8 @@ void RISCVCompressInstEmitter::evaluateCompressPat(Record *Rec) {
   });
 
   CompressPatterns.push_back(CompressPat(SourceInst, DestInst, PatReqFeatures,
-                                         SourceOperandMap, DestOperandMap, 
-                                         Rec->getValueAsBit("isCompressOnly"))); 
+                                         SourceOperandMap, DestOperandMap,
+                                         Rec->getValueAsBit("isCompressOnly")));
 }
 
 static void
@@ -511,7 +511,7 @@ getReqFeatures(std::set<std::pair<bool, StringRef>> &FeaturesSet,
 static unsigned getPredicates(DenseMap<const Record *, unsigned> &PredicateMap,
                               std::vector<const Record *> &Predicates,
                               Record *Rec, StringRef Name) {
-  unsigned &Entry = PredicateMap[Rec]; 
+  unsigned &Entry = PredicateMap[Rec];
   if (Entry)
     return Entry;
 
@@ -522,28 +522,28 @@ static unsigned getPredicates(DenseMap<const Record *, unsigned> &PredicateMap,
   }
 
   PrintFatalError(Rec->getLoc(), "No " + Name +
-                                     " predicate on this operand at all: '" + 
-                                     Rec->getName() + "'"); 
+                                     " predicate on this operand at all: '" +
+                                     Rec->getName() + "'");
   return 0;
 }
 
-static void printPredicates(const std::vector<const Record *> &Predicates, 
+static void printPredicates(const std::vector<const Record *> &Predicates,
                             StringRef Name, raw_ostream &o) {
   for (unsigned i = 0; i < Predicates.size(); ++i) {
-    StringRef Pred = Predicates[i]->getValueAsString(Name); 
-    o << "  case " << i + 1 << ": {\n" 
-      << "  // " << Predicates[i]->getName() << "\n" 
-      << "  " << Pred << "\n" 
-      << "  }\n"; 
+    StringRef Pred = Predicates[i]->getValueAsString(Name);
+    o << "  case " << i + 1 << ": {\n"
+      << "  // " << Predicates[i]->getName() << "\n"
+      << "  " << Pred << "\n"
+      << "  }\n";
   }
 }
 
-static void mergeCondAndCode(raw_ostream &CombinedStream, StringRef CondStr, 
-                             StringRef CodeStr) { 
-  // Remove first indentation and last '&&'. 
-  CondStr = CondStr.drop_front(6).drop_back(4); 
-  CombinedStream.indent(4) << "if (" << CondStr << ") {\n"; 
-  CombinedStream << CodeStr; 
+static void mergeCondAndCode(raw_ostream &CombinedStream, StringRef CondStr,
+                             StringRef CodeStr) {
+  // Remove first indentation and last '&&'.
+  CondStr = CondStr.drop_front(6).drop_back(4);
+  CombinedStream.indent(4) << "if (" << CondStr << ") {\n";
+  CombinedStream << CodeStr;
   CombinedStream.indent(4) << "  return true;\n";
   CombinedStream.indent(4) << "} // if\n";
 }
@@ -556,20 +556,20 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
                     "'PassSubtarget' is false. SubTargetInfo object is needed "
                     "for target features.\n");
 
-  StringRef Namespace = Target.getName(); 
+  StringRef Namespace = Target.getName();
 
   // Sort entries in CompressPatterns to handle instructions that can have more
   // than one candidate for compression\uncompression, e.g ADD can be
   // transformed to a C_ADD or a C_MV. When emitting 'uncompress()' function the
   // source and destination are flipped and the sort key needs to change
   // accordingly.
-  llvm::stable_sort(CompressPatterns, [EType](const CompressPat &LHS, 
-                                              const CompressPat &RHS) { 
-    if (EType == EmitterType::Compress || EType == EmitterType::CheckCompress) 
-      return (LHS.Source.TheDef->getName() < RHS.Source.TheDef->getName()); 
-    else 
-      return (LHS.Dest.TheDef->getName() < RHS.Dest.TheDef->getName()); 
-  }); 
+  llvm::stable_sort(CompressPatterns, [EType](const CompressPat &LHS,
+                                              const CompressPat &RHS) {
+    if (EType == EmitterType::Compress || EType == EmitterType::CheckCompress)
+      return (LHS.Source.TheDef->getName() < RHS.Source.TheDef->getName());
+    else
+      return (LHS.Dest.TheDef->getName() < RHS.Dest.TheDef->getName());
+  });
 
   // A list of MCOperandPredicates for all operands in use, and the reverse map.
   std::vector<const Record *> MCOpPredicates;
@@ -595,17 +595,17 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
       << "#undef GEN_CHECK_COMPRESS_INSTR\n\n";
 
   if (EType == EmitterType::Compress) {
-    FuncH << "static bool compressInst(MCInst &OutInst,\n"; 
+    FuncH << "static bool compressInst(MCInst &OutInst,\n";
     FuncH.indent(25) << "const MCInst &MI,\n";
     FuncH.indent(25) << "const MCSubtargetInfo &STI,\n";
     FuncH.indent(25) << "MCContext &Context) {\n";
   } else if (EType == EmitterType::Uncompress){
-    FuncH << "static bool uncompressInst(MCInst &OutInst,\n"; 
+    FuncH << "static bool uncompressInst(MCInst &OutInst,\n";
     FuncH.indent(27) << "const MCInst &MI,\n";
     FuncH.indent(27) << "const MCRegisterInfo &MRI,\n";
     FuncH.indent(27) << "const MCSubtargetInfo &STI) {\n";
   } else if (EType == EmitterType::CheckCompress) {
-    FuncH << "static bool isCompressibleInst(const MachineInstr &MI,\n"; 
+    FuncH << "static bool isCompressibleInst(const MachineInstr &MI,\n";
     FuncH.indent(27) << "const RISCVSubtarget *Subtarget,\n";
     FuncH.indent(27) << "const MCRegisterInfo &MRI,\n";
     FuncH.indent(27) << "const MCSubtargetInfo &STI) {\n";
@@ -623,10 +623,10 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
     return;
   }
 
-  std::string CaseString; 
+  std::string CaseString;
   raw_string_ostream CaseStream(CaseString);
-  StringRef PrevOp; 
-  StringRef CurOp; 
+  StringRef PrevOp;
+  StringRef CurOp;
   CaseStream << "  switch (MI.getOpcode()) {\n";
   CaseStream << "    default: return false;\n";
 
@@ -636,9 +636,9 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
     EType == EmitterType::Compress || EType == EmitterType::Uncompress;
 
   for (auto &CompressPat : CompressPatterns) {
-    if (EType == EmitterType::Uncompress && CompressPat.IsCompressOnly) 
-      continue; 
- 
+    if (EType == EmitterType::Uncompress && CompressPat.IsCompressOnly)
+      continue;
+
     std::string CondString;
     std::string CodeString;
     raw_string_ostream CondStream(CondString);
@@ -652,10 +652,10 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
     IndexedMap<OpData> &DestOperandMap = CompressOrCheck ?
       CompressPat.DestOperandMap : CompressPat.SourceOperandMap;
 
-    CurOp = Source.TheDef->getName(); 
+    CurOp = Source.TheDef->getName();
     // Check current and previous opcode to decide to continue or end a case.
     if (CurOp != PrevOp) {
-      if (!PrevOp.empty()) 
+      if (!PrevOp.empty())
         CaseStream.indent(6) << "break;\n    } // case " + PrevOp + "\n";
       CaseStream.indent(4) << "case " + Namespace + "::" + CurOp + ": {\n";
     }
@@ -676,9 +676,9 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
     // Emit checks for all required features.
     for (auto &Op : FeaturesSet) {
       StringRef Not = Op.first ? "!" : "";
-      CondStream.indent(6) << Not << "STI.getFeatureBits()[" << Namespace 
-                           << "::" << Op.second << "]" 
-                           << " &&\n"; 
+      CondStream.indent(6) << Not << "STI.getFeatureBits()[" << Namespace
+                           << "::" << Op.second << "]"
+                           << " &&\n";
     }
 
     // Emit checks for all required feature groups.
@@ -687,8 +687,8 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
       for (auto &Op : Set) {
         bool isLast = &Op == &*Set.rbegin();
         StringRef Not = Op.first ? "!" : "";
-        CondStream << Not << "STI.getFeatureBits()[" << Namespace 
-                   << "::" << Op.second << "]"; 
+        CondStream << Not << "STI.getFeatureBits()[" << Namespace
+                   << "::" << Op.second << "]";
         if (!isLast)
           CondStream << " || ";
       }
@@ -701,8 +701,8 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
       if (SourceOperandMap[OpNo].TiedOpIdx != -1) {
         if (Source.Operands[OpNo].Rec->isSubClassOf("RegisterClass"))
           CondStream.indent(6)
-              << "(MI.getOperand(" << OpNo << ").getReg() ==  MI.getOperand(" 
-              << SourceOperandMap[OpNo].TiedOpIdx << ").getReg()) &&\n"; 
+              << "(MI.getOperand(" << OpNo << ").getReg() ==  MI.getOperand("
+              << SourceOperandMap[OpNo].TiedOpIdx << ").getReg()) &&\n";
         else
           PrintFatalError("Unexpected tied operand types!\n");
       }
@@ -713,26 +713,26 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
         break;
       case OpData::Imm:
         CondStream.indent(6)
-            << "(MI.getOperand(" << OpNo << ").isImm()) &&\n" 
-            << "      (MI.getOperand(" << OpNo 
-            << ").getImm() == " << SourceOperandMap[OpNo].Data.Imm << ") &&\n"; 
+            << "(MI.getOperand(" << OpNo << ").isImm()) &&\n"
+            << "      (MI.getOperand(" << OpNo
+            << ").getImm() == " << SourceOperandMap[OpNo].Data.Imm << ") &&\n";
         break;
       case OpData::Reg: {
         Record *Reg = SourceOperandMap[OpNo].Data.Reg;
-        CondStream.indent(6) 
-            << "(MI.getOperand(" << OpNo << ").getReg() == " << Namespace 
-            << "::" << Reg->getName() << ") &&\n"; 
+        CondStream.indent(6)
+            << "(MI.getOperand(" << OpNo << ").getReg() == " << Namespace
+            << "::" << Reg->getName() << ") &&\n";
         break;
       }
       }
     }
-    CodeStream.indent(6) << "// " << Dest.AsmString << "\n"; 
+    CodeStream.indent(6) << "// " << Dest.AsmString << "\n";
     if (CompressOrUncompress)
-      CodeStream.indent(6) << "OutInst.setOpcode(" << Namespace 
-                           << "::" << Dest.TheDef->getName() << ");\n"; 
+      CodeStream.indent(6) << "OutInst.setOpcode(" << Namespace
+                           << "::" << Dest.TheDef->getName() << ");\n";
     OpNo = 0;
     for (const auto &DestOperand : Dest.Operands) {
-      CodeStream.indent(6) << "// Operand: " << DestOperand.Name << "\n"; 
+      CodeStream.indent(6) << "// Operand: " << DestOperand.Name << "\n";
       switch (DestOperandMap[OpNo].Kind) {
       case OpData::Operand: {
         unsigned OpIdx = DestOperandMap[OpNo].Data.Operand;
@@ -744,67 +744,67 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
           // Don't check register class if this is a tied operand, it was done
           // for the operand its tied to.
           if (DestOperand.getTiedRegister() == -1)
-            CondStream.indent(6) << "(MRI.getRegClass(" << Namespace 
-                                 << "::" << DestOperand.Rec->getName() 
-                                 << "RegClassID).contains(MI.getOperand(" 
-                                 << OpIdx << ").getReg())) &&\n"; 
+            CondStream.indent(6) << "(MRI.getRegClass(" << Namespace
+                                 << "::" << DestOperand.Rec->getName()
+                                 << "RegClassID).contains(MI.getOperand("
+                                 << OpIdx << ").getReg())) &&\n";
 
           if (CompressOrUncompress)
-            CodeStream.indent(6) 
-                << "OutInst.addOperand(MI.getOperand(" << OpIdx << "));\n"; 
+            CodeStream.indent(6)
+                << "OutInst.addOperand(MI.getOperand(" << OpIdx << "));\n";
         } else {
           // Handling immediate operands.
           if (CompressOrUncompress) {
-            unsigned Entry = 
-                getPredicates(MCOpPredicateMap, MCOpPredicates, DestOperand.Rec, 
-                              "MCOperandPredicate"); 
-            CondStream.indent(6) 
-                << Namespace << "ValidateMCOperand(" 
-                << "MI.getOperand(" << OpIdx << "), STI, " << Entry << ") &&\n"; 
+            unsigned Entry =
+                getPredicates(MCOpPredicateMap, MCOpPredicates, DestOperand.Rec,
+                              "MCOperandPredicate");
+            CondStream.indent(6)
+                << Namespace << "ValidateMCOperand("
+                << "MI.getOperand(" << OpIdx << "), STI, " << Entry << ") &&\n";
           } else {
-            unsigned Entry = 
-                getPredicates(ImmLeafPredicateMap, ImmLeafPredicates, 
-                              DestOperand.Rec, "ImmediateCode"); 
-            CondStream.indent(6) 
-                << "MI.getOperand(" << OpIdx << ").isImm() &&\n"; 
-            CondStream.indent(6) << Namespace << "ValidateMachineOperand(" 
-                                 << "MI.getOperand(" << OpIdx 
-                                 << "), Subtarget, " << Entry << ") &&\n"; 
+            unsigned Entry =
+                getPredicates(ImmLeafPredicateMap, ImmLeafPredicates,
+                              DestOperand.Rec, "ImmediateCode");
+            CondStream.indent(6)
+                << "MI.getOperand(" << OpIdx << ").isImm() &&\n";
+            CondStream.indent(6) << Namespace << "ValidateMachineOperand("
+                                 << "MI.getOperand(" << OpIdx
+                                 << "), Subtarget, " << Entry << ") &&\n";
           }
           if (CompressOrUncompress)
-            CodeStream.indent(6) 
-                << "OutInst.addOperand(MI.getOperand(" << OpIdx << "));\n"; 
+            CodeStream.indent(6)
+                << "OutInst.addOperand(MI.getOperand(" << OpIdx << "));\n";
         }
         break;
       }
       case OpData::Imm: {
         if (CompressOrUncompress) {
           unsigned Entry = getPredicates(MCOpPredicateMap, MCOpPredicates,
-                                         DestOperand.Rec, "MCOperandPredicate"); 
+                                         DestOperand.Rec, "MCOperandPredicate");
           CondStream.indent(6)
-              << Namespace << "ValidateMCOperand(" 
-              << "MCOperand::createImm(" << DestOperandMap[OpNo].Data.Imm 
-              << "), STI, " << Entry << ") &&\n"; 
+              << Namespace << "ValidateMCOperand("
+              << "MCOperand::createImm(" << DestOperandMap[OpNo].Data.Imm
+              << "), STI, " << Entry << ") &&\n";
         } else {
           unsigned Entry = getPredicates(ImmLeafPredicateMap, ImmLeafPredicates,
-                                         DestOperand.Rec, "ImmediateCode"); 
+                                         DestOperand.Rec, "ImmediateCode");
           CondStream.indent(6)
-              << Namespace 
-              << "ValidateMachineOperand(MachineOperand::CreateImm(" 
-              << DestOperandMap[OpNo].Data.Imm << "), SubTarget, " << Entry 
-              << ") &&\n"; 
+              << Namespace
+              << "ValidateMachineOperand(MachineOperand::CreateImm("
+              << DestOperandMap[OpNo].Data.Imm << "), SubTarget, " << Entry
+              << ") &&\n";
         }
         if (CompressOrUncompress)
-          CodeStream.indent(6) << "OutInst.addOperand(MCOperand::createImm(" 
-                               << DestOperandMap[OpNo].Data.Imm << "));\n"; 
+          CodeStream.indent(6) << "OutInst.addOperand(MCOperand::createImm("
+                               << DestOperandMap[OpNo].Data.Imm << "));\n";
       } break;
       case OpData::Reg: {
         if (CompressOrUncompress) {
           // Fixed register has been validated at pattern validation time.
           Record *Reg = DestOperandMap[OpNo].Data.Reg;
-          CodeStream.indent(6) 
-              << "OutInst.addOperand(MCOperand::createReg(" << Namespace 
-              << "::" << Reg->getName() << "));\n"; 
+          CodeStream.indent(6)
+              << "OutInst.addOperand(MCOperand::createReg(" << Namespace
+              << "::" << Reg->getName() << "));\n";
         }
       } break;
       }
@@ -812,12 +812,12 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
     }
     if (CompressOrUncompress)
       CodeStream.indent(6) << "OutInst.setLoc(MI.getLoc());\n";
-    mergeCondAndCode(CaseStream, CondStream.str(), CodeStream.str()); 
+    mergeCondAndCode(CaseStream, CondStream.str(), CodeStream.str());
     PrevOp = CurOp;
   }
   Func << CaseStream.str() << "\n";
   // Close brace for the last case.
-  Func.indent(4) << "} // case " << CurOp << "\n"; 
+  Func.indent(4) << "} // case " << CurOp << "\n";
   Func.indent(2) << "} // switch\n";
   Func.indent(2) << "return false;\n}\n";
 
@@ -842,7 +842,7 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
       << "ValidateMachineOperand(const MachineOperand &MO,\n"
       << "                  const RISCVSubtarget *Subtarget,\n"
       << "                  unsigned PredicateIndex) {\n"
-      << "  int64_t Imm = MO.getImm();\n" 
+      << "  int64_t Imm = MO.getImm();\n"
       << "  switch (PredicateIndex) {\n"
       << "  default:\n"
       << "    llvm_unreachable(\"Unknown ImmLeaf Predicate kind\");\n"
@@ -868,7 +868,7 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
 }
 
 void RISCVCompressInstEmitter::run(raw_ostream &o) {
-  std::vector<Record *> Insts = Records.getAllDerivedDefinitions("CompressPat"); 
+  std::vector<Record *> Insts = Records.getAllDerivedDefinitions("CompressPat");
 
   // Process the CompressPat definitions, validating them as we do so.
   for (unsigned i = 0, e = Insts.size(); i != e; ++i)
diff --git a/contrib/libs/llvm12/utils/TableGen/RegisterBankEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/RegisterBankEmitter.cpp
index 7e09e70c72..0725657150 100644
--- a/contrib/libs/llvm12/utils/TableGen/RegisterBankEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/RegisterBankEmitter.cpp
@@ -71,7 +71,7 @@ public:
 
   /// Add a register class to the bank without duplicates.
   void addRegisterClass(const CodeGenRegisterClass *RC) {
-    if (llvm::is_contained(RCs, RC)) 
+    if (llvm::is_contained(RCs, RC))
       return;
 
     // FIXME? We really want the register size rather than the spill size
@@ -128,12 +128,12 @@ void RegisterBankEmitter::emitHeader(raw_ostream &OS,
   // <Target>RegisterBankInfo.h
   OS << "namespace llvm {\n"
      << "namespace " << TargetName << " {\n"
-     << "enum : unsigned {\n"; 
- 
-  OS << "  InvalidRegBankID = ~0u,\n"; 
-  unsigned ID = 0; 
+     << "enum : unsigned {\n";
+
+  OS << "  InvalidRegBankID = ~0u,\n";
+  unsigned ID = 0;
   for (const auto &Bank : Banks)
-    OS << "  " << Bank.getEnumeratorName() << " = " << ID++ << ",\n"; 
+    OS << "  " << Bank.getEnumeratorName() << " = " << ID++ << ",\n";
   OS << "  NumRegisterBanks,\n"
      << "};\n"
      << "} // end namespace " << TargetName << "\n"
@@ -168,7 +168,7 @@ void RegisterBankEmitter::emitBaseClassDefinition(
 ///                to the class.
 static void visitRegisterBankClasses(
     const CodeGenRegBank &RegisterClassHierarchy,
-    const CodeGenRegisterClass *RC, const Twine &Kind, 
+    const CodeGenRegisterClass *RC, const Twine &Kind,
     std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn,
     SmallPtrSetImpl<const CodeGenRegisterClass *> &VisitedRCs) {
 
@@ -182,7 +182,7 @@ static void visitRegisterBankClasses(
 
   for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) {
     std::string TmpKind =
-        (Kind + " (" + PossibleSubclass.getName() + ")").str(); 
+        (Kind + " (" + PossibleSubclass.getName() + ")").str();
 
     // Visit each subclass of an explicitly named class.
     if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass))
@@ -279,7 +279,7 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
   StringRef TargetName = Target.getName();
   const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
 
-  Records.startTimer("Analyze records"); 
+  Records.startTimer("Analyze records");
   std::vector<RegisterBank> Banks;
   for (const auto &V : Records.getAllDerivedDefinitions("RegisterBank")) {
     SmallPtrSet<const CodeGenRegisterClass *, 8> VisitedRCs;
@@ -301,7 +301,7 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
   }
 
   // Warn about ambiguous MIR caused by register bank/class name clashes.
-  Records.startTimer("Warn ambiguous"); 
+  Records.startTimer("Warn ambiguous");
   for (const auto &Class : RegisterClassHierarchy.getRegClasses()) {
     for (const auto &Bank : Banks) {
       if (Bank.getName().lower() == StringRef(Class.getName()).lower()) {
@@ -314,7 +314,7 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
     }
   }
 
-  Records.startTimer("Emit output"); 
+  Records.startTimer("Emit output");
   emitSourceFileHeader("Register Bank Source Fragments", OS);
   OS << "#ifdef GET_REGBANK_DECLARATIONS\n"
      << "#undef GET_REGBANK_DECLARATIONS\n";
diff --git a/contrib/libs/llvm12/utils/TableGen/RegisterInfoEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/RegisterInfoEmitter.cpp
index 0d3b5fd4e9..dce7594dec 100644
--- a/contrib/libs/llvm12/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/RegisterInfoEmitter.cpp
@@ -127,7 +127,7 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS,
     OS << "  " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
   assert(Registers.size() == Registers.back().EnumValue &&
          "Register enum value mismatch!");
-  OS << "  NUM_TARGET_REGS // " << Registers.size()+1 << "\n"; 
+  OS << "  NUM_TARGET_REGS // " << Registers.size()+1 << "\n";
   OS << "};\n";
   if (!Namespace.empty())
     OS << "} // end namespace " << Namespace << "\n";
@@ -146,7 +146,7 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS,
     for (const auto &RC : RegisterClasses)
       OS << "  " << RC.getName() << "RegClassID"
          << " = " << RC.EnumValue << ",\n";
-    OS << "\n};\n"; 
+    OS << "\n};\n";
     if (!Namespace.empty())
       OS << "} // end namespace " << Namespace << "\n\n";
   }
@@ -323,7 +323,7 @@ EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
   OS << "/// Get the dimensions of register pressure impacted by this "
      << "register class.\n"
      << "/// Returns a -1 terminated array of pressure set IDs\n"
-     << "const int *" << ClassName << "::\n" 
+     << "const int *" << ClassName << "::\n"
      << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
   OS << "  static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32)
      << " RCSetStartTable[] = {\n    ";
@@ -337,7 +337,7 @@ EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
   OS << "/// Get the dimensions of register pressure impacted by this "
      << "register unit.\n"
      << "/// Returns a -1 terminated array of pressure set IDs\n"
-     << "const int *" << ClassName << "::\n" 
+     << "const int *" << ClassName << "::\n"
      << "getRegUnitPressureSets(unsigned RegUnit) const {\n"
      << "  assert(RegUnit < " << RegBank.getNumNativeRegUnits()
      << " && \"invalid register unit\");\n";
@@ -356,10 +356,10 @@ EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
 using DwarfRegNumsMapPair = std::pair<Record*, std::vector<int64_t>>;
 using DwarfRegNumsVecTy = std::vector<DwarfRegNumsMapPair>;
 
-static void finalizeDwarfRegNumsKeys(DwarfRegNumsVecTy &DwarfRegNums) { 
+static void finalizeDwarfRegNumsKeys(DwarfRegNumsVecTy &DwarfRegNums) {
   // Sort and unique to get a map-like vector. We want the last assignment to
   // match previous behaviour.
-  llvm::stable_sort(DwarfRegNums, on_first<LessRecordRegister>()); 
+  llvm::stable_sort(DwarfRegNums, on_first<LessRecordRegister>());
   // Warn about duplicate assignments.
   const Record *LastSeenReg = nullptr;
   for (const auto &X : DwarfRegNums) {
@@ -461,16 +461,16 @@ void RegisterInfoEmitter::EmitRegMappingTables(
 
     DefInit *DI = cast<DefInit>(V->getValue());
     Record *Alias = DI->getDef();
-    const auto &AliasIter = llvm::lower_bound( 
-        DwarfRegNums, Alias, [](const DwarfRegNumsMapPair &A, const Record *B) { 
-          return LessRecordRegister()(A.first, B); 
-        }); 
+    const auto &AliasIter = llvm::lower_bound(
+        DwarfRegNums, Alias, [](const DwarfRegNumsMapPair &A, const Record *B) {
+          return LessRecordRegister()(A.first, B);
+        });
     assert(AliasIter != DwarfRegNums.end() && AliasIter->first == Alias &&
            "Expected Alias to be present in map");
-    const auto &RegIter = llvm::lower_bound( 
-        DwarfRegNums, Reg, [](const DwarfRegNumsMapPair &A, const Record *B) { 
-          return LessRecordRegister()(A.first, B); 
-        }); 
+    const auto &RegIter = llvm::lower_bound(
+        DwarfRegNums, Reg, [](const DwarfRegNumsMapPair &A, const Record *B) {
+          return LessRecordRegister()(A.first, B);
+        });
     assert(RegIter != DwarfRegNums.end() && RegIter->first == Reg &&
            "Expected Reg to be present in map");
     RegIter->second = AliasIter->second;
@@ -957,7 +957,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
     const auto &RUMasks = Reg.getRegUnitLaneMasks();
     MaskVec &LaneMaskVec = RegUnitLaneMasks[i];
     assert(LaneMaskVec.empty());
-    llvm::append_range(LaneMaskVec, RUMasks); 
+    llvm::append_range(LaneMaskVec, RUMasks);
     // Terminator mask should not be used inside of the list.
 #ifndef NDEBUG
     for (LaneBitmask M : LaneMaskVec) {
@@ -1164,7 +1164,7 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
        << "  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl"
        << "(unsigned, LaneBitmask) const override;\n"
        << "  const TargetRegisterClass *getSubClassWithSubReg"
-       << "(const TargetRegisterClass *, unsigned) const override;\n"; 
+       << "(const TargetRegisterClass *, unsigned) const override;\n";
   }
   OS << "  const RegClassWeight &getRegClassWeight("
      << "const TargetRegisterClass *RC) const override;\n"
@@ -1285,8 +1285,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
         OS << CGH.getMode(M).Name;
       OS << ")\n";
       for (const auto &RC : RegisterClasses) {
-        assert(RC.EnumValue == EV && "Unexpected order of register classes"); 
-        ++EV; 
+        assert(RC.EnumValue == EV && "Unexpected order of register classes");
+        ++EV;
         (void)EV;
         const RegSizeInfo &RI = RC.RSI.get(M);
         OS << "  { " << RI.RegSize << ", " << RI.SpillSize << ", "
@@ -1433,7 +1433,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
   }
 
   OS << "\nnamespace {\n";
-  OS << "  const TargetRegisterClass *const RegisterClasses[] = {\n"; 
+  OS << "  const TargetRegisterClass *const RegisterClasses[] = {\n";
   for (const auto &RC : RegisterClasses)
     OS << "    &" << RC.getQualifiedName() << "RegClass,\n";
   OS << "  };\n";
@@ -1613,16 +1613,16 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
 
 void RegisterInfoEmitter::run(raw_ostream &OS) {
   CodeGenRegBank &RegBank = Target.getRegBank();
-  Records.startTimer("Print enums"); 
+  Records.startTimer("Print enums");
   runEnums(OS, Target, RegBank);
- 
-  Records.startTimer("Print MC registers"); 
+
+  Records.startTimer("Print MC registers");
   runMCDesc(OS, Target, RegBank);
- 
-  Records.startTimer("Print header fragment"); 
+
+  Records.startTimer("Print header fragment");
   runTargetHeader(OS, Target, RegBank);
- 
-  Records.startTimer("Print target registers"); 
+
+  Records.startTimer("Print target registers");
   runTargetDesc(OS, Target, RegBank);
 
   if (RegisterInfoDebug)
diff --git a/contrib/libs/llvm12/utils/TableGen/SearchableTableEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/SearchableTableEmitter.cpp
index 484b886f41..912d43b2ca 100644
--- a/contrib/libs/llvm12/utils/TableGen/SearchableTableEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/SearchableTableEmitter.cpp
@@ -12,8 +12,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "CodeGenIntrinsics.h" 
-#include "llvm/ADT/ArrayRef.h" 
+#include "CodeGenIntrinsics.h"
+#include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/Support/Format.h"
@@ -54,7 +54,7 @@ struct GenericEnum {
 struct GenericField {
   std::string Name;
   RecTy *RecType = nullptr;
-  bool IsCode = false; 
+  bool IsCode = false;
   bool IsIntrinsic = false;
   bool IsInstruction = false;
   GenericEnum *Enum = nullptr;
@@ -64,14 +64,14 @@ struct GenericField {
 
 struct SearchIndex {
   std::string Name;
-  SMLoc Loc; // Source location of PrimaryKey or Key field definition. 
+  SMLoc Loc; // Source location of PrimaryKey or Key field definition.
   SmallVector<GenericField, 1> Fields;
   bool EarlyOut = false;
 };
 
 struct GenericTable {
   std::string Name;
-  ArrayRef<SMLoc> Locs; // Source locations from the Record instance. 
+  ArrayRef<SMLoc> Locs; // Source locations from the Record instance.
   std::string PreprocessorGuard;
   std::string CppTypeName;
   SmallVector<GenericField, 2> Fields;
@@ -110,14 +110,14 @@ private:
     TypeInArgument,
   };
 
-  std::string primaryRepresentation(SMLoc Loc, const GenericField &Field, 
-                                    Init *I) { 
-    if (StringInit *SI = dyn_cast<StringInit>(I)) { 
-      if (Field.IsCode || SI->hasCodeFormat()) 
-        return std::string(SI->getValue()); 
-      else 
-        return SI->getAsString(); 
-    } else if (BitsInit *BI = dyn_cast<BitsInit>(I)) 
+  std::string primaryRepresentation(SMLoc Loc, const GenericField &Field,
+                                    Init *I) {
+    if (StringInit *SI = dyn_cast<StringInit>(I)) {
+      if (Field.IsCode || SI->hasCodeFormat())
+        return std::string(SI->getValue());
+      else
+        return SI->getAsString();
+    } else if (BitsInit *BI = dyn_cast<BitsInit>(I))
       return "0x" + utohexstr(getAsInt(BI));
     else if (BitInit *BI = dyn_cast<BitInit>(I))
       return BI->getValue() ? "true" : "false";
@@ -128,12 +128,12 @@ private:
     else if (Field.Enum) {
       auto *Entry = Field.Enum->EntryMap[cast<DefInit>(I)->getDef()];
       if (!Entry)
-        PrintFatalError(Loc, 
-                        Twine("Entry for field '") + Field.Name + "' is null"); 
+        PrintFatalError(Loc,
+                        Twine("Entry for field '") + Field.Name + "' is null");
       return std::string(Entry->first);
     }
-    PrintFatalError(Loc, Twine("invalid field type for field '") + Field.Name +  
-                             "'; expected: bit, bits, string, or code"); 
+    PrintFatalError(Loc, Twine("invalid field type for field '") + Field.Name + 
+                             "'; expected: bit, bits, string, or code");
   }
 
   bool isIntrinsic(Init *I) {
@@ -145,16 +145,16 @@ private:
   CodeGenIntrinsic &getIntrinsic(Init *I) {
     std::unique_ptr<CodeGenIntrinsic> &Intr = Intrinsics[I];
     if (!Intr)
-      Intr = std::make_unique<CodeGenIntrinsic>(cast<DefInit>(I)->getDef(), 
-                                                std::vector<Record *>()); 
+      Intr = std::make_unique<CodeGenIntrinsic>(cast<DefInit>(I)->getDef(),
+                                                std::vector<Record *>());
     return *Intr;
   }
 
   bool compareBy(Record *LHS, Record *RHS, const SearchIndex &Index);
 
-  std::string searchableFieldType(const GenericTable &Table, 
-                                  const SearchIndex &Index, 
-                                  const GenericField &Field, TypeContext Ctx) { 
+  std::string searchableFieldType(const GenericTable &Table,
+                                  const SearchIndex &Index,
+                                  const GenericField &Field, TypeContext Ctx) {
     if (isa<StringRecTy>(Field.RecType)) {
       if (Ctx == TypeInStaticStruct)
         return "const char *";
@@ -171,16 +171,16 @@ private:
         return "uint32_t";
       if (NumBits <= 64)
         return "uint64_t";
-      PrintFatalError(Index.Loc, Twine("In table '") + Table.Name +  
-                                     "' lookup method '" + Index.Name + 
-                                     "', key field '" + Field.Name + 
-                                     "' of type bits is too large"); 
+      PrintFatalError(Index.Loc, Twine("In table '") + Table.Name + 
+                                     "' lookup method '" + Index.Name +
+                                     "', key field '" + Field.Name +
+                                     "' of type bits is too large");
     } else if (Field.Enum || Field.IsIntrinsic || Field.IsInstruction)
       return "unsigned";
-    PrintFatalError(Index.Loc, 
-                    Twine("In table '") + Table.Name + "' lookup method '" + 
-                        Index.Name + "', key field '" + Field.Name + 
-                        "' has invalid type: " + Field.RecType->getAsString()); 
+    PrintFatalError(Index.Loc,
+                    Twine("In table '") + Table.Name + "' lookup method '" +
+                        Index.Name + "', key field '" + Field.Name +
+                        "' has invalid type: " + Field.RecType->getAsString());
   }
 
   void emitGenericTable(const GenericTable &Table, raw_ostream &OS);
@@ -193,7 +193,7 @@ private:
 
   bool parseFieldType(GenericField &Field, Init *II);
   std::unique_ptr<SearchIndex>
-  parseSearchIndex(GenericTable &Table, const RecordVal *RecVal, StringRef Name, 
+  parseSearchIndex(GenericTable &Table, const RecordVal *RecVal, StringRef Name,
                    const std::vector<StringRef> &Key, bool EarlyOut);
   void collectEnumEntries(GenericEnum &Enum, StringRef NameField,
                           StringRef ValueField,
@@ -268,8 +268,8 @@ bool SearchableTableEmitter::compareBy(Record *LHS, Record *RHS,
       if (LHSv > RHSv)
         return false;
     } else {
-      std::string LHSs = primaryRepresentation(Index.Loc, Field, LHSI); 
-      std::string RHSs = primaryRepresentation(Index.Loc, Field, RHSI); 
+      std::string LHSs = primaryRepresentation(Index.Loc, Field, LHSI);
+      std::string RHSs = primaryRepresentation(Index.Loc, Field, RHSI);
 
       if (isa<StringRecTy>(Field.RecType)) {
         LHSs = StringRef(LHSs).upper();
@@ -324,8 +324,8 @@ void SearchableTableEmitter::emitLookupFunction(const GenericTable &Table,
   } else {
     OS << "  struct IndexType {\n";
     for (const auto &Field : Index.Fields) {
-      OS << "    " 
-         << searchableFieldType(Table, Index, Field, TypeInStaticStruct) << " " 
+      OS << "    "
+         << searchableFieldType(Table, Index, Field, TypeInStaticStruct) << " "
          << Field.Name << ";\n";
     }
     OS << "    unsigned _index;\n";
@@ -338,10 +338,10 @@ void SearchableTableEmitter::emitLookupFunction(const GenericTable &Table,
     for (unsigned i = 0; i < Table.Entries.size(); ++i)
       Entries.emplace_back(Table.Entries[i], i);
 
-    llvm::stable_sort(Entries, [&](const std::pair<Record *, unsigned> &LHS, 
-                                   const std::pair<Record *, unsigned> &RHS) { 
-      return compareBy(LHS.first, RHS.first, Index); 
-    }); 
+    llvm::stable_sort(Entries, [&](const std::pair<Record *, unsigned> &LHS,
+                                   const std::pair<Record *, unsigned> &RHS) {
+      return compareBy(LHS.first, RHS.first, Index);
+    });
 
     IndexRowsStorage.reserve(Entries.size());
     for (const auto &Entry : Entries) {
@@ -354,8 +354,8 @@ void SearchableTableEmitter::emitLookupFunction(const GenericTable &Table,
           OS << ", ";
         NeedComma = true;
 
-        std::string Repr = primaryRepresentation( 
-            Index.Loc, Field, Entry.first->getValueInit(Field.Name)); 
+        std::string Repr = primaryRepresentation(
+            Index.Loc, Field, Entry.first->getValueInit(Field.Name));
         if (isa<StringRecTy>(Field.RecType))
           Repr = StringRef(Repr).upper();
         OS << Repr;
@@ -398,10 +398,10 @@ void SearchableTableEmitter::emitLookupFunction(const GenericTable &Table,
 
   if (Index.EarlyOut) {
     const GenericField &Field = Index.Fields[0];
-    std::string FirstRepr = primaryRepresentation( 
-        Index.Loc, Field, IndexRows[0]->getValueInit(Field.Name)); 
+    std::string FirstRepr = primaryRepresentation(
+        Index.Loc, Field, IndexRows[0]->getValueInit(Field.Name));
     std::string LastRepr = primaryRepresentation(
-        Index.Loc, Field, IndexRows.back()->getValueInit(Field.Name)); 
+        Index.Loc, Field, IndexRows.back()->getValueInit(Field.Name));
     OS << "  if ((" << Field.Name << " < " << FirstRepr << ") ||\n";
     OS << "      (" << Field.Name << " > " << LastRepr << "))\n";
     OS << "    return nullptr;\n\n";
@@ -409,11 +409,11 @@ void SearchableTableEmitter::emitLookupFunction(const GenericTable &Table,
 
   OS << "  struct KeyType {\n";
   for (const auto &Field : Index.Fields) {
-    OS << "    " << searchableFieldType(Table, Index, Field, TypeInTempStruct)  
-       << " " << Field.Name << ";\n"; 
+    OS << "    " << searchableFieldType(Table, Index, Field, TypeInTempStruct) 
+       << " " << Field.Name << ";\n";
   }
   OS << "  };\n";
-  OS << "  KeyType Key = {"; 
+  OS << "  KeyType Key = {";
   bool NeedComma = false;
   for (const auto &Field : Index.Fields) {
     if (NeedComma)
@@ -424,14 +424,14 @@ void SearchableTableEmitter::emitLookupFunction(const GenericTable &Table,
     if (isa<StringRecTy>(Field.RecType)) {
       OS << ".upper()";
       if (IsPrimary)
-        PrintFatalError(Index.Loc,  
-                        Twine("In table '") + Table.Name + 
-                            "', use a secondary lookup method for " 
-                            "case-insensitive comparison of field '" + 
-                            Field.Name + "'"); 
+        PrintFatalError(Index.Loc, 
+                        Twine("In table '") + Table.Name +
+                            "', use a secondary lookup method for "
+                            "case-insensitive comparison of field '" +
+                            Field.Name + "'");
     }
   }
-  OS << "};\n"; 
+  OS << "};\n";
 
   OS << "  auto Table = makeArrayRef(" << IndexName << ");\n";
   OS << "  auto Idx = std::lower_bound(Table.begin(), Table.end(), Key,\n";
@@ -488,8 +488,8 @@ void SearchableTableEmitter::emitLookupDeclaration(const GenericTable &Table,
       OS << ", ";
     NeedComma = true;
 
-    OS << searchableFieldType(Table, Index, Field, TypeInArgument) << " " 
-       << Field.Name; 
+    OS << searchableFieldType(Table, Index, Field, TypeInArgument) << " "
+       << Field.Name;
   }
   OS << ")";
 }
@@ -524,8 +524,8 @@ void SearchableTableEmitter::emitGenericTable(const GenericTable &Table,
         OS << ", ";
       NeedComma = true;
 
-      OS << primaryRepresentation(Table.Locs[0], Field, 
-                                  Entry->getValueInit(Field.Name)); 
+      OS << primaryRepresentation(Table.Locs[0], Field,
+                                  Entry->getValueInit(Field.Name));
     }
 
     OS << " }, // " << i << "\n";
@@ -542,49 +542,49 @@ void SearchableTableEmitter::emitGenericTable(const GenericTable &Table,
   OS << "#endif\n\n";
 }
 
-bool SearchableTableEmitter::parseFieldType(GenericField &Field, Init *TypeOf) { 
-  if (auto Type = dyn_cast<StringInit>(TypeOf)) { 
-    if (Type->getValue() == "code") { 
-      Field.IsCode = true; 
+bool SearchableTableEmitter::parseFieldType(GenericField &Field, Init *TypeOf) {
+  if (auto Type = dyn_cast<StringInit>(TypeOf)) {
+    if (Type->getValue() == "code") {
+      Field.IsCode = true;
       return true;
-    } else { 
-      if (Record *TypeRec = Records.getDef(Type->getValue())) { 
-        if (TypeRec->isSubClassOf("GenericEnum")) { 
-          Field.Enum = EnumMap[TypeRec]; 
-          Field.RecType = RecordRecTy::get(Field.Enum->Class); 
-          return true; 
-        } 
-      } 
+    } else {
+      if (Record *TypeRec = Records.getDef(Type->getValue())) {
+        if (TypeRec->isSubClassOf("GenericEnum")) {
+          Field.Enum = EnumMap[TypeRec];
+          Field.RecType = RecordRecTy::get(Field.Enum->Class);
+          return true;
+        }
+      }
     }
   }
 
   return false;
 }
 
-std::unique_ptr<SearchIndex> SearchableTableEmitter::parseSearchIndex( 
-    GenericTable &Table, const RecordVal *KeyRecVal, StringRef Name, 
-    const std::vector<StringRef> &Key, bool EarlyOut) { 
+std::unique_ptr<SearchIndex> SearchableTableEmitter::parseSearchIndex(
+    GenericTable &Table, const RecordVal *KeyRecVal, StringRef Name,
+    const std::vector<StringRef> &Key, bool EarlyOut) {
   auto Index = std::make_unique<SearchIndex>();
   Index->Name = std::string(Name);
-  Index->Loc = KeyRecVal->getLoc(); 
+  Index->Loc = KeyRecVal->getLoc();
   Index->EarlyOut = EarlyOut;
 
   for (const auto &FieldName : Key) {
     const GenericField *Field = Table.getFieldByName(FieldName);
     if (!Field)
-      PrintFatalError( 
-          KeyRecVal, 
-          Twine("In table '") + Table.Name + 
-              "', 'PrimaryKey' or 'Key' refers to nonexistent field '" + 
-              FieldName + "'"); 
-                       
+      PrintFatalError(
+          KeyRecVal,
+          Twine("In table '") + Table.Name +
+              "', 'PrimaryKey' or 'Key' refers to nonexistent field '" +
+              FieldName + "'");
+                      
     Index->Fields.push_back(*Field);
   }
 
   if (EarlyOut && isa<StringRecTy>(Index->Fields[0].RecType)) {
     PrintFatalError(
-        KeyRecVal, Twine("In lookup method '") + Name + "', early-out is not " + 
-                       "supported for a first key field of type string"); 
+        KeyRecVal, Twine("In lookup method '") + Name + "', early-out is not " +
+                       "supported for a first key field of type string");
   }
 
   return Index;
@@ -609,11 +609,11 @@ void SearchableTableEmitter::collectEnumEntries(
   }
 
   if (ValueField.empty()) {
-    llvm::stable_sort(Enum.Entries, 
-                      [](const std::unique_ptr<GenericEnum::Entry> &LHS, 
-                         const std::unique_ptr<GenericEnum::Entry> &RHS) { 
-                        return LHS->first < RHS->first; 
-                      }); 
+    llvm::stable_sort(Enum.Entries,
+                      [](const std::unique_ptr<GenericEnum::Entry> &LHS,
+                         const std::unique_ptr<GenericEnum::Entry> &RHS) {
+                        return LHS->first < RHS->first;
+                      });
 
     for (size_t i = 0; i < Enum.Entries.size(); ++i)
       Enum.Entries[i]->second = i;
@@ -623,33 +623,33 @@ void SearchableTableEmitter::collectEnumEntries(
 void SearchableTableEmitter::collectTableEntries(
     GenericTable &Table, const std::vector<Record *> &Items) {
   if (Items.empty())
-    PrintFatalError(Table.Locs, 
-                    Twine("Table '") + Table.Name + "' has no entries"); 
+    PrintFatalError(Table.Locs,
+                    Twine("Table '") + Table.Name + "' has no entries");
 
   for (auto EntryRec : Items) {
     for (auto &Field : Table.Fields) {
       auto TI = dyn_cast<TypedInit>(EntryRec->getValueInit(Field.Name));
       if (!TI || !TI->isComplete()) {
-        PrintFatalError(EntryRec, Twine("Record '") + EntryRec->getName() + 
-                                      "' for table '" + Table.Name + 
-                                      "' is missing field '" + Field.Name + 
-                                      "'"); 
+        PrintFatalError(EntryRec, Twine("Record '") + EntryRec->getName() +
+                                      "' for table '" + Table.Name +
+                                      "' is missing field '" + Field.Name +
+                                      "'");
       }
       if (!Field.RecType) {
         Field.RecType = TI->getType();
       } else {
         RecTy *Ty = resolveTypes(Field.RecType, TI->getType());
         if (!Ty)
-          PrintFatalError(EntryRec->getValue(Field.Name),  
-                          Twine("Field '") + Field.Name + "' of table '" + 
-                          Table.Name + "' entry has incompatible type: " + 
-                          TI->getType()->getAsString() + " vs. " + 
-                          Field.RecType->getAsString()); 
+          PrintFatalError(EntryRec->getValue(Field.Name), 
+                          Twine("Field '") + Field.Name + "' of table '" +
+                          Table.Name + "' entry has incompatible type: " +
+                          TI->getType()->getAsString() + " vs. " +
+                          Field.RecType->getAsString());
         Field.RecType = Ty;
       }
     }
 
-    Table.Entries.push_back(EntryRec); // Add record to table's record list. 
+    Table.Entries.push_back(EntryRec); // Add record to table's record list.
   }
 
   Record *IntrinsicClass = Records.getClass("Intrinsic");
@@ -690,9 +690,9 @@ void SearchableTableEmitter::run(raw_ostream &OS) {
     StringRef FilterClass = EnumRec->getValueAsString("FilterClass");
     Enum->Class = Records.getClass(FilterClass);
     if (!Enum->Class)
-      PrintFatalError(EnumRec->getValue("FilterClass"),  
-                      Twine("Enum FilterClass '") + FilterClass + 
-                          "' does not exist"); 
+      PrintFatalError(EnumRec->getValue("FilterClass"), 
+                      Twine("Enum FilterClass '") + FilterClass +
+                          "' does not exist");
 
     collectEnumEntries(*Enum, NameField, ValueField,
                        Records.getAllDerivedDefinitions(FilterClass));
@@ -703,44 +703,44 @@ void SearchableTableEmitter::run(raw_ostream &OS) {
   for (auto TableRec : Records.getAllDerivedDefinitions("GenericTable")) {
     auto Table = std::make_unique<GenericTable>();
     Table->Name = std::string(TableRec->getName());
-    Table->Locs = TableRec->getLoc(); 
+    Table->Locs = TableRec->getLoc();
     Table->PreprocessorGuard = std::string(TableRec->getName());
     Table->CppTypeName = std::string(TableRec->getValueAsString("CppTypeName"));
 
     std::vector<StringRef> Fields = TableRec->getValueAsListOfStrings("Fields");
     for (const auto &FieldName : Fields) {
-      Table->Fields.emplace_back(FieldName); // Construct a GenericField. 
-
-      if (auto TypeOfRecordVal = TableRec->getValue(("TypeOf_" + FieldName).str())) { 
-        if (!parseFieldType(Table->Fields.back(), TypeOfRecordVal->getValue())) { 
-          PrintError(TypeOfRecordVal,  
-                     Twine("Table '") + Table->Name + 
-                         "' has invalid 'TypeOf_" + FieldName + 
-                         "': " + TypeOfRecordVal->getValue()->getAsString()); 
-          PrintFatalNote("The 'TypeOf_xxx' field must be a string naming a " 
-                         "GenericEnum record, or \"code\""); 
+      Table->Fields.emplace_back(FieldName); // Construct a GenericField.
+
+      if (auto TypeOfRecordVal = TableRec->getValue(("TypeOf_" + FieldName).str())) {
+        if (!parseFieldType(Table->Fields.back(), TypeOfRecordVal->getValue())) {
+          PrintError(TypeOfRecordVal, 
+                     Twine("Table '") + Table->Name +
+                         "' has invalid 'TypeOf_" + FieldName +
+                         "': " + TypeOfRecordVal->getValue()->getAsString());
+          PrintFatalNote("The 'TypeOf_xxx' field must be a string naming a "
+                         "GenericEnum record, or \"code\"");
         }
       }
     }
 
-    StringRef FilterClass = TableRec->getValueAsString("FilterClass"); 
-    if (!Records.getClass(FilterClass)) 
-      PrintFatalError(TableRec->getValue("FilterClass"),  
-                      Twine("Table FilterClass '") + 
-                          FilterClass + "' does not exist"); 
+    StringRef FilterClass = TableRec->getValueAsString("FilterClass");
+    if (!Records.getClass(FilterClass))
+      PrintFatalError(TableRec->getValue("FilterClass"), 
+                      Twine("Table FilterClass '") +
+                          FilterClass + "' does not exist");
+
+    collectTableEntries(*Table, Records.getAllDerivedDefinitions(FilterClass));
 
-    collectTableEntries(*Table, Records.getAllDerivedDefinitions(FilterClass)); 
- 
     if (!TableRec->isValueUnset("PrimaryKey")) {
       Table->PrimaryKey =
-          parseSearchIndex(*Table, TableRec->getValue("PrimaryKey"), 
-                           TableRec->getValueAsString("PrimaryKeyName"), 
+          parseSearchIndex(*Table, TableRec->getValue("PrimaryKey"),
+                           TableRec->getValueAsString("PrimaryKeyName"),
                            TableRec->getValueAsListOfStrings("PrimaryKey"),
                            TableRec->getValueAsBit("PrimaryKeyEarlyOut"));
 
-      llvm::stable_sort(Table->Entries, [&](Record *LHS, Record *RHS) { 
-        return compareBy(LHS, RHS, *Table->PrimaryKey); 
-      }); 
+      llvm::stable_sort(Table->Entries, [&](Record *LHS, Record *RHS) {
+        return compareBy(LHS, RHS, *Table->PrimaryKey);
+      });
     }
 
     TableMap.insert(std::make_pair(TableRec, Table.get()));
@@ -751,16 +751,16 @@ void SearchableTableEmitter::run(raw_ostream &OS) {
     Record *TableRec = IndexRec->getValueAsDef("Table");
     auto It = TableMap.find(TableRec);
     if (It == TableMap.end())
-      PrintFatalError(IndexRec->getValue("Table"),  
+      PrintFatalError(IndexRec->getValue("Table"), 
                       Twine("SearchIndex '") + IndexRec->getName() +
-                          "' refers to nonexistent table '" + 
+                          "' refers to nonexistent table '" +
                           TableRec->getName());
 
     GenericTable &Table = *It->second;
-    Table.Indices.push_back( 
-        parseSearchIndex(Table, IndexRec->getValue("Key"), IndexRec->getName(),  
-                         IndexRec->getValueAsListOfStrings("Key"), 
-                         IndexRec->getValueAsBit("EarlyOut"))); 
+    Table.Indices.push_back(
+        parseSearchIndex(Table, IndexRec->getValue("Key"), IndexRec->getName(), 
+                         IndexRec->getValueAsListOfStrings("Key"),
+                         IndexRec->getValueAsBit("EarlyOut")));
   }
 
   // Translate legacy tables.
@@ -791,7 +791,7 @@ void SearchableTableEmitter::run(raw_ostream &OS) {
 
     auto Table = std::make_unique<GenericTable>();
     Table->Name = (Twine(Class->getName()) + "sList").str();
-    Table->Locs = Class->getLoc(); 
+    Table->Locs = Class->getLoc();
     Table->PreprocessorGuard = Class->getName().upper();
     Table->CppTypeName = std::string(Class->getName());
 
@@ -814,8 +814,8 @@ void SearchableTableEmitter::run(raw_ostream &OS) {
          Class->getValueAsListOfStrings("SearchableFields")) {
       std::string Name =
           (Twine("lookup") + Table->CppTypeName + "By" + Field).str();
-      Table->Indices.push_back(parseSearchIndex(*Table, Class->getValue(Field), 
-                                                Name, {Field}, false)); 
+      Table->Indices.push_back(parseSearchIndex(*Table, Class->getValue(Field),
+                                                Name, {Field}, false));
     }
 
     Tables.emplace_back(std::move(Table));
diff --git a/contrib/libs/llvm12/utils/TableGen/SubtargetEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/SubtargetEmitter.cpp
index 5da6a153a6..7d2b4b929d 100644
--- a/contrib/libs/llvm12/utils/TableGen/SubtargetEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/SubtargetEmitter.cpp
@@ -266,15 +266,15 @@ SubtargetEmitter::CPUKeyValues(raw_ostream &OS,
   for (Record *Processor : ProcessorList) {
     StringRef Name = Processor->getValueAsString("Name");
     RecVec FeatureList = Processor->getValueAsListOfDefs("Features");
-    RecVec TuneFeatureList = Processor->getValueAsListOfDefs("TuneFeatures"); 
+    RecVec TuneFeatureList = Processor->getValueAsListOfDefs("TuneFeatures");
 
     // Emit as { "cpu", "description", 0, { f1 , f2 , ... fn } },
     OS << " { "
        << "\"" << Name << "\", ";
 
     printFeatureMask(OS, FeatureList, FeatureMap);
-    OS << ", "; 
-    printFeatureMask(OS, TuneFeatureList, FeatureMap); 
+    OS << ", ";
+    printFeatureMask(OS, TuneFeatureList, FeatureMap);
 
     // Emit the scheduler model pointer.
     const std::string &ProcModelName =
@@ -730,8 +730,8 @@ void SubtargetEmitter::EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
   unsigned QueueID = 0;
   if (ProcModel.LoadQueue) {
     const Record *Queue = ProcModel.LoadQueue->getValueAsDef("QueueDescriptor");
-    QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(), 
-                                find(ProcModel.ProcResourceDefs, Queue)); 
+    QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(),
+                                find(ProcModel.ProcResourceDefs, Queue));
   }
   OS << "  " << QueueID << ", // Resource Descriptor for the Load Queue\n";
 
@@ -739,8 +739,8 @@ void SubtargetEmitter::EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
   if (ProcModel.StoreQueue) {
     const Record *Queue =
         ProcModel.StoreQueue->getValueAsDef("QueueDescriptor");
-    QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(), 
-                                find(ProcModel.ProcResourceDefs, Queue)); 
+    QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(),
+                                find(ProcModel.ProcResourceDefs, Queue));
   }
   OS << "  " << QueueID << ", // Resource Descriptor for the Store Queue\n";
 }
@@ -1003,7 +1003,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
     bool HasVariants = false;
     for (const CodeGenSchedTransition &CGT :
            make_range(SC.Transitions.begin(), SC.Transitions.end())) {
-      if (CGT.ProcIndex == ProcModel.Index) { 
+      if (CGT.ProcIndex == ProcModel.Index) {
         HasVariants = true;
         break;
       }
@@ -1216,8 +1216,8 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
     }
     else {
       SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size();
-      llvm::append_range(SchedTables.WriteLatencies, WriteLatencies); 
-      llvm::append_range(SchedTables.WriterNames, WriterNames); 
+      llvm::append_range(SchedTables.WriteLatencies, WriteLatencies);
+      llvm::append_range(SchedTables.WriterNames, WriterNames);
     }
     // ReadAdvanceEntries must remain in operand order.
     SCDesc.NumReadAdvanceEntries = ReadAdvanceEntries.size();
@@ -1229,7 +1229,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
       SCDesc.ReadAdvanceIdx = RAPos - SchedTables.ReadAdvanceEntries.begin();
     else {
       SCDesc.ReadAdvanceIdx = SchedTables.ReadAdvanceEntries.size();
-      llvm::append_range(SchedTables.ReadAdvanceEntries, ReadAdvanceEntries); 
+      llvm::append_range(SchedTables.ReadAdvanceEntries, ReadAdvanceEntries);
     }
   }
 }
@@ -1436,11 +1436,11 @@ static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) {
   OS << Buffer;
 }
 
-static bool isTruePredicate(const Record *Rec) { 
-  return Rec->isSubClassOf("MCSchedPredicate") && 
-         Rec->getValueAsDef("Pred")->isSubClassOf("MCTrue"); 
-} 
- 
+static bool isTruePredicate(const Record *Rec) {
+  return Rec->isSubClassOf("MCSchedPredicate") &&
+         Rec->getValueAsDef("Pred")->isSubClassOf("MCTrue");
+}
+
 static void emitPredicates(const CodeGenSchedTransition &T,
                            const CodeGenSchedClass &SC, PredicateExpander &PE,
                            raw_ostream &OS) {
@@ -1449,7 +1449,7 @@ static void emitPredicates(const CodeGenSchedTransition &T,
 
   // If not all predicates are MCTrue, then we need an if-stmt.
   unsigned NumNonTruePreds =
-      T.PredTerm.size() - count_if(T.PredTerm, isTruePredicate); 
+      T.PredTerm.size() - count_if(T.PredTerm, isTruePredicate);
 
   SS.indent(PE.getIndentLevel() * 2);
 
@@ -1461,7 +1461,7 @@ static void emitPredicates(const CodeGenSchedTransition &T,
 
     for (const Record *Rec : T.PredTerm) {
       // Skip predicates that evaluate to "true".
-      if (isTruePredicate(Rec)) 
+      if (isTruePredicate(Rec))
         continue;
 
       if (FirstNonTruePredicate) {
@@ -1497,8 +1497,8 @@ static void emitPredicates(const CodeGenSchedTransition &T,
 
 // Used by method `SubtargetEmitter::emitSchedModelHelpersImpl()` to generate
 // epilogue code for the auto-generated helper.
-static void emitSchedModelHelperEpilogue(raw_ostream &OS, 
-                                         bool ShouldReturnZero) { 
+static void emitSchedModelHelperEpilogue(raw_ostream &OS,
+                                         bool ShouldReturnZero) {
   if (ShouldReturnZero) {
     OS << "  // Don't know how to resolve this scheduling class.\n"
        << "  return 0;\n";
@@ -1508,15 +1508,15 @@ static void emitSchedModelHelperEpilogue(raw_ostream &OS,
   OS << "  report_fatal_error(\"Expected a variant SchedClass\");\n";
 }
 
-static bool hasMCSchedPredicates(const CodeGenSchedTransition &T) { 
+static bool hasMCSchedPredicates(const CodeGenSchedTransition &T) {
   return all_of(T.PredTerm, [](const Record *Rec) {
     return Rec->isSubClassOf("MCSchedPredicate");
   });
 }
 
-static void collectVariantClasses(const CodeGenSchedModels &SchedModels, 
-                                  IdxVec &VariantClasses, 
-                                  bool OnlyExpandMCInstPredicates) { 
+static void collectVariantClasses(const CodeGenSchedModels &SchedModels,
+                                  IdxVec &VariantClasses,
+                                  bool OnlyExpandMCInstPredicates) {
   for (const CodeGenSchedClass &SC : SchedModels.schedClasses()) {
     // Ignore non-variant scheduling classes.
     if (SC.Transitions.empty())
@@ -1535,24 +1535,24 @@ static void collectVariantClasses(const CodeGenSchedModels &SchedModels,
   }
 }
 
-static void collectProcessorIndices(const CodeGenSchedClass &SC, 
-                                    IdxVec &ProcIndices) { 
+static void collectProcessorIndices(const CodeGenSchedClass &SC,
+                                    IdxVec &ProcIndices) {
   // A variant scheduling class may define transitions for multiple
   // processors.  This function identifies wich processors are associated with
   // transition rules specified by variant class `SC`.
   for (const CodeGenSchedTransition &T : SC.Transitions) {
     IdxVec PI;
-    std::set_union(&T.ProcIndex, &T.ProcIndex + 1, ProcIndices.begin(), 
-                   ProcIndices.end(), std::back_inserter(PI)); 
+    std::set_union(&T.ProcIndex, &T.ProcIndex + 1, ProcIndices.begin(),
+                   ProcIndices.end(), std::back_inserter(PI));
     ProcIndices.swap(PI);
   }
 }
 
-static bool isAlwaysTrue(const CodeGenSchedTransition &T) { 
-  return llvm::all_of(T.PredTerm, 
-                      [](const Record *R) { return isTruePredicate(R); }); 
-} 
- 
+static bool isAlwaysTrue(const CodeGenSchedTransition &T) {
+  return llvm::all_of(T.PredTerm,
+                      [](const Record *R) { return isTruePredicate(R); });
+}
+
 void SubtargetEmitter::emitSchedModelHelpersImpl(
     raw_ostream &OS, bool OnlyExpandMCInstPredicates) {
   IdxVec VariantClasses;
@@ -1595,9 +1595,9 @@ void SubtargetEmitter::emitSchedModelHelpersImpl(
       }
 
       // Now emit transitions associated with processor PI.
-      const CodeGenSchedTransition *FinalT = nullptr; 
+      const CodeGenSchedTransition *FinalT = nullptr;
       for (const CodeGenSchedTransition &T : SC.Transitions) {
-        if (PI != 0 && T.ProcIndex != PI) 
+        if (PI != 0 && T.ProcIndex != PI)
           continue;
 
         // Emit only transitions based on MCSchedPredicate, if it's the case.
@@ -1610,17 +1610,17 @@ void SubtargetEmitter::emitSchedModelHelpersImpl(
         if (OnlyExpandMCInstPredicates && !hasMCSchedPredicates(T))
           continue;
 
-        // If transition is folded to 'return X' it should be the last one. 
-        if (isAlwaysTrue(T)) { 
-          FinalT = &T; 
-          continue; 
-        } 
+        // If transition is folded to 'return X' it should be the last one.
+        if (isAlwaysTrue(T)) {
+          FinalT = &T;
+          continue;
+        }
         PE.setIndentLevel(3);
         emitPredicates(T, SchedModels.getSchedClass(T.ToClassIdx), PE, OS);
       }
-      if (FinalT) 
-        emitPredicates(*FinalT, SchedModels.getSchedClass(FinalT->ToClassIdx), 
-                       PE, OS); 
+      if (FinalT)
+        emitPredicates(*FinalT, SchedModels.getSchedClass(FinalT->ToClassIdx),
+                       PE, OS);
 
       OS << "    }\n";
 
@@ -1654,9 +1654,9 @@ void SubtargetEmitter::EmitSchedModelHelpers(const std::string &ClassName,
 
   OS << "unsigned " << ClassName
      << "\n::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,"
-     << " const MCInstrInfo *MCII, unsigned CPUID) const {\n" 
+     << " const MCInstrInfo *MCII, unsigned CPUID) const {\n"
      << "  return " << Target << "_MC"
-     << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);\n" 
+     << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);\n"
      << "} // " << ClassName << "::resolveVariantSchedClass\n\n";
 
   STIPredicateExpander PE(Target);
@@ -1700,19 +1700,19 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
      << "// subtarget options.\n"
      << "void llvm::";
   OS << Target;
-  OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, " 
-     << "StringRef FS) {\n" 
+  OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, "
+     << "StringRef FS) {\n"
      << "  LLVM_DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"
-     << "  LLVM_DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n" 
-     << "  LLVM_DEBUG(dbgs() << \"\\nTuneCPU:\" << TuneCPU << \"\\n\\n\");\n"; 
+     << "  LLVM_DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n"
+     << "  LLVM_DEBUG(dbgs() << \"\\nTuneCPU:\" << TuneCPU << \"\\n\\n\");\n";
 
   if (Features.empty()) {
     OS << "}\n";
     return;
   }
 
-  OS << "  InitMCProcessorInfo(CPU, TuneCPU, FS);\n" 
-     << "  const FeatureBitset &Bits = getFeatureBits();\n"; 
+  OS << "  InitMCProcessorInfo(CPU, TuneCPU, FS);\n"
+     << "  const FeatureBitset &Bits = getFeatureBits();\n";
 
   for (Record *R : Features) {
     // Next record
@@ -1737,28 +1737,28 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
 void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
   OS << "namespace " << Target << "_MC {\n"
      << "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,\n"
-     << "    const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {\n"; 
+     << "    const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {\n";
   emitSchedModelHelpersImpl(OS, /* OnlyExpandMCPredicates */ true);
   OS << "}\n";
   OS << "} // end namespace " << Target << "_MC\n\n";
 
   OS << "struct " << Target
      << "GenMCSubtargetInfo : public MCSubtargetInfo {\n";
-  OS << "  " << Target << "GenMCSubtargetInfo(const Triple &TT,\n" 
-     << "    StringRef CPU, StringRef TuneCPU, StringRef FS,\n" 
-     << "    ArrayRef<SubtargetFeatureKV> PF,\n" 
+  OS << "  " << Target << "GenMCSubtargetInfo(const Triple &TT,\n"
+     << "    StringRef CPU, StringRef TuneCPU, StringRef FS,\n"
+     << "    ArrayRef<SubtargetFeatureKV> PF,\n"
      << "    ArrayRef<SubtargetSubTypeKV> PD,\n"
      << "    const MCWriteProcResEntry *WPR,\n"
      << "    const MCWriteLatencyEntry *WL,\n"
      << "    const MCReadAdvanceEntry *RA, const InstrStage *IS,\n"
      << "    const unsigned *OC, const unsigned *FP) :\n"
-     << "      MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,\n" 
+     << "      MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,\n"
      << "                      WPR, WL, RA, IS, OC, FP) { }\n\n"
      << "  unsigned resolveVariantSchedClass(unsigned SchedClass,\n"
-     << "      const MCInst *MI, const MCInstrInfo *MCII,\n" 
-     << "      unsigned CPUID) const override {\n" 
+     << "      const MCInst *MI, const MCInstrInfo *MCII,\n"
+     << "      unsigned CPUID) const override {\n"
      << "    return " << Target << "_MC"
-     << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);\n"; 
+     << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);\n";
   OS << "  }\n";
   if (TGT.getHwModes().getNumModeIds() > 1)
     OS << "  unsigned getHwMode() const override;\n";
@@ -1829,9 +1829,9 @@ void SubtargetEmitter::run(raw_ostream &OS) {
 
   OS << "\nstatic inline MCSubtargetInfo *create" << Target
      << "MCSubtargetInfoImpl("
-     << "const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {\n"; 
-  OS << "  return new " << Target 
-     << "GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, "; 
+     << "const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {\n";
+  OS << "  return new " << Target
+     << "GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, ";
   if (NumFeatures)
     OS << Target << "FeatureKV, ";
   else
@@ -1875,18 +1875,18 @@ void SubtargetEmitter::run(raw_ostream &OS) {
   OS << "class DFAPacketizer;\n";
   OS << "namespace " << Target << "_MC {\n"
      << "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,"
-     << " const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);\n" 
+     << " const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);\n"
      << "} // end namespace " << Target << "_MC\n\n";
   OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
      << "  explicit " << ClassName << "(const Triple &TT, StringRef CPU, "
-     << "StringRef TuneCPU, StringRef FS);\n" 
+     << "StringRef TuneCPU, StringRef FS);\n"
      << "public:\n"
      << "  unsigned resolveSchedClass(unsigned SchedClass, "
      << " const MachineInstr *DefMI,"
      << " const TargetSchedModel *SchedModel) const override;\n"
      << "  unsigned resolveVariantSchedClass(unsigned SchedClass,"
-     << " const MCInst *MI, const MCInstrInfo *MCII," 
-     << " unsigned CPUID) const override;\n" 
+     << " const MCInst *MI, const MCInstrInfo *MCII,"
+     << " unsigned CPUID) const override;\n"
      << "  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
      << " const;\n";
   if (TGT.getHwModes().getNumModeIds() > 1)
@@ -1923,8 +1923,8 @@ void SubtargetEmitter::run(raw_ostream &OS) {
   }
 
   OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, "
-     << "StringRef TuneCPU, StringRef FS)\n" 
-     << "  : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, "; 
+     << "StringRef TuneCPU, StringRef FS)\n"
+     << "  : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ";
   if (NumFeatures)
     OS << "makeArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";
   else
diff --git a/contrib/libs/llvm12/utils/TableGen/SubtargetFeatureInfo.cpp b/contrib/libs/llvm12/utils/TableGen/SubtargetFeatureInfo.cpp
index b8ed4e97a0..105ed82c9d 100644
--- a/contrib/libs/llvm12/utils/TableGen/SubtargetFeatureInfo.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/SubtargetFeatureInfo.cpp
@@ -9,7 +9,7 @@
 #include "SubtargetFeatureInfo.h"
 #include "Types.h"
 #include "llvm/Config/llvm-config.h"
-#include "llvm/TableGen/Error.h" 
+#include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
 #include <map>
 
@@ -112,7 +112,7 @@ void SubtargetFeatureInfo::emitComputeAssemblerAvailableFeatures(
     StringRef TargetName, StringRef ClassName, StringRef FuncName,
     SubtargetFeatureInfoMap &SubtargetFeatures, raw_ostream &OS) {
   OS << "FeatureBitset " << TargetName << ClassName << "::\n"
-     << FuncName << "(const FeatureBitset &FB) const {\n"; 
+     << FuncName << "(const FeatureBitset &FB) const {\n";
   OS << "  FeatureBitset Features;\n";
   for (const auto &SF : SubtargetFeatures) {
     const SubtargetFeatureInfo &SFI = SF.second;
diff --git a/contrib/libs/llvm12/utils/TableGen/TableGen.cpp b/contrib/libs/llvm12/utils/TableGen/TableGen.cpp
index d514e00c6c..6d851da347 100644
--- a/contrib/libs/llvm12/utils/TableGen/TableGen.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/TableGen.cpp
@@ -12,7 +12,7 @@
 
 #include "TableGenBackends.h" // Declares all backends.
 #include "llvm/Support/CommandLine.h"
-#include "llvm/Support/InitLLVM.h" 
+#include "llvm/Support/InitLLVM.h"
 #include "llvm/TableGen/Main.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/SetTheory.h"
@@ -21,8 +21,8 @@ using namespace llvm;
 
 enum ActionType {
   PrintRecords,
-  PrintDetailedRecords, 
-  NullBackend, 
+  PrintDetailedRecords,
+  NullBackend,
   DumpJSON,
   GenEmitter,
   GenRegisterInfo,
@@ -74,10 +74,10 @@ cl::opt<ActionType> Action(
     cl::values(
         clEnumValN(PrintRecords, "print-records",
                    "Print all records to stdout (default)"),
-        clEnumValN(PrintDetailedRecords, "print-detailed-records", 
-                   "Print full details of all records to stdout"), 
-        clEnumValN(NullBackend, "null-backend", 
-                   "Do nothing after parsing (useful for timing)"), 
+        clEnumValN(PrintDetailedRecords, "print-detailed-records",
+                   "Print full details of all records to stdout"),
+        clEnumValN(NullBackend, "null-backend",
+                   "Do nothing after parsing (useful for timing)"),
         clEnumValN(DumpJSON, "dump-json",
                    "Dump all records as machine-readable JSON"),
         clEnumValN(GenEmitter, "gen-emitter", "Generate machine code emitter"),
@@ -148,13 +148,13 @@ cl::opt<std::string> Class("class", cl::desc("Print Enum list for this class"),
 bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
   switch (Action) {
   case PrintRecords:
-    OS << Records;              // No argument, dump all contents 
+    OS << Records;              // No argument, dump all contents
+    break;
+  case PrintDetailedRecords:
+    EmitDetailedRecords(Records, OS);
+    break;
+  case NullBackend:             // No backend at all.
     break;
-  case PrintDetailedRecords: 
-    EmitDetailedRecords(Records, OS); 
-    break; 
-  case NullBackend:             // No backend at all. 
-    break; 
   case DumpJSON:
     EmitJSON(Records, OS);
     break;
@@ -279,7 +279,7 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
 }
 
 int main(int argc, char **argv) {
-  InitLLVM X(argc, argv); 
+  InitLLVM X(argc, argv);
   cl::ParseCommandLineOptions(argc, argv);
 
   return TableGenMain(argv[0], &LLVMTableGenMain);
diff --git a/contrib/libs/llvm12/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
index 803cd12abc..7518b262e6 100644
--- a/contrib/libs/llvm12/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
@@ -39,15 +39,15 @@ void emitWebAssemblyDisassemblerTables(
             ->getValue());
     if (Opc == 0xFFFFFFFF)
       continue; // No opcode defined.
-    assert(Opc <= 0xFFFFFF); 
-    unsigned Prefix; 
-    if (Opc <= 0xFFFF) { 
-      Prefix = Opc >> 8; 
-      Opc = Opc & 0xFF; 
-    } else { 
-      Prefix = Opc >> 16; 
-      Opc = Opc & 0xFFFF; 
-    } 
+    assert(Opc <= 0xFFFFFF);
+    unsigned Prefix;
+    if (Opc <= 0xFFFF) {
+      Prefix = Opc >> 8;
+      Opc = Opc & 0xFF;
+    } else {
+      Prefix = Opc >> 16;
+      Opc = Opc & 0xFFFF;
+    }
     auto &CGIP = OpcodeTable[Prefix][Opc];
     // All wasm instructions have a StackBased field of type string, we only
     // want the instructions for which this is "true".
@@ -139,7 +139,7 @@ void emitWebAssemblyDisassemblerTables(
         }
         // Store operands if no prior occurrence.
         if (OperandStart == OperandTable.size()) {
-          llvm::append_range(OperandTable, CurOperandList); 
+          llvm::append_range(OperandTable, CurOperandList);
         }
         OS << OperandStart;
       } else {
diff --git a/contrib/libs/llvm12/utils/TableGen/X86DisassemblerTables.cpp b/contrib/libs/llvm12/utils/TableGen/X86DisassemblerTables.cpp
index fa103849a6..331664f875 100644
--- a/contrib/libs/llvm12/utils/TableGen/X86DisassemblerTables.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/X86DisassemblerTables.cpp
@@ -763,7 +763,7 @@ void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
   }
   if (index == 256) {
     // If all 256 entries are MODRM_ONEENTRY, omit output.
-    static_assert(MODRM_ONEENTRY == 0, ""); 
+    static_assert(MODRM_ONEENTRY == 0, "");
     --i2;
     o2 << "},\n";
   } else {
diff --git a/contrib/libs/llvm12/utils/TableGen/X86FoldTablesEmitter.cpp b/contrib/libs/llvm12/utils/TableGen/X86FoldTablesEmitter.cpp
index f6e80751f6..85d9262151 100644
--- a/contrib/libs/llvm12/utils/TableGen/X86FoldTablesEmitter.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/X86FoldTablesEmitter.cpp
@@ -127,15 +127,15 @@ class X86FoldTablesEmitter {
 
       OS << "0 },\n";
     }
- 
-    bool operator<(const X86FoldTableEntry &RHS) const { 
-      bool LHSpseudo = RegInst->TheDef->getValueAsBit("isPseudo"); 
-      bool RHSpseudo = RHS.RegInst->TheDef->getValueAsBit("isPseudo"); 
-      if (LHSpseudo != RHSpseudo) 
-        return LHSpseudo; 
- 
-      return RegInst->TheDef->getName() < RHS.RegInst->TheDef->getName(); 
-    } 
+
+    bool operator<(const X86FoldTableEntry &RHS) const {
+      bool LHSpseudo = RegInst->TheDef->getValueAsBit("isPseudo");
+      bool RHSpseudo = RHS.RegInst->TheDef->getValueAsBit("isPseudo");
+      if (LHSpseudo != RHSpseudo)
+        return LHSpseudo;
+
+      return RegInst->TheDef->getName() < RHS.RegInst->TheDef->getName();
+    }
   };
 
   typedef std::vector<X86FoldTableEntry> FoldTable;
@@ -234,7 +234,7 @@ static inline unsigned int getRegOperandSize(const Record *RegRec) {
 }
 
 // Return the size of the memory operand
-static inline unsigned getMemOperandSize(const Record *MemRec) { 
+static inline unsigned getMemOperandSize(const Record *MemRec) {
   if (MemRec->isSubClassOf("Operand")) {
     StringRef Name =
         MemRec->getValueAsDef("ParserMatchClass")->getValueAsString("Name");
@@ -654,14 +654,14 @@ void X86FoldTablesEmitter::run(formatted_raw_ostream &OS) {
                  &(Target.getInstruction(MemInstIter)), Entry.Strategy);
   }
 
-  // Sort the tables before printing. 
-  llvm::sort(Table2Addr); 
-  llvm::sort(Table0); 
-  llvm::sort(Table1); 
-  llvm::sort(Table2); 
-  llvm::sort(Table3); 
-  llvm::sort(Table4); 
- 
+  // Sort the tables before printing.
+  llvm::sort(Table2Addr);
+  llvm::sort(Table0);
+  llvm::sort(Table1);
+  llvm::sort(Table2);
+  llvm::sort(Table3);
+  llvm::sort(Table4);
+
   // Print all tables.
   printTable(Table2Addr, "Table2Addr", OS);
   printTable(Table0, "Table0", OS);
diff --git a/contrib/libs/llvm12/utils/TableGen/X86RecognizableInstr.cpp b/contrib/libs/llvm12/utils/TableGen/X86RecognizableInstr.cpp
index 0d1c7a32b2..e4b7c05cfb 100644
--- a/contrib/libs/llvm12/utils/TableGen/X86RecognizableInstr.cpp
+++ b/contrib/libs/llvm12/utils/TableGen/X86RecognizableInstr.cpp
@@ -54,7 +54,7 @@ static uint8_t byteFromBitsInit(BitsInit &init) {
 /// @param rec  - The record from which to extract the value.
 /// @param name - The name of the field in the record.
 /// @return     - The field, as translated by byteFromBitsInit().
-static uint8_t byteFromRec(const Record* rec, StringRef name) { 
+static uint8_t byteFromRec(const Record* rec, StringRef name) {
   BitsInit* bits = rec->getValueAsBitsInit(name);
   return byteFromBitsInit(*bits);
 }
diff --git a/contrib/libs/llvm12/utils/TableGen/ya.make b/contrib/libs/llvm12/utils/TableGen/ya.make
index d93e2ce27c..69c2241a4d 100644
--- a/contrib/libs/llvm12/utils/TableGen/ya.make
+++ b/contrib/libs/llvm12/utils/TableGen/ya.make
@@ -12,11 +12,11 @@ LICENSE(Apache-2.0 WITH LLVM-exception)
 LICENSE_TEXTS(.yandex_meta/licenses.list.txt)
 
 PEERDIR(
-    contrib/libs/llvm12 
-    contrib/libs/llvm12/lib/Demangle 
-    contrib/libs/llvm12/lib/Support 
-    contrib/libs/llvm12/lib/TableGen 
-    contrib/libs/llvm12/utils/TableGen/GlobalISel 
+    contrib/libs/llvm12
+    contrib/libs/llvm12/lib/Demangle
+    contrib/libs/llvm12/lib/Support
+    contrib/libs/llvm12/lib/TableGen
+    contrib/libs/llvm12/utils/TableGen/GlobalISel
 )
 
 ADDINCL(