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author | shadchin <shadchin@yandex-team.ru> | 2022-02-10 16:44:30 +0300 |
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committer | Daniil Cherednik <dcherednik@yandex-team.ru> | 2022-02-10 16:44:30 +0300 |
commit | 2598ef1d0aee359b4b6d5fdd1758916d5907d04f (patch) | |
tree | 012bb94d777798f1f56ac1cec429509766d05181 /contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td | |
parent | 6751af0b0c1b952fede40b19b71da8025b5d8bcf (diff) | |
download | ydb-2598ef1d0aee359b4b6d5fdd1758916d5907d04f.tar.gz |
Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 1 of 2.
Diffstat (limited to 'contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td')
-rw-r--r-- | contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td | 78 |
1 files changed, 39 insertions, 39 deletions
diff --git a/contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td b/contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td index 8d7cd60820..e21028c8a3 100644 --- a/contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td +++ b/contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td @@ -1,39 +1,39 @@ -//===- X86InstrTDX.td - TDX Instruction Set Extension -*- tablegen -*===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file describes the instructions that make up the Intel TDX instruction -// set. -// -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// TDX instructions - -// 64-bit only instructions -let SchedRW = [WriteSystem], Predicates = [In64BitMode] in { -// SEAMCALL - Call to SEAM VMX-root Operation Module -def SEAMCALL : I<0x01, MRM_CF, (outs), (ins), - "seamcall", []>, PD; - -// SEAMRET - Return to Legacy VMX-root Operation -def SEAMRET : I<0x01, MRM_CD, (outs), (ins), - "seamret", []>, PD; - -// SEAMOPS - SEAM Operations -def SEAMOPS : I<0x01, MRM_CE, (outs), (ins), - "seamops", []>, PD; - -} // SchedRW - -// common instructions -let SchedRW = [WriteSystem] in { -// TDCALL - Call SEAM Module Functions -def TDCALL : I<0x01, MRM_CC, (outs), (ins), - "tdcall", []>, PD; - -} // SchedRW +//===- X86InstrTDX.td - TDX Instruction Set Extension -*- tablegen -*===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the instructions that make up the Intel TDX instruction +// set. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// TDX instructions + +// 64-bit only instructions +let SchedRW = [WriteSystem], Predicates = [In64BitMode] in { +// SEAMCALL - Call to SEAM VMX-root Operation Module +def SEAMCALL : I<0x01, MRM_CF, (outs), (ins), + "seamcall", []>, PD; + +// SEAMRET - Return to Legacy VMX-root Operation +def SEAMRET : I<0x01, MRM_CD, (outs), (ins), + "seamret", []>, PD; + +// SEAMOPS - SEAM Operations +def SEAMOPS : I<0x01, MRM_CE, (outs), (ins), + "seamops", []>, PD; + +} // SchedRW + +// common instructions +let SchedRW = [WriteSystem] in { +// TDCALL - Call SEAM Module Functions +def TDCALL : I<0x01, MRM_CC, (outs), (ins), + "tdcall", []>, PD; + +} // SchedRW |