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| author | shadchin <shadchin@yandex-team.ru> | 2022-02-10 16:44:39 +0300 |
|---|---|---|
| committer | Daniil Cherednik <dcherednik@yandex-team.ru> | 2022-02-10 16:44:39 +0300 |
| commit | e9656aae26e0358d5378e5b63dcac5c8dbe0e4d0 (patch) | |
| tree | 64175d5cadab313b3e7039ebaa06c5bc3295e274 /contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td | |
| parent | 2598ef1d0aee359b4b6d5fdd1758916d5907d04f (diff) | |
| download | ydb-e9656aae26e0358d5378e5b63dcac5c8dbe0e4d0.tar.gz | |
Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 2 of 2.
Diffstat (limited to 'contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td')
| -rw-r--r-- | contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td b/contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td index 23cec4e363..686b19fc0a 100644 --- a/contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td +++ b/contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td @@ -216,7 +216,7 @@ class T8XS : T8 { Prefix OpPrefix = XS; } class TAPS : TA { Prefix OpPrefix = PS; } class TAPD : TA { Prefix OpPrefix = PD; } class TAXD : TA { Prefix OpPrefix = XD; } -class TAXS : TA { Prefix OpPrefix = XS; } +class TAXS : TA { Prefix OpPrefix = XS; } class VEX { Encoding OpEnc = EncVEX; } class VEX_W { bit HasVEX_W = 1; } class VEX_WIG { bit IgnoresVEX_W = 1; } @@ -264,9 +264,9 @@ class NotMemoryFoldable { bit isMemoryFoldable = 0; } // Prevent EVEX->VEX conversion from considering this instruction. class NotEVEX2VEXConvertible { bit notEVEX2VEXConvertible = 1; } -// Force the instruction to use VEX encoding. -class ExplicitVEXPrefix { bit ExplicitVEXPrefix = 1; } - +// Force the instruction to use VEX encoding. +class ExplicitVEXPrefix { bit ExplicitVEXPrefix = 1; } + class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins, string AsmStr, Domain d = GenericDomain> : Instruction { @@ -351,7 +351,7 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins, bit isMemoryFoldable = 1; // Is it allowed to memory fold/unfold this instruction? bit notEVEX2VEXConvertible = 0; // Prevent EVEX->VEX conversion. - bit ExplicitVEXPrefix = 0; // Force the instruction to use VEX encoding. + bit ExplicitVEXPrefix = 0; // Force the instruction to use VEX encoding. // TSFlags layout should be kept in sync with X86BaseInfo.h. let TSFlags{6-0} = FormBits; @@ -380,7 +380,7 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins, let TSFlags{51-45} = CD8_Scale; let TSFlags{52} = hasEVEX_RC; let TSFlags{53} = hasNoTrackPrefix; - let TSFlags{54} = ExplicitVEXPrefix; + let TSFlags{54} = ExplicitVEXPrefix; } class PseudoI<dag oops, dag iops, list<dag> pattern> |