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author | shadchin <shadchin@yandex-team.ru> | 2022-02-10 16:44:30 +0300 |
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committer | Daniil Cherednik <dcherednik@yandex-team.ru> | 2022-02-10 16:44:30 +0300 |
commit | 2598ef1d0aee359b4b6d5fdd1758916d5907d04f (patch) | |
tree | 012bb94d777798f1f56ac1cec429509766d05181 /contrib/libs/llvm12/lib/Target/X86/X86FixupSetCC.cpp | |
parent | 6751af0b0c1b952fede40b19b71da8025b5d8bcf (diff) | |
download | ydb-2598ef1d0aee359b4b6d5fdd1758916d5907d04f.tar.gz |
Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 1 of 2.
Diffstat (limited to 'contrib/libs/llvm12/lib/Target/X86/X86FixupSetCC.cpp')
-rw-r--r-- | contrib/libs/llvm12/lib/Target/X86/X86FixupSetCC.cpp | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/contrib/libs/llvm12/lib/Target/X86/X86FixupSetCC.cpp b/contrib/libs/llvm12/lib/Target/X86/X86FixupSetCC.cpp index 269f8ce6bd..a46da8aa48 100644 --- a/contrib/libs/llvm12/lib/Target/X86/X86FixupSetCC.cpp +++ b/contrib/libs/llvm12/lib/Target/X86/X86FixupSetCC.cpp @@ -101,24 +101,24 @@ bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) { const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit() ? &X86::GR32RegClass : &X86::GR32_ABCDRegClass; - if (!MRI->constrainRegClass(ZExt->getOperand(0).getReg(), RC)) { - // If we cannot constrain the register, we would need an additional copy - // and are better off keeping the MOVZX32rr8 we have now. - continue; - } - - ++NumSubstZexts; - Changed = true; - + if (!MRI->constrainRegClass(ZExt->getOperand(0).getReg(), RC)) { + // If we cannot constrain the register, we would need an additional copy + // and are better off keeping the MOVZX32rr8 we have now. + continue; + } + + ++NumSubstZexts; + Changed = true; + // Initialize a register with 0. This must go before the eflags def - Register ZeroReg = MRI->createVirtualRegister(RC); + Register ZeroReg = MRI->createVirtualRegister(RC); BuildMI(MBB, FlagsDefMI, MI.getDebugLoc(), TII->get(X86::MOV32r0), ZeroReg); // X86 setcc only takes an output GR8, so fake a GR32 input by inserting // the setcc result into the low byte of the zeroed register. BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(), - TII->get(X86::INSERT_SUBREG), ZExt->getOperand(0).getReg()) + TII->get(X86::INSERT_SUBREG), ZExt->getOperand(0).getReg()) .addReg(ZeroReg) .addReg(MI.getOperand(0).getReg()) .addImm(X86::sub_8bit); |