Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 1 of 2.

1 files changed, 66 insertions, 66 deletions

diff --git a/contrib/libs/llvm12/lib/Target/PowerPC/PPCTargetMachine.cpp b/contrib/libs/llvm12/lib/Target/PowerPC/PPCTargetMachine.cpp
index 0634833e64..d9ffab3ceb 100644
--- a/contrib/libs/llvm12/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/contrib/libs/llvm12/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -24,18 +24,18 @@
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
-#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
-#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
-#include "llvm/CodeGen/GlobalISel/Legalizer.h"
-#include "llvm/CodeGen/GlobalISel/Localizer.h"
-#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
-#include "llvm/CodeGen/MachineScheduler.h"
+#include "llvm/CodeGen/GlobalISel/IRTranslator.h" 
+#include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 
+#include "llvm/CodeGen/GlobalISel/Legalizer.h" 
+#include "llvm/CodeGen/GlobalISel/Localizer.h" 
+#include "llvm/CodeGen/GlobalISel/RegBankSelect.h" 
+#include "llvm/CodeGen/MachineScheduler.h" 
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/Attributes.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Function.h"
-#include "llvm/InitializePasses.h"
+#include "llvm/InitializePasses.h" 
 #include "llvm/Pass.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/CommandLine.h"
@@ -100,9 +100,9 @@ static cl::opt<bool>
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() {
   // Register the targets
   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
-  RegisterTargetMachine<PPCTargetMachine> B(getThePPC32LETarget());
-  RegisterTargetMachine<PPCTargetMachine> C(getThePPC64Target());
-  RegisterTargetMachine<PPCTargetMachine> D(getThePPC64LETarget());
+  RegisterTargetMachine<PPCTargetMachine> B(getThePPC32LETarget()); 
+  RegisterTargetMachine<PPCTargetMachine> C(getThePPC64Target()); 
+  RegisterTargetMachine<PPCTargetMachine> D(getThePPC64LETarget()); 
 
   PassRegistry &PR = *PassRegistry::getPassRegistry();
 #ifndef NDEBUG
@@ -123,7 +123,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() {
   initializePPCTLSDynamicCallPass(PR);
   initializePPCMIPeepholePass(PR);
   initializePPCLowerMASSVEntriesPass(PR);
-  initializeGlobalISel(PR);
+  initializeGlobalISel(PR); 
 }
 
 /// Return the datalayout string of a subtarget.
@@ -131,8 +131,8 @@ static std::string getDataLayoutString(const Triple &T) {
   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
   std::string Ret;
 
-  // Most PPC* platforms are big endian, PPC(64)LE is little endian.
-  if (T.getArch() == Triple::ppc64le || T.getArch() == Triple::ppcle)
+  // Most PPC* platforms are big endian, PPC(64)LE is little endian. 
+  if (T.getArch() == Triple::ppc64le || T.getArch() == Triple::ppcle) 
     Ret = "e";
   else
     Ret = "E";
@@ -146,7 +146,7 @@ static std::string getDataLayoutString(const Triple &T) {
 
   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
   // documentation are wrong; these are correct (i.e. "what gcc does").
-  Ret += "-i64:64";
+  Ret += "-i64:64"; 
 
   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
   if (is64Bit)
@@ -154,13 +154,13 @@ static std::string getDataLayoutString(const Triple &T) {
   else
     Ret += "-n32";
 
-  // Specify the vector alignment explicitly. For v256i1 and v512i1, the
-  // calculated alignment would be 256*alignment(i1) and 512*alignment(i1),
-  // which is 256 and 512 bytes - way over aligned.
-  if ((T.getArch() == Triple::ppc64le || T.getArch() == Triple::ppc64) &&
-      (T.isOSAIX() || T.isOSLinux()))
-    Ret += "-v256:256:256-v512:512:512";
-
+  // Specify the vector alignment explicitly. For v256i1 and v512i1, the 
+  // calculated alignment would be 256*alignment(i1) and 512*alignment(i1), 
+  // which is 256 and 512 bytes - way over aligned. 
+  if ((T.getArch() == Triple::ppc64le || T.getArch() == Triple::ppc64) && 
+      (T.isOSAIX() || T.isOSLinux())) 
+    Ret += "-v256:256:256-v512:512:512"; 
+ 
   return Ret;
 }
 
@@ -190,13 +190,13 @@ static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
       FullFS = "+invariant-function-descriptors";
   }
 
-  if (TT.isOSAIX()) {
-    if (!FullFS.empty())
-      FullFS = "+aix," + FullFS;
-    else
-      FullFS = "+aix";
-  }
-
+  if (TT.isOSAIX()) { 
+    if (!FullFS.empty()) 
+      FullFS = "+aix," + FullFS; 
+    else 
+      FullFS = "+aix"; 
+  } 
+ 
   return FullFS;
 }
 
@@ -280,8 +280,8 @@ static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
                           std::make_unique<GenericScheduler>(C));
   // add DAG Mutations here.
   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
-  if (ST.hasStoreFusion())
-    DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
+  if (ST.hasStoreFusion()) 
+    DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); 
   if (ST.hasFusion())
     DAG->addMutation(createPowerPCMacroFusionDAGMutation());
 
@@ -296,8 +296,8 @@ static ScheduleDAGInstrs *createPPCPostMachineScheduler(
                       std::make_unique<PPCPostRASchedStrategy>(C) :
                       std::make_unique<PostGenericScheduler>(C), true);
   // add DAG Mutations here.
-  if (ST.hasStoreFusion())
-    DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
+  if (ST.hasStoreFusion()) 
+    DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); 
   if (ST.hasFusion())
     DAG->addMutation(createPowerPCMacroFusionDAGMutation());
   return DAG;
@@ -329,10 +329,10 @@ PPCTargetMachine::getSubtargetImpl(const Function &F) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");
 
-  std::string CPU =
-      CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
-  std::string FS =
-      FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
+  std::string CPU = 
+      CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; 
+  std::string FS = 
+      FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; 
 
   // FIXME: This is related to the code below to reset the target options,
   // we need to know whether or not the soft float flag is set on the
@@ -394,12 +394,12 @@ public:
   void addPreRegAlloc() override;
   void addPreSched2() override;
   void addPreEmitPass() override;
-  // GlobalISEL
-  bool addIRTranslator() override;
-  bool addLegalizeMachineIR() override;
-  bool addRegBankSelect() override;
-  bool addGlobalInstructionSelect() override;
-
+  // GlobalISEL 
+  bool addIRTranslator() override; 
+  bool addLegalizeMachineIR() override; 
+  bool addRegBankSelect() override; 
+  bool addGlobalInstructionSelect() override; 
+ 
   ScheduleDAGInstrs *
   createMachineScheduler(MachineSchedContext *C) const override {
     return createPPCMachineScheduler(C);
@@ -423,8 +423,8 @@ void PPCPassConfig::addIRPasses() {
 
   // Lower generic MASSV routines to PowerPC subtarget-specific entries.
   addPass(createPPCLowerMASSVEntriesPass());
-
-  // If explicitly requested, add explicit data prefetch intrinsics.
+ 
+  // If explicitly requested, add explicit data prefetch intrinsics. 
   if (EnablePrefetch.getNumOccurrences() > 0)
     addPass(createLoopDataPrefetchPass());
 
@@ -522,7 +522,7 @@ void PPCPassConfig::addPreRegAlloc() {
 }
 
 void PPCPassConfig::addPreSched2() {
-  if (getOptLevel() != CodeGenOpt::None)
+  if (getOptLevel() != CodeGenOpt::None) 
     addPass(&IfConverterID);
 }
 
@@ -550,24 +550,24 @@ static MachineSchedRegistry
 PPCPostRASchedRegistry("ppc-postra",
                        "Run PowerPC PostRA specific scheduler",
                        createPPCPostMachineScheduler);
-
-// Global ISEL
-bool PPCPassConfig::addIRTranslator() {
-  addPass(new IRTranslator());
-  return false;
-}
-
-bool PPCPassConfig::addLegalizeMachineIR() {
-  addPass(new Legalizer());
-  return false;
-}
-
-bool PPCPassConfig::addRegBankSelect() {
-  addPass(new RegBankSelect());
-  return false;
-}
-
-bool PPCPassConfig::addGlobalInstructionSelect() {
-  addPass(new InstructionSelect());
-  return false;
-}
+ 
+// Global ISEL 
+bool PPCPassConfig::addIRTranslator() { 
+  addPass(new IRTranslator()); 
+  return false; 
+} 
+ 
+bool PPCPassConfig::addLegalizeMachineIR() { 
+  addPass(new Legalizer()); 
+  return false; 
+} 
+ 
+bool PPCPassConfig::addRegBankSelect() { 
+  addPass(new RegBankSelect()); 
+  return false; 
+} 
+ 
+bool PPCPassConfig::addGlobalInstructionSelect() { 
+  addPass(new InstructionSelect()); 
+  return false; 
+}