Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 1 of 2.

8 files changed, 188 insertions, 188 deletions

diff --git a/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h b/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
index 8459b4ff2a..07376848c4 100644
--- a/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
+++ b/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
@@ -205,20 +205,20 @@ namespace ARM_AM {
     return V;
   }
 
-  /// isSOImmTwoPartValNeg - Return true if the specified value can be obtained
-  /// by two SOImmVal, that -V = First + Second.
-  /// "R+V" can be optimized to (sub (sub R, First), Second).
-  /// "R=V" can be optimized to (sub (mvn R, ~(-First)), Second).
-  inline bool isSOImmTwoPartValNeg(unsigned V) {
-    unsigned First;
-    if (!isSOImmTwoPartVal(-V))
-      return false;
-    // Return false if ~(-First) is not a SoImmval.
-    First = getSOImmTwoPartFirst(-V);
-    First = ~(-First);
-    return !(rotr32(~255U, getSOImmValRotate(First)) & First);
-  }
-
+  /// isSOImmTwoPartValNeg - Return true if the specified value can be obtained 
+  /// by two SOImmVal, that -V = First + Second. 
+  /// "R+V" can be optimized to (sub (sub R, First), Second). 
+  /// "R=V" can be optimized to (sub (mvn R, ~(-First)), Second). 
+  inline bool isSOImmTwoPartValNeg(unsigned V) { 
+    unsigned First; 
+    if (!isSOImmTwoPartVal(-V)) 
+      return false; 
+    // Return false if ~(-First) is not a SoImmval. 
+    First = getSOImmTwoPartFirst(-V); 
+    First = ~(-First); 
+    return !(rotr32(~255U, getSOImmValRotate(First)) & First); 
+  } 
+ 
   /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
   /// by a left shift. Returns the shift amount to use.
   inline unsigned getThumbImmValShift(unsigned Imm) {
@@ -687,18 +687,18 @@ namespace ARM_AM {
     return getFP16Imm(FPImm.bitcastToAPInt());
   }
 
-  /// If this is a FP16Imm encoded as a fp32 value, return the 8-bit encoding
-  /// for it. Otherwise return -1 like getFP16Imm.
-  inline int getFP32FP16Imm(const APInt &Imm) {
-    if (Imm.getActiveBits() > 16)
-      return -1;
-    return ARM_AM::getFP16Imm(Imm.trunc(16));
-  }
-
-  inline int getFP32FP16Imm(const APFloat &FPImm) {
-    return getFP32FP16Imm(FPImm.bitcastToAPInt());
-  }
-
+  /// If this is a FP16Imm encoded as a fp32 value, return the 8-bit encoding 
+  /// for it. Otherwise return -1 like getFP16Imm. 
+  inline int getFP32FP16Imm(const APInt &Imm) { 
+    if (Imm.getActiveBits() > 16) 
+      return -1; 
+    return ARM_AM::getFP16Imm(Imm.trunc(16)); 
+  } 
+ 
+  inline int getFP32FP16Imm(const APFloat &FPImm) { 
+    return getFP32FP16Imm(FPImm.bitcastToAPInt()); 
+  } 
+ 
   /// getFP32Imm - Return an 8-bit floating-point version of the 32-bit
   /// floating-point value. If the value cannot be represented as an 8-bit
   /// floating-point value, then return -1.
diff --git a/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index b02aef3c33..697eeab4e5 100644
--- a/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -1010,7 +1010,7 @@ static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
   case ARM::fixup_t2_condbranch:
   case ARM::fixup_t2_uncondbranch:
   case ARM::fixup_t2_pcrel_10:
-  case ARM::fixup_t2_pcrel_9:
+  case ARM::fixup_t2_pcrel_9: 
   case ARM::fixup_t2_adr_pcrel_12:
   case ARM::fixup_arm_thumb_bl:
   case ARM::fixup_arm_thumb_blx:
diff --git a/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h b/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
index ecd96114e8..5599eaaf2f 100644
--- a/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
+++ b/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
@@ -254,7 +254,7 @@ namespace ARMII {
     MO_OPTION_MASK = 0x3,
 
     /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
-    /// reference is actually to the ".refptr.FOO" symbol.  This is used for
+    /// reference is actually to the ".refptr.FOO" symbol.  This is used for 
     /// stub symbols on windows.
     MO_COFFSTUB = 0x4,
 
diff --git a/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h b/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
index d975d799e0..ac75bf3fca 100644
--- a/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
+++ b/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
@@ -30,7 +30,7 @@ public:
   void printRegName(raw_ostream &OS, unsigned RegNo) const override;
 
   // Autogenerated by tblgen.
-  std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
+  std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; 
   void printInstruction(const MCInst *MI, uint64_t Address,
                         const MCSubtargetInfo &STI, raw_ostream &O);
   virtual bool printAliasInstr(const MCInst *MI, uint64_t Address,
diff --git a/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp b/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
index 40e8e244e3..a26944a38f 100644
--- a/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
+++ b/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
@@ -87,7 +87,7 @@ void ARMCOFFMCAsmInfoMicrosoft::anchor() { }
 
 ARMCOFFMCAsmInfoMicrosoft::ARMCOFFMCAsmInfoMicrosoft() {
   AlignmentIsInBytes = false;
-  SupportsDebugInformation = true;
+  SupportsDebugInformation = true; 
   ExceptionsType = ExceptionHandling::WinEH;
   PrivateGlobalPrefix = "$M";
   PrivateLabelPrefix = "$M";
diff --git a/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index 774f2507b8..3da71ade87 100644
--- a/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -11,13 +11,13 @@
 //===----------------------------------------------------------------------===//
 
 #include "ARMMCTargetDesc.h"
-#include "ARMAddressingModes.h"
+#include "ARMAddressingModes.h" 
 #include "ARMBaseInfo.h"
 #include "ARMInstPrinter.h"
 #include "ARMMCAsmInfo.h"
 #include "TargetInfo/ARMTargetInfo.h"
 #include "llvm/ADT/Triple.h"
-#include "llvm/DebugInfo/CodeView/CodeView.h"
+#include "llvm/DebugInfo/CodeView/CodeView.h" 
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCELFStreamer.h"
@@ -182,23 +182,23 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
   return ARMArchFeature;
 }
 
-bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
-  const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
-  int PredOpIdx = Desc.findFirstPredOperandIdx();
-  return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL;
-}
-
-bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) {
-  const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
-  for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
-    const MCOperand &MO = MI.getOperand(I);
-    if (MO.isReg() && MO.getReg() == ARM::CPSR &&
-        Desc.OpInfo[I].isOptionalDef())
-      return true;
-  }
-  return false;
-}
-
+bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) { 
+  const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 
+  int PredOpIdx = Desc.findFirstPredOperandIdx(); 
+  return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL; 
+} 
+ 
+bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) { 
+  const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 
+  for (unsigned I = 0; I < MI.getNumOperands(); ++I) { 
+    const MCOperand &MO = MI.getOperand(I); 
+    if (MO.isReg() && MO.getReg() == ARM::CPSR && 
+        Desc.OpInfo[I].isOptionalDef()) 
+      return true; 
+  } 
+  return false; 
+} 
+ 
 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
                                                   StringRef CPU, StringRef FS) {
   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
@@ -209,7 +209,7 @@ MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
       ArchFS = std::string(FS);
   }
 
-  return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);
+  return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS); 
 }
 
 static MCInstrInfo *createARMMCInstrInfo() {
@@ -218,120 +218,120 @@ static MCInstrInfo *createARMMCInstrInfo() {
   return X;
 }
 
-void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
-  // Mapping from CodeView to MC register id.
-  static const struct {
-    codeview::RegisterId CVReg;
-    MCPhysReg Reg;
-  } RegMap[] = {
-      {codeview::RegisterId::ARM_R0, ARM::R0},
-      {codeview::RegisterId::ARM_R1, ARM::R1},
-      {codeview::RegisterId::ARM_R2, ARM::R2},
-      {codeview::RegisterId::ARM_R3, ARM::R3},
-      {codeview::RegisterId::ARM_R4, ARM::R4},
-      {codeview::RegisterId::ARM_R5, ARM::R5},
-      {codeview::RegisterId::ARM_R6, ARM::R6},
-      {codeview::RegisterId::ARM_R7, ARM::R7},
-      {codeview::RegisterId::ARM_R8, ARM::R8},
-      {codeview::RegisterId::ARM_R9, ARM::R9},
-      {codeview::RegisterId::ARM_R10, ARM::R10},
-      {codeview::RegisterId::ARM_R11, ARM::R11},
-      {codeview::RegisterId::ARM_R12, ARM::R12},
-      {codeview::RegisterId::ARM_SP, ARM::SP},
-      {codeview::RegisterId::ARM_LR, ARM::LR},
-      {codeview::RegisterId::ARM_PC, ARM::PC},
-      {codeview::RegisterId::ARM_CPSR, ARM::CPSR},
-      {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},
-      {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC},
-      {codeview::RegisterId::ARM_FS0, ARM::S0},
-      {codeview::RegisterId::ARM_FS1, ARM::S1},
-      {codeview::RegisterId::ARM_FS2, ARM::S2},
-      {codeview::RegisterId::ARM_FS3, ARM::S3},
-      {codeview::RegisterId::ARM_FS4, ARM::S4},
-      {codeview::RegisterId::ARM_FS5, ARM::S5},
-      {codeview::RegisterId::ARM_FS6, ARM::S6},
-      {codeview::RegisterId::ARM_FS7, ARM::S7},
-      {codeview::RegisterId::ARM_FS8, ARM::S8},
-      {codeview::RegisterId::ARM_FS9, ARM::S9},
-      {codeview::RegisterId::ARM_FS10, ARM::S10},
-      {codeview::RegisterId::ARM_FS11, ARM::S11},
-      {codeview::RegisterId::ARM_FS12, ARM::S12},
-      {codeview::RegisterId::ARM_FS13, ARM::S13},
-      {codeview::RegisterId::ARM_FS14, ARM::S14},
-      {codeview::RegisterId::ARM_FS15, ARM::S15},
-      {codeview::RegisterId::ARM_FS16, ARM::S16},
-      {codeview::RegisterId::ARM_FS17, ARM::S17},
-      {codeview::RegisterId::ARM_FS18, ARM::S18},
-      {codeview::RegisterId::ARM_FS19, ARM::S19},
-      {codeview::RegisterId::ARM_FS20, ARM::S20},
-      {codeview::RegisterId::ARM_FS21, ARM::S21},
-      {codeview::RegisterId::ARM_FS22, ARM::S22},
-      {codeview::RegisterId::ARM_FS23, ARM::S23},
-      {codeview::RegisterId::ARM_FS24, ARM::S24},
-      {codeview::RegisterId::ARM_FS25, ARM::S25},
-      {codeview::RegisterId::ARM_FS26, ARM::S26},
-      {codeview::RegisterId::ARM_FS27, ARM::S27},
-      {codeview::RegisterId::ARM_FS28, ARM::S28},
-      {codeview::RegisterId::ARM_FS29, ARM::S29},
-      {codeview::RegisterId::ARM_FS30, ARM::S30},
-      {codeview::RegisterId::ARM_FS31, ARM::S31},
-      {codeview::RegisterId::ARM_ND0, ARM::D0},
-      {codeview::RegisterId::ARM_ND1, ARM::D1},
-      {codeview::RegisterId::ARM_ND2, ARM::D2},
-      {codeview::RegisterId::ARM_ND3, ARM::D3},
-      {codeview::RegisterId::ARM_ND4, ARM::D4},
-      {codeview::RegisterId::ARM_ND5, ARM::D5},
-      {codeview::RegisterId::ARM_ND6, ARM::D6},
-      {codeview::RegisterId::ARM_ND7, ARM::D7},
-      {codeview::RegisterId::ARM_ND8, ARM::D8},
-      {codeview::RegisterId::ARM_ND9, ARM::D9},
-      {codeview::RegisterId::ARM_ND10, ARM::D10},
-      {codeview::RegisterId::ARM_ND11, ARM::D11},
-      {codeview::RegisterId::ARM_ND12, ARM::D12},
-      {codeview::RegisterId::ARM_ND13, ARM::D13},
-      {codeview::RegisterId::ARM_ND14, ARM::D14},
-      {codeview::RegisterId::ARM_ND15, ARM::D15},
-      {codeview::RegisterId::ARM_ND16, ARM::D16},
-      {codeview::RegisterId::ARM_ND17, ARM::D17},
-      {codeview::RegisterId::ARM_ND18, ARM::D18},
-      {codeview::RegisterId::ARM_ND19, ARM::D19},
-      {codeview::RegisterId::ARM_ND20, ARM::D20},
-      {codeview::RegisterId::ARM_ND21, ARM::D21},
-      {codeview::RegisterId::ARM_ND22, ARM::D22},
-      {codeview::RegisterId::ARM_ND23, ARM::D23},
-      {codeview::RegisterId::ARM_ND24, ARM::D24},
-      {codeview::RegisterId::ARM_ND25, ARM::D25},
-      {codeview::RegisterId::ARM_ND26, ARM::D26},
-      {codeview::RegisterId::ARM_ND27, ARM::D27},
-      {codeview::RegisterId::ARM_ND28, ARM::D28},
-      {codeview::RegisterId::ARM_ND29, ARM::D29},
-      {codeview::RegisterId::ARM_ND30, ARM::D30},
-      {codeview::RegisterId::ARM_ND31, ARM::D31},
-      {codeview::RegisterId::ARM_NQ0, ARM::Q0},
-      {codeview::RegisterId::ARM_NQ1, ARM::Q1},
-      {codeview::RegisterId::ARM_NQ2, ARM::Q2},
-      {codeview::RegisterId::ARM_NQ3, ARM::Q3},
-      {codeview::RegisterId::ARM_NQ4, ARM::Q4},
-      {codeview::RegisterId::ARM_NQ5, ARM::Q5},
-      {codeview::RegisterId::ARM_NQ6, ARM::Q6},
-      {codeview::RegisterId::ARM_NQ7, ARM::Q7},
-      {codeview::RegisterId::ARM_NQ8, ARM::Q8},
-      {codeview::RegisterId::ARM_NQ9, ARM::Q9},
-      {codeview::RegisterId::ARM_NQ10, ARM::Q10},
-      {codeview::RegisterId::ARM_NQ11, ARM::Q11},
-      {codeview::RegisterId::ARM_NQ12, ARM::Q12},
-      {codeview::RegisterId::ARM_NQ13, ARM::Q13},
-      {codeview::RegisterId::ARM_NQ14, ARM::Q14},
-      {codeview::RegisterId::ARM_NQ15, ARM::Q15},
-  };
-  for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
-    MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
-}
-
+void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) { 
+  // Mapping from CodeView to MC register id. 
+  static const struct { 
+    codeview::RegisterId CVReg; 
+    MCPhysReg Reg; 
+  } RegMap[] = { 
+      {codeview::RegisterId::ARM_R0, ARM::R0}, 
+      {codeview::RegisterId::ARM_R1, ARM::R1}, 
+      {codeview::RegisterId::ARM_R2, ARM::R2}, 
+      {codeview::RegisterId::ARM_R3, ARM::R3}, 
+      {codeview::RegisterId::ARM_R4, ARM::R4}, 
+      {codeview::RegisterId::ARM_R5, ARM::R5}, 
+      {codeview::RegisterId::ARM_R6, ARM::R6}, 
+      {codeview::RegisterId::ARM_R7, ARM::R7}, 
+      {codeview::RegisterId::ARM_R8, ARM::R8}, 
+      {codeview::RegisterId::ARM_R9, ARM::R9}, 
+      {codeview::RegisterId::ARM_R10, ARM::R10}, 
+      {codeview::RegisterId::ARM_R11, ARM::R11}, 
+      {codeview::RegisterId::ARM_R12, ARM::R12}, 
+      {codeview::RegisterId::ARM_SP, ARM::SP}, 
+      {codeview::RegisterId::ARM_LR, ARM::LR}, 
+      {codeview::RegisterId::ARM_PC, ARM::PC}, 
+      {codeview::RegisterId::ARM_CPSR, ARM::CPSR}, 
+      {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR}, 
+      {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC}, 
+      {codeview::RegisterId::ARM_FS0, ARM::S0}, 
+      {codeview::RegisterId::ARM_FS1, ARM::S1}, 
+      {codeview::RegisterId::ARM_FS2, ARM::S2}, 
+      {codeview::RegisterId::ARM_FS3, ARM::S3}, 
+      {codeview::RegisterId::ARM_FS4, ARM::S4}, 
+      {codeview::RegisterId::ARM_FS5, ARM::S5}, 
+      {codeview::RegisterId::ARM_FS6, ARM::S6}, 
+      {codeview::RegisterId::ARM_FS7, ARM::S7}, 
+      {codeview::RegisterId::ARM_FS8, ARM::S8}, 
+      {codeview::RegisterId::ARM_FS9, ARM::S9}, 
+      {codeview::RegisterId::ARM_FS10, ARM::S10}, 
+      {codeview::RegisterId::ARM_FS11, ARM::S11}, 
+      {codeview::RegisterId::ARM_FS12, ARM::S12}, 
+      {codeview::RegisterId::ARM_FS13, ARM::S13}, 
+      {codeview::RegisterId::ARM_FS14, ARM::S14}, 
+      {codeview::RegisterId::ARM_FS15, ARM::S15}, 
+      {codeview::RegisterId::ARM_FS16, ARM::S16}, 
+      {codeview::RegisterId::ARM_FS17, ARM::S17}, 
+      {codeview::RegisterId::ARM_FS18, ARM::S18}, 
+      {codeview::RegisterId::ARM_FS19, ARM::S19}, 
+      {codeview::RegisterId::ARM_FS20, ARM::S20}, 
+      {codeview::RegisterId::ARM_FS21, ARM::S21}, 
+      {codeview::RegisterId::ARM_FS22, ARM::S22}, 
+      {codeview::RegisterId::ARM_FS23, ARM::S23}, 
+      {codeview::RegisterId::ARM_FS24, ARM::S24}, 
+      {codeview::RegisterId::ARM_FS25, ARM::S25}, 
+      {codeview::RegisterId::ARM_FS26, ARM::S26}, 
+      {codeview::RegisterId::ARM_FS27, ARM::S27}, 
+      {codeview::RegisterId::ARM_FS28, ARM::S28}, 
+      {codeview::RegisterId::ARM_FS29, ARM::S29}, 
+      {codeview::RegisterId::ARM_FS30, ARM::S30}, 
+      {codeview::RegisterId::ARM_FS31, ARM::S31}, 
+      {codeview::RegisterId::ARM_ND0, ARM::D0}, 
+      {codeview::RegisterId::ARM_ND1, ARM::D1}, 
+      {codeview::RegisterId::ARM_ND2, ARM::D2}, 
+      {codeview::RegisterId::ARM_ND3, ARM::D3}, 
+      {codeview::RegisterId::ARM_ND4, ARM::D4}, 
+      {codeview::RegisterId::ARM_ND5, ARM::D5}, 
+      {codeview::RegisterId::ARM_ND6, ARM::D6}, 
+      {codeview::RegisterId::ARM_ND7, ARM::D7}, 
+      {codeview::RegisterId::ARM_ND8, ARM::D8}, 
+      {codeview::RegisterId::ARM_ND9, ARM::D9}, 
+      {codeview::RegisterId::ARM_ND10, ARM::D10}, 
+      {codeview::RegisterId::ARM_ND11, ARM::D11}, 
+      {codeview::RegisterId::ARM_ND12, ARM::D12}, 
+      {codeview::RegisterId::ARM_ND13, ARM::D13}, 
+      {codeview::RegisterId::ARM_ND14, ARM::D14}, 
+      {codeview::RegisterId::ARM_ND15, ARM::D15}, 
+      {codeview::RegisterId::ARM_ND16, ARM::D16}, 
+      {codeview::RegisterId::ARM_ND17, ARM::D17}, 
+      {codeview::RegisterId::ARM_ND18, ARM::D18}, 
+      {codeview::RegisterId::ARM_ND19, ARM::D19}, 
+      {codeview::RegisterId::ARM_ND20, ARM::D20}, 
+      {codeview::RegisterId::ARM_ND21, ARM::D21}, 
+      {codeview::RegisterId::ARM_ND22, ARM::D22}, 
+      {codeview::RegisterId::ARM_ND23, ARM::D23}, 
+      {codeview::RegisterId::ARM_ND24, ARM::D24}, 
+      {codeview::RegisterId::ARM_ND25, ARM::D25}, 
+      {codeview::RegisterId::ARM_ND26, ARM::D26}, 
+      {codeview::RegisterId::ARM_ND27, ARM::D27}, 
+      {codeview::RegisterId::ARM_ND28, ARM::D28}, 
+      {codeview::RegisterId::ARM_ND29, ARM::D29}, 
+      {codeview::RegisterId::ARM_ND30, ARM::D30}, 
+      {codeview::RegisterId::ARM_ND31, ARM::D31}, 
+      {codeview::RegisterId::ARM_NQ0, ARM::Q0}, 
+      {codeview::RegisterId::ARM_NQ1, ARM::Q1}, 
+      {codeview::RegisterId::ARM_NQ2, ARM::Q2}, 
+      {codeview::RegisterId::ARM_NQ3, ARM::Q3}, 
+      {codeview::RegisterId::ARM_NQ4, ARM::Q4}, 
+      {codeview::RegisterId::ARM_NQ5, ARM::Q5}, 
+      {codeview::RegisterId::ARM_NQ6, ARM::Q6}, 
+      {codeview::RegisterId::ARM_NQ7, ARM::Q7}, 
+      {codeview::RegisterId::ARM_NQ8, ARM::Q8}, 
+      {codeview::RegisterId::ARM_NQ9, ARM::Q9}, 
+      {codeview::RegisterId::ARM_NQ10, ARM::Q10}, 
+      {codeview::RegisterId::ARM_NQ11, ARM::Q11}, 
+      {codeview::RegisterId::ARM_NQ12, ARM::Q12}, 
+      {codeview::RegisterId::ARM_NQ13, ARM::Q13}, 
+      {codeview::RegisterId::ARM_NQ14, ARM::Q14}, 
+      {codeview::RegisterId::ARM_NQ15, ARM::Q15}, 
+  }; 
+  for (unsigned I = 0; I < array_lengthof(RegMap); ++I) 
+    MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg)); 
+} 
+ 
 static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
-  ARM_MC::initLLVMToCVRegMapping(X);
+  ARM_MC::initLLVMToCVRegMapping(X); 
   return X;
 }
 
diff --git a/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h b/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
index 5a0874f0ef..a84576e757 100644
--- a/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
+++ b/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
@@ -41,22 +41,22 @@ class raw_pwrite_stream;
 
 namespace ARM_MC {
 std::string ParseARMTriple(const Triple &TT, StringRef CPU);
-void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
-
-bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
-bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII);
-
-template<class Inst>
-bool isLDMBaseRegInList(const Inst &MI) {
-  auto BaseReg = MI.getOperand(0).getReg();
-  for (unsigned I = 1, E = MI.getNumOperands(); I < E; ++I) {
-    const auto &Op = MI.getOperand(I);
-    if (Op.isReg() && Op.getReg() == BaseReg)
-      return true;
-  }
-  return false;
-}
-
+void initLLVMToCVRegMapping(MCRegisterInfo *MRI); 
+
+bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII); 
+bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII); 
+ 
+template<class Inst> 
+bool isLDMBaseRegInList(const Inst &MI) { 
+  auto BaseReg = MI.getOperand(0).getReg(); 
+  for (unsigned I = 1, E = MI.getNumOperands(); I < E; ++I) { 
+    const auto &Op = MI.getOperand(I); 
+    if (Op.isReg() && Op.getReg() == BaseReg) 
+      return true; 
+  } 
+  return false; 
+} 
+ 
 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
 /// do not need to go through TargetRegistry.
 MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
diff --git a/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ya.make b/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ya.make
index b92b47d057..0256e1fdac 100644
--- a/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ya.make
+++ b/contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc/ya.make
@@ -12,20 +12,20 @@ LICENSE(Apache-2.0 WITH LLVM-exception)
 LICENSE_TEXTS(.yandex_meta/licenses.list.txt)
 
 PEERDIR(
-    contrib/libs/llvm12
-    contrib/libs/llvm12/include
-    contrib/libs/llvm12/lib/BinaryFormat
-    contrib/libs/llvm12/lib/MC
-    contrib/libs/llvm12/lib/MC/MCDisassembler
-    contrib/libs/llvm12/lib/Support
-    contrib/libs/llvm12/lib/Target/ARM/TargetInfo
-    contrib/libs/llvm12/lib/Target/ARM/Utils
+    contrib/libs/llvm12 
+    contrib/libs/llvm12/include 
+    contrib/libs/llvm12/lib/BinaryFormat 
+    contrib/libs/llvm12/lib/MC 
+    contrib/libs/llvm12/lib/MC/MCDisassembler 
+    contrib/libs/llvm12/lib/Support 
+    contrib/libs/llvm12/lib/Target/ARM/TargetInfo 
+    contrib/libs/llvm12/lib/Target/ARM/Utils 
 )
 
 ADDINCL(
-    ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM
-    contrib/libs/llvm12/lib/Target/ARM
-    contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc
+    ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM 
+    contrib/libs/llvm12/lib/Target/ARM 
+    contrib/libs/llvm12/lib/Target/ARM/MCTargetDesc 
 )
 
 NO_COMPILER_WARNINGS()