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| author | shadchin <shadchin@yandex-team.ru> | 2022-02-10 16:44:39 +0300 |
|---|---|---|
| committer | Daniil Cherednik <dcherednik@yandex-team.ru> | 2022-02-10 16:44:39 +0300 |
| commit | e9656aae26e0358d5378e5b63dcac5c8dbe0e4d0 (patch) | |
| tree | 64175d5cadab313b3e7039ebaa06c5bc3295e274 /contrib/libs/llvm12/lib/Target/ARM/ARMFastISel.cpp | |
| parent | 2598ef1d0aee359b4b6d5fdd1758916d5907d04f (diff) | |
| download | ydb-e9656aae26e0358d5378e5b63dcac5c8dbe0e4d0.tar.gz | |
Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 2 of 2.
Diffstat (limited to 'contrib/libs/llvm12/lib/Target/ARM/ARMFastISel.cpp')
| -rw-r--r-- | contrib/libs/llvm12/lib/Target/ARM/ARMFastISel.cpp | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/contrib/libs/llvm12/lib/Target/ARM/ARMFastISel.cpp b/contrib/libs/llvm12/lib/Target/ARM/ARMFastISel.cpp index 483aeb4d72..da1d9af8d5 100644 --- a/contrib/libs/llvm12/lib/Target/ARM/ARMFastISel.cpp +++ b/contrib/libs/llvm12/lib/Target/ARM/ARMFastISel.cpp @@ -606,9 +606,9 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) { } } - if ((Subtarget->isTargetELF() && Subtarget->isGVInGOT(GV)) || - (Subtarget->isTargetMachO() && IsIndirect) || - Subtarget->genLongCalls()) { + if ((Subtarget->isTargetELF() && Subtarget->isGVInGOT(GV)) || + (Subtarget->isTargetMachO() && IsIndirect) || + Subtarget->genLongCalls()) { MachineInstrBuilder MIB; unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); if (isThumb2) @@ -2175,7 +2175,7 @@ bool ARMFastISel::SelectRet(const Instruction *I) { unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) { if (UseReg) - return isThumb2 ? gettBLXrOpcode(*MF) : getBLXOpcode(*MF); + return isThumb2 ? gettBLXrOpcode(*MF) : getBLXOpcode(*MF); else return isThumb2 ? ARM::tBL : ARM::BL; } @@ -2266,11 +2266,11 @@ bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) { // BL / BLX don't take a predicate, but tBL / tBLX do. if (isThumb2) MIB.add(predOps(ARMCC::AL)); - if (Subtarget->genLongCalls()) { - CalleeReg = - constrainOperandRegClass(TII.get(CallOpc), CalleeReg, isThumb2 ? 2 : 0); + if (Subtarget->genLongCalls()) { + CalleeReg = + constrainOperandRegClass(TII.get(CallOpc), CalleeReg, isThumb2 ? 2 : 0); MIB.addReg(CalleeReg); - } else + } else MIB.addExternalSymbol(TLI.getLibcallName(Call)); // Add implicit physical register uses to the call. @@ -2408,11 +2408,11 @@ bool ARMFastISel::SelectCall(const Instruction *I, // ARM calls don't take a predicate, but tBL / tBLX do. if(isThumb2) MIB.add(predOps(ARMCC::AL)); - if (UseReg) { - CalleeReg = - constrainOperandRegClass(TII.get(CallOpc), CalleeReg, isThumb2 ? 2 : 0); + if (UseReg) { + CalleeReg = + constrainOperandRegClass(TII.get(CallOpc), CalleeReg, isThumb2 ? 2 : 0); MIB.addReg(CalleeReg); - } else if (!IntrMemName) + } else if (!IntrMemName) MIB.addGlobalAddress(GV, 0, 0); else MIB.addExternalSymbol(IntrMemName, 0); |