Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 2 of 2.

1 files changed, 60 insertions, 60 deletions

diff --git a/contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td b/contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
index b7d5014166..25656fac1d 100644
--- a/contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
@@ -88,29 +88,29 @@ def G_DUP: AArch64GenericInstruction {
   let InOperandList = (ins type1:$lane);
   let hasSideEffects = 0;
 }
- 
-// Represents a lane duplicate operation. 
-def G_DUPLANE8 : AArch64GenericInstruction { 
-  let OutOperandList = (outs type0:$dst); 
-  let InOperandList = (ins type0:$src, type1:$lane); 
-  let hasSideEffects = 0; 
-} 
-def G_DUPLANE16 : AArch64GenericInstruction { 
-  let OutOperandList = (outs type0:$dst); 
-  let InOperandList = (ins type0:$src, type1:$lane); 
-  let hasSideEffects = 0; 
-} 
-def G_DUPLANE32 : AArch64GenericInstruction { 
-  let OutOperandList = (outs type0:$dst); 
-  let InOperandList = (ins type0:$src, type1:$lane); 
-  let hasSideEffects = 0; 
-} 
-def G_DUPLANE64 : AArch64GenericInstruction { 
-  let OutOperandList = (outs type0:$dst); 
-  let InOperandList = (ins type0:$src, type1:$lane); 
-  let hasSideEffects = 0; 
-} 
- 
+
+// Represents a lane duplicate operation.
+def G_DUPLANE8 : AArch64GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src, type1:$lane);
+  let hasSideEffects = 0;
+}
+def G_DUPLANE16 : AArch64GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src, type1:$lane);
+  let hasSideEffects = 0;
+}
+def G_DUPLANE32 : AArch64GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src, type1:$lane);
+  let hasSideEffects = 0;
+}
+def G_DUPLANE64 : AArch64GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src, type1:$lane);
+  let hasSideEffects = 0;
+}
+
 // Represents a trn1 instruction. Produced post-legalization from
 // G_SHUFFLE_VECTORs with appropriate masks.
 def G_TRN1 : AArch64GenericInstruction {
@@ -134,28 +134,28 @@ def G_EXT: AArch64GenericInstruction {
   let InOperandList = (ins type0:$v1, type0:$v2, untyped_imm_0:$imm);
 }
 
-// Represents a vector G_ASHR with an immediate. 
-def G_VASHR : AArch64GenericInstruction { 
-  let OutOperandList = (outs type0:$dst); 
-  let InOperandList = (ins type0:$src1, untyped_imm_0:$imm); 
-} 
- 
-// Represents a vector G_LSHR with an immediate. 
-def G_VLSHR : AArch64GenericInstruction { 
-  let OutOperandList = (outs type0:$dst); 
-  let InOperandList = (ins type0:$src1, untyped_imm_0:$imm); 
-} 
- 
-// Represents an integer to FP conversion on the FPR bank. 
-def G_SITOF : AArch64GenericInstruction { 
-  let OutOperandList = (outs type0:$dst); 
-  let InOperandList = (ins type0:$src); 
-} 
-def G_UITOF : AArch64GenericInstruction { 
-  let OutOperandList = (outs type0:$dst); 
-  let InOperandList = (ins type0:$src); 
-} 
- 
+// Represents a vector G_ASHR with an immediate.
+def G_VASHR : AArch64GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src1, untyped_imm_0:$imm);
+}
+
+// Represents a vector G_LSHR with an immediate.
+def G_VLSHR : AArch64GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src1, untyped_imm_0:$imm);
+}
+
+// Represents an integer to FP conversion on the FPR bank.
+def G_SITOF : AArch64GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src);
+}
+def G_UITOF : AArch64GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src);
+}
+
 def : GINodeEquiv<G_REV16, AArch64rev16>;
 def : GINodeEquiv<G_REV32, AArch64rev32>;
 def : GINodeEquiv<G_REV64, AArch64rev64>;
@@ -164,21 +164,21 @@ def : GINodeEquiv<G_UZP2, AArch64uzp2>;
 def : GINodeEquiv<G_ZIP1, AArch64zip1>;
 def : GINodeEquiv<G_ZIP2, AArch64zip2>;
 def : GINodeEquiv<G_DUP, AArch64dup>;
-def : GINodeEquiv<G_DUPLANE8, AArch64duplane8>; 
-def : GINodeEquiv<G_DUPLANE16, AArch64duplane16>; 
-def : GINodeEquiv<G_DUPLANE32, AArch64duplane32>; 
-def : GINodeEquiv<G_DUPLANE64, AArch64duplane64>; 
+def : GINodeEquiv<G_DUPLANE8, AArch64duplane8>;
+def : GINodeEquiv<G_DUPLANE16, AArch64duplane16>;
+def : GINodeEquiv<G_DUPLANE32, AArch64duplane32>;
+def : GINodeEquiv<G_DUPLANE64, AArch64duplane64>;
 def : GINodeEquiv<G_TRN1, AArch64trn1>;
 def : GINodeEquiv<G_TRN2, AArch64trn2>;
 def : GINodeEquiv<G_EXT, AArch64ext>;
-def : GINodeEquiv<G_VASHR, AArch64vashr>; 
-def : GINodeEquiv<G_VLSHR, AArch64vlshr>; 
-def : GINodeEquiv<G_SITOF, AArch64sitof>; 
-def : GINodeEquiv<G_UITOF, AArch64uitof>; 
- 
-def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>; 
- 
-// These are patterns that we only use for GlobalISel via the importer. 
-def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)), 
-                     (vector_extract (v2f32 FPR64:$Rn), (i64 1)))), 
-           (f32 (FADDPv2i32p (v2f32 FPR64:$Rn)))>; 
+def : GINodeEquiv<G_VASHR, AArch64vashr>;
+def : GINodeEquiv<G_VLSHR, AArch64vlshr>;
+def : GINodeEquiv<G_SITOF, AArch64sitof>;
+def : GINodeEquiv<G_UITOF, AArch64uitof>;
+
+def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
+
+// These are patterns that we only use for GlobalISel via the importer.
+def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
+                     (vector_extract (v2f32 FPR64:$Rn), (i64 1)))),
+           (f32 (FADDPv2i32p (v2f32 FPR64:$Rn)))>;