Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 1 of 2.

1 files changed, 271 insertions, 271 deletions

diff --git a/contrib/libs/llvm12/lib/CodeGen/MachineVerifier.cpp b/contrib/libs/llvm12/lib/CodeGen/MachineVerifier.cpp
index 0f6d9b888f..9e4409ac3e 100644
--- a/contrib/libs/llvm12/lib/CodeGen/MachineVerifier.cpp
+++ b/contrib/libs/llvm12/lib/CodeGen/MachineVerifier.cpp
@@ -86,7 +86,7 @@ namespace {
   struct MachineVerifier {
     MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
 
-    unsigned verify(const MachineFunction &MF);
+    unsigned verify(const MachineFunction &MF); 
 
     Pass *const PASS;
     const char *Banner;
@@ -102,10 +102,10 @@ namespace {
     bool isFunctionRegBankSelected;
     bool isFunctionSelected;
 
-    using RegVector = SmallVector<Register, 16>;
+    using RegVector = SmallVector<Register, 16>; 
     using RegMaskVector = SmallVector<const uint32_t *, 4>;
-    using RegSet = DenseSet<Register>;
-    using RegMap = DenseMap<Register, const MachineInstr *>;
+    using RegSet = DenseSet<Register>; 
+    using RegMap = DenseMap<Register, const MachineInstr *>; 
     using BlockSet = SmallPtrSet<const MachineBasicBlock *, 8>;
 
     const MachineInstr *FirstNonPHI;
@@ -120,10 +120,10 @@ namespace {
     SlotIndex lastIndex;
 
     // Add Reg and any sub-registers to RV
-    void addRegWithSubRegs(RegVector &RV, Register Reg) {
+    void addRegWithSubRegs(RegVector &RV, Register Reg) { 
       RV.push_back(Reg);
-      if (Reg.isPhysical())
-        append_range(RV, TRI->subregs(Reg.asMCReg()));
+      if (Reg.isPhysical()) 
+        append_range(RV, TRI->subregs(Reg.asMCReg())); 
     }
 
     struct BBInfo {
@@ -131,8 +131,8 @@ namespace {
       bool reachable = false;
 
       // Vregs that must be live in because they are used without being
-      // defined. Map value is the user. vregsLiveIn doesn't include regs
-      // that only are used by PHI nodes.
+      // defined. Map value is the user. vregsLiveIn doesn't include regs 
+      // that only are used by PHI nodes. 
       RegMap vregsLiveIn;
 
       // Regs killed in MBB. They may be defined again, and will then be in both
@@ -158,8 +158,8 @@ namespace {
 
       // Add register to vregsRequired if it belongs there. Return true if
       // anything changed.
-      bool addRequired(Register Reg) {
-        if (!Reg.isVirtual())
+      bool addRequired(Register Reg) { 
+        if (!Reg.isVirtual()) 
           return false;
         if (regsLiveOut.count(Reg))
           return false;
@@ -169,7 +169,7 @@ namespace {
       // Same for a full set.
       bool addRequired(const RegSet &RS) {
         bool Changed = false;
-        for (Register Reg : RS)
+        for (Register Reg : RS) 
           Changed |= addRequired(Reg);
         return Changed;
       }
@@ -183,7 +183,7 @@ namespace {
       }
 
       // Live-out registers are either in regsLiveOut or vregsPassed.
-      bool isLiveOut(Register Reg) const {
+      bool isLiveOut(Register Reg) const { 
         return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
       }
     };
@@ -191,13 +191,13 @@ namespace {
     // Extra register info per MBB.
     DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
 
-    bool isReserved(Register Reg) {
-      return Reg.id() < regsReserved.size() && regsReserved.test(Reg.id());
+    bool isReserved(Register Reg) { 
+      return Reg.id() < regsReserved.size() && regsReserved.test(Reg.id()); 
     }
 
-    bool isAllocatable(Register Reg) const {
-      return Reg.id() < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
-             !regsReserved.test(Reg.id());
+    bool isAllocatable(Register Reg) const { 
+      return Reg.id() < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) && 
+             !regsReserved.test(Reg.id()); 
     }
 
     // Analysis information if available
@@ -225,7 +225,7 @@ namespace {
                 LLT MOVRegType = LLT{});
 
     void report_context(const LiveInterval &LI) const;
-    void report_context(const LiveRange &LR, Register VRegUnit,
+    void report_context(const LiveRange &LR, Register VRegUnit, 
                         LaneBitmask LaneMask) const;
     void report_context(const LiveRange::Segment &S) const;
     void report_context(const VNInfo &VNI) const;
@@ -233,19 +233,19 @@ namespace {
     void report_context(MCPhysReg PhysReg) const;
     void report_context_liverange(const LiveRange &LR) const;
     void report_context_lanemask(LaneBitmask LaneMask) const;
-    void report_context_vreg(Register VReg) const;
-    void report_context_vreg_regunit(Register VRegOrUnit) const;
+    void report_context_vreg(Register VReg) const; 
+    void report_context_vreg_regunit(Register VRegOrUnit) const; 
 
     void verifyInlineAsm(const MachineInstr *MI);
 
     void checkLiveness(const MachineOperand *MO, unsigned MONum);
     void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
-                            SlotIndex UseIdx, const LiveRange &LR,
-                            Register VRegOrUnit,
+                            SlotIndex UseIdx, const LiveRange &LR, 
+                            Register VRegOrUnit, 
                             LaneBitmask LaneMask = LaneBitmask::getNone());
     void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
-                            SlotIndex DefIdx, const LiveRange &LR,
-                            Register VRegOrUnit, bool SubRangeCheck = false,
+                            SlotIndex DefIdx, const LiveRange &LR, 
+                            Register VRegOrUnit, bool SubRangeCheck = false, 
                             LaneBitmask LaneMask = LaneBitmask::getNone());
 
     void markReachable(const MachineBasicBlock *MBB);
@@ -256,12 +256,12 @@ namespace {
     void verifyLiveVariables();
     void verifyLiveIntervals();
     void verifyLiveInterval(const LiveInterval&);
-    void verifyLiveRangeValue(const LiveRange &, const VNInfo *, Register,
+    void verifyLiveRangeValue(const LiveRange &, const VNInfo *, Register, 
                               LaneBitmask);
-    void verifyLiveRangeSegment(const LiveRange &,
-                                const LiveRange::const_iterator I, Register,
+    void verifyLiveRangeSegment(const LiveRange &, 
+                                const LiveRange::const_iterator I, Register, 
                                 LaneBitmask);
-    void verifyLiveRange(const LiveRange &, Register,
+    void verifyLiveRange(const LiveRange &, Register, 
                          LaneBitmask LaneMask = LaneBitmask::getNone());
 
     void verifyStackFrame();
@@ -304,19 +304,19 @@ FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
   return new MachineVerifierPass(Banner);
 }
 
-void llvm::verifyMachineFunction(MachineFunctionAnalysisManager *,
-                                 const std::string &Banner,
-                                 const MachineFunction &MF) {
-  // TODO: Use MFAM after porting below analyses.
-  // LiveVariables *LiveVars;
-  // LiveIntervals *LiveInts;
-  // LiveStacks *LiveStks;
-  // SlotIndexes *Indexes;
-  unsigned FoundErrors = MachineVerifier(nullptr, Banner.c_str()).verify(MF);
-  if (FoundErrors)
-    report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
-}
-
+void llvm::verifyMachineFunction(MachineFunctionAnalysisManager *, 
+                                 const std::string &Banner, 
+                                 const MachineFunction &MF) { 
+  // TODO: Use MFAM after porting below analyses. 
+  // LiveVariables *LiveVars; 
+  // LiveIntervals *LiveInts; 
+  // LiveStacks *LiveStks; 
+  // SlotIndexes *Indexes; 
+  unsigned FoundErrors = MachineVerifier(nullptr, Banner.c_str()).verify(MF); 
+  if (FoundErrors) 
+    report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors."); 
+} 
+ 
 bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
     const {
   MachineFunction &MF = const_cast<MachineFunction&>(*this);
@@ -349,7 +349,7 @@ void MachineVerifier::verifyProperties(const MachineFunction &MF) {
     report("Function has NoVRegs property but there are VReg operands", &MF);
 }
 
-unsigned MachineVerifier::verify(const MachineFunction &MF) {
+unsigned MachineVerifier::verify(const MachineFunction &MF) { 
   foundErrors = 0;
 
   this->MF = &MF;
@@ -488,7 +488,7 @@ void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
   errs() << "- instruction: ";
   if (Indexes && Indexes->hasIndex(*MI))
     errs() << Indexes->getInstructionIndex(*MI) << '\t';
-  MI->print(errs(), /*IsStandalone=*/true);
+  MI->print(errs(), /*IsStandalone=*/true); 
 }
 
 void MachineVerifier::report(const char *msg, const MachineOperand *MO,
@@ -508,7 +508,7 @@ void MachineVerifier::report_context(const LiveInterval &LI) const {
   errs() << "- interval:    " << LI << '\n';
 }
 
-void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit,
+void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit, 
                                      LaneBitmask LaneMask) const {
   report_context_liverange(LR);
   report_context_vreg_regunit(VRegUnit);
@@ -532,11 +532,11 @@ void MachineVerifier::report_context(MCPhysReg PReg) const {
   errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
 }
 
-void MachineVerifier::report_context_vreg(Register VReg) const {
+void MachineVerifier::report_context_vreg(Register VReg) const { 
   errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
 }
 
-void MachineVerifier::report_context_vreg_regunit(Register VRegOrUnit) const {
+void MachineVerifier::report_context_vreg_regunit(Register VRegOrUnit) const { 
   if (Register::isVirtualRegister(VRegOrUnit)) {
     report_context_vreg(VRegOrUnit);
   } else {
@@ -790,7 +790,7 @@ void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
   }
 
   // Ensure non-terminators don't follow terminators.
-  if (MI->isTerminator()) {
+  if (MI->isTerminator()) { 
     if (!FirstTerminator)
       FirstTerminator = MI;
   } else if (FirstTerminator) {
@@ -1004,15 +1004,15 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
   }
   case TargetOpcode::G_PHI: {
     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
-    if (!DstTy.isValid() || !all_of(drop_begin(MI->operands()),
-                                    [this, &DstTy](const MachineOperand &MO) {
-                                      if (!MO.isReg())
-                                        return true;
-                                      LLT Ty = MRI->getType(MO.getReg());
-                                      if (!Ty.isValid() || (Ty != DstTy))
-                                        return false;
-                                      return true;
-                                    }))
+    if (!DstTy.isValid() || !all_of(drop_begin(MI->operands()), 
+                                    [this, &DstTy](const MachineOperand &MO) { 
+                                      if (!MO.isReg()) 
+                                        return true; 
+                                      LLT Ty = MRI->getType(MO.getReg()); 
+                                      if (!Ty.isValid() || (Ty != DstTy)) 
+                                        return false; 
+                                      return true; 
+                                    })) 
       report("Generic Instruction G_PHI has operands with incompatible/missing "
              "types",
              MI);
@@ -1354,7 +1354,7 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
         break;
       }
     }
-
+ 
     break;
   }
   case TargetOpcode::G_SEXT_INREG: {
@@ -1432,95 +1432,95 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
     }
     break;
   }
-  case TargetOpcode::G_MEMCPY:
-  case TargetOpcode::G_MEMMOVE: {
-    ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
-    if (MMOs.size() != 2) {
-      report("memcpy/memmove must have 2 memory operands", MI);
-      break;
-    }
-
-    if ((!MMOs[0]->isStore() || MMOs[0]->isLoad()) ||
-        (MMOs[1]->isStore() || !MMOs[1]->isLoad())) {
-      report("wrong memory operand types", MI);
-      break;
-    }
-
-    if (MMOs[0]->getSize() != MMOs[1]->getSize())
-      report("inconsistent memory operand sizes", MI);
-
-    LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
-    LLT SrcPtrTy = MRI->getType(MI->getOperand(1).getReg());
-
-    if (!DstPtrTy.isPointer() || !SrcPtrTy.isPointer()) {
-      report("memory instruction operand must be a pointer", MI);
-      break;
-    }
-
-    if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
-      report("inconsistent store address space", MI);
-    if (SrcPtrTy.getAddressSpace() != MMOs[1]->getAddrSpace())
-      report("inconsistent load address space", MI);
-
-    break;
-  }
-  case TargetOpcode::G_MEMSET: {
-    ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
-    if (MMOs.size() != 1) {
-      report("memset must have 1 memory operand", MI);
-      break;
-    }
-
-    if ((!MMOs[0]->isStore() || MMOs[0]->isLoad())) {
-      report("memset memory operand must be a store", MI);
-      break;
-    }
-
-    LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
-    if (!DstPtrTy.isPointer()) {
-      report("memset operand must be a pointer", MI);
-      break;
-    }
-
-    if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
-      report("inconsistent memset address space", MI);
-
-    break;
-  }
-  case TargetOpcode::G_VECREDUCE_SEQ_FADD:
-  case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
-    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
-    LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
-    LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
-    if (!DstTy.isScalar())
-      report("Vector reduction requires a scalar destination type", MI);
-    if (!Src1Ty.isScalar())
-      report("Sequential FADD/FMUL vector reduction requires a scalar 1st operand", MI);
-    if (!Src2Ty.isVector())
-      report("Sequential FADD/FMUL vector reduction must have a vector 2nd operand", MI);
-    break;
-  }
-  case TargetOpcode::G_VECREDUCE_FADD:
-  case TargetOpcode::G_VECREDUCE_FMUL:
-  case TargetOpcode::G_VECREDUCE_FMAX:
-  case TargetOpcode::G_VECREDUCE_FMIN:
-  case TargetOpcode::G_VECREDUCE_ADD:
-  case TargetOpcode::G_VECREDUCE_MUL:
-  case TargetOpcode::G_VECREDUCE_AND:
-  case TargetOpcode::G_VECREDUCE_OR:
-  case TargetOpcode::G_VECREDUCE_XOR:
-  case TargetOpcode::G_VECREDUCE_SMAX:
-  case TargetOpcode::G_VECREDUCE_SMIN:
-  case TargetOpcode::G_VECREDUCE_UMAX:
-  case TargetOpcode::G_VECREDUCE_UMIN: {
-    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
-    LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
-    if (!DstTy.isScalar())
-      report("Vector reduction requires a scalar destination type", MI);
-    if (!SrcTy.isVector())
-      report("Vector reduction requires vector source=", MI);
-    break;
-  }
+  case TargetOpcode::G_MEMCPY: 
+  case TargetOpcode::G_MEMMOVE: { 
+    ArrayRef<MachineMemOperand *> MMOs = MI->memoperands(); 
+    if (MMOs.size() != 2) { 
+      report("memcpy/memmove must have 2 memory operands", MI); 
+      break; 
+    } 
+ 
+    if ((!MMOs[0]->isStore() || MMOs[0]->isLoad()) || 
+        (MMOs[1]->isStore() || !MMOs[1]->isLoad())) { 
+      report("wrong memory operand types", MI); 
+      break; 
+    } 
+ 
+    if (MMOs[0]->getSize() != MMOs[1]->getSize()) 
+      report("inconsistent memory operand sizes", MI); 
+ 
+    LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg()); 
+    LLT SrcPtrTy = MRI->getType(MI->getOperand(1).getReg()); 
+ 
+    if (!DstPtrTy.isPointer() || !SrcPtrTy.isPointer()) { 
+      report("memory instruction operand must be a pointer", MI); 
+      break; 
+    } 
+ 
+    if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace()) 
+      report("inconsistent store address space", MI); 
+    if (SrcPtrTy.getAddressSpace() != MMOs[1]->getAddrSpace()) 
+      report("inconsistent load address space", MI); 
+ 
+    break; 
+  } 
+  case TargetOpcode::G_MEMSET: { 
+    ArrayRef<MachineMemOperand *> MMOs = MI->memoperands(); 
+    if (MMOs.size() != 1) { 
+      report("memset must have 1 memory operand", MI); 
+      break; 
+    } 
+ 
+    if ((!MMOs[0]->isStore() || MMOs[0]->isLoad())) { 
+      report("memset memory operand must be a store", MI); 
+      break; 
+    } 
+ 
+    LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg()); 
+    if (!DstPtrTy.isPointer()) { 
+      report("memset operand must be a pointer", MI); 
+      break; 
+    } 
+ 
+    if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace()) 
+      report("inconsistent memset address space", MI); 
+ 
+    break; 
+  } 
+  case TargetOpcode::G_VECREDUCE_SEQ_FADD: 
+  case TargetOpcode::G_VECREDUCE_SEQ_FMUL: { 
+    LLT DstTy = MRI->getType(MI->getOperand(0).getReg()); 
+    LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg()); 
+    LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg()); 
+    if (!DstTy.isScalar()) 
+      report("Vector reduction requires a scalar destination type", MI); 
+    if (!Src1Ty.isScalar()) 
+      report("Sequential FADD/FMUL vector reduction requires a scalar 1st operand", MI); 
+    if (!Src2Ty.isVector()) 
+      report("Sequential FADD/FMUL vector reduction must have a vector 2nd operand", MI); 
+    break; 
+  } 
+  case TargetOpcode::G_VECREDUCE_FADD: 
+  case TargetOpcode::G_VECREDUCE_FMUL: 
+  case TargetOpcode::G_VECREDUCE_FMAX: 
+  case TargetOpcode::G_VECREDUCE_FMIN: 
+  case TargetOpcode::G_VECREDUCE_ADD: 
+  case TargetOpcode::G_VECREDUCE_MUL: 
+  case TargetOpcode::G_VECREDUCE_AND: 
+  case TargetOpcode::G_VECREDUCE_OR: 
+  case TargetOpcode::G_VECREDUCE_XOR: 
+  case TargetOpcode::G_VECREDUCE_SMAX: 
+  case TargetOpcode::G_VECREDUCE_SMIN: 
+  case TargetOpcode::G_VECREDUCE_UMAX: 
+  case TargetOpcode::G_VECREDUCE_UMIN: { 
+    LLT DstTy = MRI->getType(MI->getOperand(0).getReg()); 
+    LLT SrcTy = MRI->getType(MI->getOperand(1).getReg()); 
+    if (!DstTy.isScalar()) 
+      report("Vector reduction requires a scalar destination type", MI); 
+    if (!SrcTy.isVector()) 
+      report("Vector reduction requires vector source=", MI); 
+    break; 
+  } 
   default:
     break;
   }
@@ -1548,16 +1548,16 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
   if (MI->isInlineAsm())
     verifyInlineAsm(MI);
 
-  // Check that unspillable terminators define a reg and have at most one use.
-  if (TII->isUnspillableTerminator(MI)) {
-    if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef())
-      report("Unspillable Terminator does not define a reg", MI);
-    Register Def = MI->getOperand(0).getReg();
-    if (Def.isVirtual() &&
-        std::distance(MRI->use_nodbg_begin(Def), MRI->use_nodbg_end()) > 1)
-      report("Unspillable Terminator expected to have at most one use!", MI);
-  }
-
+  // Check that unspillable terminators define a reg and have at most one use. 
+  if (TII->isUnspillableTerminator(MI)) { 
+    if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef()) 
+      report("Unspillable Terminator does not define a reg", MI); 
+    Register Def = MI->getOperand(0).getReg(); 
+    if (Def.isVirtual() && 
+        std::distance(MRI->use_nodbg_begin(Def), MRI->use_nodbg_end()) > 1) 
+      report("Unspillable Terminator expected to have at most one use!", MI); 
+  } 
+ 
   // A fully-formed DBG_VALUE must have a location. Ignore partially formed
   // DBG_VALUEs: these are convenient to use in tests, but should never get
   // generated.
@@ -1565,11 +1565,11 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
     if (!MI->getDebugLoc())
       report("Missing DebugLoc for debug instruction", MI);
 
-  // Meta instructions should never be the subject of debug value tracking,
-  // they don't create a value in the output program at all.
-  if (MI->isMetaInstruction() && MI->peekDebugInstrNum())
-    report("Metadata instruction should not have a value tracking number", MI);
-
+  // Meta instructions should never be the subject of debug value tracking, 
+  // they don't create a value in the output program at all. 
+  if (MI->isMetaInstruction() && MI->peekDebugInstrNum()) 
+    report("Metadata instruction should not have a value tracking number", MI); 
+ 
   // Check the MachineMemOperands for basic consistency.
   for (MachineMemOperand *Op : MI->memoperands()) {
     if (Op->isLoad() && !MI->mayLoad())
@@ -1645,10 +1645,10 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
     }
 
     auto VerifyStackMapConstant = [&](unsigned Offset) {
-      if (Offset >= MI->getNumOperands()) {
-        report("stack map constant to STATEPOINT is out of range!", MI);
-        return;
-      }
+      if (Offset >= MI->getNumOperands()) { 
+        report("stack map constant to STATEPOINT is out of range!", MI); 
+        return; 
+      } 
       if (!MI->getOperand(Offset - 1).isImm() ||
           MI->getOperand(Offset - 1).getImm() != StackMaps::ConstantOp ||
           !MI->getOperand(Offset).isImm())
@@ -1657,26 +1657,26 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
     VerifyStackMapConstant(SO.getCCIdx());
     VerifyStackMapConstant(SO.getFlagsIdx());
     VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
-    VerifyStackMapConstant(SO.getNumGCPtrIdx());
-    VerifyStackMapConstant(SO.getNumAllocaIdx());
-    VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
-
-    // Verify that all explicit statepoint defs are tied to gc operands as
-    // they are expected to be a relocation of gc operands.
-    unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
-    unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
-    for (unsigned Idx = 0; Idx < MI->getNumDefs(); Idx++) {
-      unsigned UseOpIdx;
-      if (!MI->isRegTiedToUseOperand(Idx, &UseOpIdx)) {
-        report("STATEPOINT defs expected to be tied", MI);
-        break;
-      }
-      if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
-        report("STATEPOINT def tied to non-gc operand", MI);
-        break;
-      }
-    }
-
+    VerifyStackMapConstant(SO.getNumGCPtrIdx()); 
+    VerifyStackMapConstant(SO.getNumAllocaIdx()); 
+    VerifyStackMapConstant(SO.getNumGcMapEntriesIdx()); 
+
+    // Verify that all explicit statepoint defs are tied to gc operands as 
+    // they are expected to be a relocation of gc operands. 
+    unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx(); 
+    unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2; 
+    for (unsigned Idx = 0; Idx < MI->getNumDefs(); Idx++) { 
+      unsigned UseOpIdx; 
+      if (!MI->isRegTiedToUseOperand(Idx, &UseOpIdx)) { 
+        report("STATEPOINT defs expected to be tied", MI); 
+        break; 
+      } 
+      if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) { 
+        report("STATEPOINT def tied to non-gc operand", MI); 
+        break; 
+      } 
+    } 
+ 
     // TODO: verify we have properly encoded deopt arguments
   } break;
   }
@@ -1990,10 +1990,10 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
 }
 
 void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
-                                         unsigned MONum, SlotIndex UseIdx,
-                                         const LiveRange &LR,
-                                         Register VRegOrUnit,
-                                         LaneBitmask LaneMask) {
+                                         unsigned MONum, SlotIndex UseIdx, 
+                                         const LiveRange &LR, 
+                                         Register VRegOrUnit, 
+                                         LaneBitmask LaneMask) { 
   LiveQueryResult LRQ = LR.Query(UseIdx);
   // Check if we have a segment at the use, note however that we only need one
   // live subregister range, the others may be dead.
@@ -2014,11 +2014,11 @@ void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
 }
 
 void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
-                                         unsigned MONum, SlotIndex DefIdx,
-                                         const LiveRange &LR,
-                                         Register VRegOrUnit,
-                                         bool SubRangeCheck,
-                                         LaneBitmask LaneMask) {
+                                         unsigned MONum, SlotIndex DefIdx, 
+                                         const LiveRange &LR, 
+                                         Register VRegOrUnit, 
+                                         bool SubRangeCheck, 
+                                         LaneBitmask LaneMask) { 
   if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
     assert(VNI && "NULL valno is not allowed");
     if (VNI->def != DefIdx) {
@@ -2062,7 +2062,7 @@ void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
 
 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
   const MachineInstr *MI = MO->getParent();
-  const Register Reg = MO->getReg();
+  const Register Reg = MO->getReg(); 
 
   // Both use and def operands can read a register.
   if (MO->readsReg()) {
@@ -2080,9 +2080,9 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
     if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
       SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
       // Check the cached regunit intervals.
-      if (Reg.isPhysical() && !isReserved(Reg)) {
-        for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
-             ++Units) {
+      if (Reg.isPhysical() && !isReserved(Reg)) { 
+        for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid(); 
+             ++Units) { 
           if (MRI->isReservedRegUnit(*Units))
             continue;
           if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
@@ -2228,9 +2228,9 @@ void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
   // Kill any masked registers.
   while (!regMasks.empty()) {
     const uint32_t *Mask = regMasks.pop_back_val();
-    for (Register Reg : regsLive)
-      if (Reg.isPhysical() &&
-          MachineOperand::clobbersPhysReg(Mask, Reg.asMCReg()))
+    for (Register Reg : regsLive) 
+      if (Reg.isPhysical() && 
+          MachineOperand::clobbersPhysReg(Mask, Reg.asMCReg())) 
         regsDead.push_back(Reg);
   }
   set_subtract(regsLive, regsDead);   regsDead.clear();
@@ -2263,7 +2263,7 @@ struct VRegFilter {
   // Add elements to the filter itself. \pre Input set \p FromRegSet must have
   // no duplicates. Both virtual and physical registers are fine.
   template <typename RegSetT> void add(const RegSetT &FromRegSet) {
-    SmallVector<Register, 0> VRegsBuffer;
+    SmallVector<Register, 0> VRegsBuffer; 
     filterAndAdd(FromRegSet, VRegsBuffer);
   }
   // Filter \p FromRegSet through the filter and append passed elements into \p
@@ -2271,13 +2271,13 @@ struct VRegFilter {
   // \returns true if anything changed.
   template <typename RegSetT>
   bool filterAndAdd(const RegSetT &FromRegSet,
-                    SmallVectorImpl<Register> &ToVRegs) {
+                    SmallVectorImpl<Register> &ToVRegs) { 
     unsigned SparseUniverse = Sparse.size();
     unsigned NewSparseUniverse = SparseUniverse;
     unsigned NewDenseSize = Dense.size();
     size_t Begin = ToVRegs.size();
-    for (Register Reg : FromRegSet) {
-      if (!Reg.isVirtual())
+    for (Register Reg : FromRegSet) { 
+      if (!Reg.isVirtual()) 
         continue;
       unsigned Index = Register::virtReg2Index(Reg);
       if (Index < SparseUniverseMax) {
@@ -2301,7 +2301,7 @@ struct VRegFilter {
     Sparse.resize(NewSparseUniverse);
     Dense.reserve(NewDenseSize);
     for (unsigned I = Begin; I < End; ++I) {
-      Register Reg = ToVRegs[I];
+      Register Reg = ToVRegs[I]; 
       unsigned Index = Register::virtReg2Index(Reg);
       if (Index < SparseUniverseMax)
         Sparse.set(Index);
@@ -2334,7 +2334,7 @@ private:
 // universe). filter_b implicitly contains all physical registers at all times.
 class FilteringVRegSet {
   VRegFilter Filter;
-  SmallVector<Register, 0> VRegs;
+  SmallVector<Register, 0> VRegs; 
 
 public:
   // Set-up the filter_b. \pre Input register set \p RS must have no duplicates.
@@ -2360,28 +2360,28 @@ public:
 // can pass through an MBB live, but may not be live every time. It is assumed
 // that all vregsPassed sets are empty before the call.
 void MachineVerifier::calcRegsPassed() {
-  if (MF->empty())
+  if (MF->empty()) 
     // ReversePostOrderTraversal doesn't handle empty functions.
     return;
-
-  for (const MachineBasicBlock *MB :
+ 
+  for (const MachineBasicBlock *MB : 
        ReversePostOrderTraversal<const MachineFunction *>(MF)) {
-    FilteringVRegSet VRegs;
-    BBInfo &Info = MBBInfoMap[MB];
-    assert(Info.reachable);
-
-    VRegs.addToFilter(Info.regsKilled);
-    VRegs.addToFilter(Info.regsLiveOut);
-    for (const MachineBasicBlock *Pred : MB->predecessors()) {
-      const BBInfo &PredInfo = MBBInfoMap[Pred];
-      if (!PredInfo.reachable)
+    FilteringVRegSet VRegs; 
+    BBInfo &Info = MBBInfoMap[MB]; 
+    assert(Info.reachable); 
+
+    VRegs.addToFilter(Info.regsKilled); 
+    VRegs.addToFilter(Info.regsLiveOut); 
+    for (const MachineBasicBlock *Pred : MB->predecessors()) { 
+      const BBInfo &PredInfo = MBBInfoMap[Pred]; 
+      if (!PredInfo.reachable) 
         continue;
-
-      VRegs.add(PredInfo.regsLiveOut);
-      VRegs.add(PredInfo.vregsPassed);
+ 
+      VRegs.add(PredInfo.regsLiveOut); 
+      VRegs.add(PredInfo.vregsPassed); 
     }
-    Info.vregsPassed.reserve(VRegs.size());
-    Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
+    Info.vregsPassed.reserve(VRegs.size()); 
+    Info.vregsPassed.insert(VRegs.begin(), VRegs.end()); 
   }
 }
 
@@ -2398,23 +2398,23 @@ void MachineVerifier::calcRegsRequired() {
       if (PInfo.addRequired(MInfo.vregsLiveIn))
         todo.insert(Pred);
     }
-
-    // Handle the PHI node.
-    for (const MachineInstr &MI : MBB.phis()) {
-      for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
-        // Skip those Operands which are undef regs or not regs.
-        if (!MI.getOperand(i).isReg() || !MI.getOperand(i).readsReg())
-          continue;
-
-        // Get register and predecessor for one PHI edge.
-        Register Reg = MI.getOperand(i).getReg();
-        const MachineBasicBlock *Pred = MI.getOperand(i + 1).getMBB();
-
-        BBInfo &PInfo = MBBInfoMap[Pred];
-        if (PInfo.addRequired(Reg))
-          todo.insert(Pred);
-      }
-    }
+ 
+    // Handle the PHI node. 
+    for (const MachineInstr &MI : MBB.phis()) { 
+      for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) { 
+        // Skip those Operands which are undef regs or not regs. 
+        if (!MI.getOperand(i).isReg() || !MI.getOperand(i).readsReg()) 
+          continue; 
+ 
+        // Get register and predecessor for one PHI edge. 
+        Register Reg = MI.getOperand(i).getReg(); 
+        const MachineBasicBlock *Pred = MI.getOperand(i + 1).getMBB(); 
+ 
+        BBInfo &PInfo = MBBInfoMap[Pred]; 
+        if (PInfo.addRequired(Reg)) 
+          todo.insert(Pred); 
+      } 
+    } 
   }
 
   // Iteratively push vregsRequired to predecessors. This will converge to the
@@ -2512,7 +2512,7 @@ void MachineVerifier::visitMachineFunctionAfter() {
   // Check for killed virtual registers that should be live out.
   for (const auto &MBB : *MF) {
     BBInfo &MInfo = MBBInfoMap[&MBB];
-    for (Register VReg : MInfo.vregsRequired)
+    for (Register VReg : MInfo.vregsRequired) 
       if (MInfo.regsKilled.count(VReg)) {
         report("Virtual register killed in block, but needed live out.", &MBB);
         errs() << "Virtual register " << printReg(VReg)
@@ -2522,7 +2522,7 @@ void MachineVerifier::visitMachineFunctionAfter() {
 
   if (!MF->empty()) {
     BBInfo &MInfo = MBBInfoMap[&MF->front()];
-    for (Register VReg : MInfo.vregsRequired) {
+    for (Register VReg : MInfo.vregsRequired) { 
       report("Virtual register defs don't dominate all uses.", MF);
       report_context_vreg(VReg);
     }
@@ -2562,27 +2562,27 @@ void MachineVerifier::visitMachineFunctionAfter() {
   for (auto CSInfo : MF->getCallSitesInfo())
     if (!CSInfo.first->isCall())
       report("Call site info referencing instruction that is not call", MF);
-
-  // If there's debug-info, check that we don't have any duplicate value
-  // tracking numbers.
-  if (MF->getFunction().getSubprogram()) {
-    DenseSet<unsigned> SeenNumbers;
-    for (auto &MBB : *MF) {
-      for (auto &MI : MBB) {
-        if (auto Num = MI.peekDebugInstrNum()) {
-          auto Result = SeenNumbers.insert((unsigned)Num);
-          if (!Result.second)
-            report("Instruction has a duplicated value tracking number", &MI);
-        }
-      }
-    }
-  }
+ 
+  // If there's debug-info, check that we don't have any duplicate value 
+  // tracking numbers. 
+  if (MF->getFunction().getSubprogram()) { 
+    DenseSet<unsigned> SeenNumbers; 
+    for (auto &MBB : *MF) { 
+      for (auto &MI : MBB) { 
+        if (auto Num = MI.peekDebugInstrNum()) { 
+          auto Result = SeenNumbers.insert((unsigned)Num); 
+          if (!Result.second) 
+            report("Instruction has a duplicated value tracking number", &MI); 
+        } 
+      } 
+    } 
+  } 
 }
 
 void MachineVerifier::verifyLiveVariables() {
   assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
-  for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
-    Register Reg = Register::index2VirtReg(I);
+  for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) { 
+    Register Reg = Register::index2VirtReg(I); 
     LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
     for (const auto &MBB : *MF) {
       BBInfo &MInfo = MBBInfoMap[&MBB];
@@ -2607,8 +2607,8 @@ void MachineVerifier::verifyLiveVariables() {
 
 void MachineVerifier::verifyLiveIntervals() {
   assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
-  for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
-    Register Reg = Register::index2VirtReg(I);
+  for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) { 
+    Register Reg = Register::index2VirtReg(I); 
 
     // Spilling and splitting may leave unused registers around. Skip them.
     if (MRI->reg_nodbg_empty(Reg))
@@ -2621,7 +2621,7 @@ void MachineVerifier::verifyLiveIntervals() {
     }
 
     const LiveInterval &LI = LiveInts->getInterval(Reg);
-    assert(Reg == LI.reg() && "Invalid reg to interval mapping");
+    assert(Reg == LI.reg() && "Invalid reg to interval mapping"); 
     verifyLiveInterval(LI);
   }
 
@@ -2632,7 +2632,7 @@ void MachineVerifier::verifyLiveIntervals() {
 }
 
 void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
-                                           const VNInfo *VNI, Register Reg,
+                                           const VNInfo *VNI, Register Reg, 
                                            LaneBitmask LaneMask) {
   if (VNI->isUnused())
     return;
@@ -2725,8 +2725,8 @@ void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
 
 void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
                                              const LiveRange::const_iterator I,
-                                             Register Reg,
-                                             LaneBitmask LaneMask) {
+                                             Register Reg, 
+                                             LaneBitmask LaneMask) { 
   const LiveRange::Segment &S = *I;
   const VNInfo *VNI = S.valno;
   assert(VNI && "Live segment has no valno");
@@ -2937,7 +2937,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
   }
 }
 
-void MachineVerifier::verifyLiveRange(const LiveRange &LR, Register Reg,
+void MachineVerifier::verifyLiveRange(const LiveRange &LR, Register Reg, 
                                       LaneBitmask LaneMask) {
   for (const VNInfo *VNI : LR.valnos)
     verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
@@ -2947,7 +2947,7 @@ void MachineVerifier::verifyLiveRange(const LiveRange &LR, Register Reg,
 }
 
 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
-  Register Reg = LI.reg();
+  Register Reg = LI.reg(); 
   assert(Register::isVirtualRegister(Reg));
   verifyLiveRange(LI, Reg);
 
@@ -2964,10 +2964,10 @@ void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
     }
     if (SR.empty()) {
       report("Subrange must not be empty", MF);
-      report_context(SR, LI.reg(), SR.LaneMask);
+      report_context(SR, LI.reg(), SR.LaneMask); 
     }
     Mask |= SR.LaneMask;
-    verifyLiveRange(SR, LI.reg(), SR.LaneMask);
+    verifyLiveRange(SR, LI.reg(), SR.LaneMask); 
     if (!LI.covers(SR)) {
       report("A Subrange is not covered by the main range", MF);
       report_context(LI);