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author | shadchin <shadchin@yandex-team.ru> | 2022-02-10 16:44:39 +0300 |
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committer | Daniil Cherednik <dcherednik@yandex-team.ru> | 2022-02-10 16:44:39 +0300 |
commit | e9656aae26e0358d5378e5b63dcac5c8dbe0e4d0 (patch) | |
tree | 64175d5cadab313b3e7039ebaa06c5bc3295e274 /contrib/libs/llvm12/lib/CodeGen/BreakFalseDeps.cpp | |
parent | 2598ef1d0aee359b4b6d5fdd1758916d5907d04f (diff) | |
download | ydb-e9656aae26e0358d5378e5b63dcac5c8dbe0e4d0.tar.gz |
Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 2 of 2.
Diffstat (limited to 'contrib/libs/llvm12/lib/CodeGen/BreakFalseDeps.cpp')
-rw-r--r-- | contrib/libs/llvm12/lib/CodeGen/BreakFalseDeps.cpp | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/contrib/libs/llvm12/lib/CodeGen/BreakFalseDeps.cpp b/contrib/libs/llvm12/lib/CodeGen/BreakFalseDeps.cpp index 7454888e40..b11db3e657 100644 --- a/contrib/libs/llvm12/lib/CodeGen/BreakFalseDeps.cpp +++ b/contrib/libs/llvm12/lib/CodeGen/BreakFalseDeps.cpp @@ -118,7 +118,7 @@ bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx, if (!MO.isRenamable()) return false; - MCRegister OriginalReg = MO.getReg().asMCReg(); + MCRegister OriginalReg = MO.getReg().asMCReg(); // Update only undef operands that have reg units that are mapped to one root. for (MCRegUnitIterator Unit(OriginalReg, TRI); Unit.isValid(); ++Unit) { @@ -171,8 +171,8 @@ bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx, bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, unsigned Pref) { - MCRegister Reg = MI->getOperand(OpIdx).getReg().asMCReg(); - unsigned Clearance = RDA->getClearance(MI, Reg); + MCRegister Reg = MI->getOperand(OpIdx).getReg().asMCReg(); + unsigned Clearance = RDA->getClearance(MI, Reg); LLVM_DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref); if (Pref > Clearance) { @@ -186,24 +186,24 @@ bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, void BreakFalseDeps::processDefs(MachineInstr *MI) { assert(!MI->isDebugInstr() && "Won't process debug values"); - const MCInstrDesc &MCID = MI->getDesc(); - + const MCInstrDesc &MCID = MI->getDesc(); + // Break dependence on undef uses. Do this before updating LiveRegs below. // This can remove a false dependence with no additional instructions. - for (unsigned i = MCID.getNumDefs(), e = MCID.getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg() || !MO.getReg() || !MO.isUse() || !MO.isUndef()) - continue; - - unsigned Pref = TII->getUndefRegClearance(*MI, i, TRI); - if (Pref) { - bool HadTrueDependency = pickBestRegisterForUndef(MI, i, Pref); - // We don't need to bother trying to break a dependency if this - // instruction has a true dependency on that register through another - // operand - we'll have to wait for it to be available regardless. - if (!HadTrueDependency && shouldBreakDependence(MI, i, Pref)) - UndefReads.push_back(std::make_pair(MI, i)); - } + for (unsigned i = MCID.getNumDefs(), e = MCID.getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (!MO.isReg() || !MO.getReg() || !MO.isUse() || !MO.isUndef()) + continue; + + unsigned Pref = TII->getUndefRegClearance(*MI, i, TRI); + if (Pref) { + bool HadTrueDependency = pickBestRegisterForUndef(MI, i, Pref); + // We don't need to bother trying to break a dependency if this + // instruction has a true dependency on that register through another + // operand - we'll have to wait for it to be available regardless. + if (!HadTrueDependency && shouldBreakDependence(MI, i, Pref)) + UndefReads.push_back(std::make_pair(MI, i)); + } } // The code below allows the target to create a new instruction to break the |