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author | shadchin <shadchin@yandex-team.ru> | 2022-02-10 16:44:39 +0300 |
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committer | Daniil Cherednik <dcherednik@yandex-team.ru> | 2022-02-10 16:44:39 +0300 |
commit | e9656aae26e0358d5378e5b63dcac5c8dbe0e4d0 (patch) | |
tree | 64175d5cadab313b3e7039ebaa06c5bc3295e274 /contrib/libs/llvm12/lib/CodeGen/AllocationOrder.cpp | |
parent | 2598ef1d0aee359b4b6d5fdd1758916d5907d04f (diff) | |
download | ydb-e9656aae26e0358d5378e5b63dcac5c8dbe0e4d0.tar.gz |
Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 2 of 2.
Diffstat (limited to 'contrib/libs/llvm12/lib/CodeGen/AllocationOrder.cpp')
-rw-r--r-- | contrib/libs/llvm12/lib/CodeGen/AllocationOrder.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/contrib/libs/llvm12/lib/CodeGen/AllocationOrder.cpp b/contrib/libs/llvm12/lib/CodeGen/AllocationOrder.cpp index 137c8f4f0e..2aef1234ac 100644 --- a/contrib/libs/llvm12/lib/CodeGen/AllocationOrder.cpp +++ b/contrib/libs/llvm12/lib/CodeGen/AllocationOrder.cpp @@ -26,15 +26,15 @@ using namespace llvm; #define DEBUG_TYPE "regalloc" // Compare VirtRegMap::getRegAllocPref(). -AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM, - const RegisterClassInfo &RegClassInfo, - const LiveRegMatrix *Matrix) { +AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM, + const RegisterClassInfo &RegClassInfo, + const LiveRegMatrix *Matrix) { const MachineFunction &MF = VRM.getMachineFunction(); const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); - auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); - SmallVector<MCPhysReg, 16> Hints; - bool HardHints = - TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix); + auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); + SmallVector<MCPhysReg, 16> Hints; + bool HardHints = + TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix); LLVM_DEBUG({ if (!Hints.empty()) { @@ -49,5 +49,5 @@ AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM, assert(is_contained(Order, Hints[I]) && "Target hint is outside allocation order."); #endif - return AllocationOrder(std::move(Hints), Order, HardHints); + return AllocationOrder(std::move(Hints), Order, HardHints); } |