Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 2 of 2.

1 files changed, 66 insertions, 66 deletions

diff --git a/contrib/libs/llvm12/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h b/contrib/libs/llvm12/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
index b5885ff663..e3202fc976 100644
--- a/contrib/libs/llvm12/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
+++ b/contrib/libs/llvm12/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
@@ -161,26 +161,26 @@ bool InstructionSelector::executeMatchTable(
       break;
     }
 
-    case GIM_CheckOpcode: 
-    case GIM_CheckOpcodeIsEither: { 
+    case GIM_CheckOpcode:
+    case GIM_CheckOpcodeIsEither: {
       int64_t InsnID = MatchTable[CurrentIdx++];
-      int64_t Expected0 = MatchTable[CurrentIdx++]; 
-      int64_t Expected1 = -1; 
-      if (MatcherOpcode == GIM_CheckOpcodeIsEither) 
-        Expected1 = MatchTable[CurrentIdx++]; 
+      int64_t Expected0 = MatchTable[CurrentIdx++];
+      int64_t Expected1 = -1;
+      if (MatcherOpcode == GIM_CheckOpcodeIsEither)
+        Expected1 = MatchTable[CurrentIdx++];
 
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       unsigned Opcode = State.MIs[InsnID]->getOpcode();
 
       DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
-        dbgs() << CurrentIdx << ": GIM_CheckOpcode(MIs[" << InsnID 
-        << "], ExpectedOpcode=" << Expected0; 
-        if (MatcherOpcode == GIM_CheckOpcodeIsEither) 
-          dbgs() << " || " << Expected1; 
-        dbgs() << ") // Got=" << Opcode << "\n"; 
-      ); 
- 
-      if (Opcode != Expected0 && Opcode != Expected1) { 
+        dbgs() << CurrentIdx << ": GIM_CheckOpcode(MIs[" << InsnID
+        << "], ExpectedOpcode=" << Expected0;
+        if (MatcherOpcode == GIM_CheckOpcodeIsEither)
+          dbgs() << " || " << Expected1;
+        dbgs() << ") // Got=" << Opcode << "\n";
+      );
+
+      if (Opcode != Expected0 && Opcode != Expected1) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       }
@@ -207,7 +207,7 @@ bool InstructionSelector::executeMatchTable(
       CurrentIdx = MatchTable[CurrentIdx + (Opcode - LowerBound)];
       if (!CurrentIdx) {
         CurrentIdx = Default;
-        break; 
+        break;
       }
       OnFailResumeAt.push_back(Default);
       break;
@@ -335,35 +335,35 @@ bool InstructionSelector::executeMatchTable(
           return false;
       break;
     }
-    case GIM_CheckIsBuildVectorAllOnes: 
-    case GIM_CheckIsBuildVectorAllZeros: { 
-      int64_t InsnID = MatchTable[CurrentIdx++]; 
- 
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(), 
-                      dbgs() << CurrentIdx 
-                             << ": GIM_CheckBuildVectorAll{Zeros|Ones}(MIs[" 
-                             << InsnID << "])\n"); 
-      assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 
- 
-      const MachineInstr *MI = State.MIs[InsnID]; 
-      assert((MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR || 
-              MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR_TRUNC) && 
-             "Expected G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC"); 
- 
-      if (MatcherOpcode == GIM_CheckIsBuildVectorAllOnes) { 
-        if (!isBuildVectorAllOnes(*MI, MRI)) { 
-          if (handleReject() == RejectAndGiveUp) 
-            return false; 
-        } 
-      } else { 
-        if (!isBuildVectorAllZeros(*MI, MRI)) { 
-          if (handleReject() == RejectAndGiveUp) 
-            return false; 
-        } 
-      } 
- 
-      break; 
-    } 
+    case GIM_CheckIsBuildVectorAllOnes:
+    case GIM_CheckIsBuildVectorAllZeros: {
+      int64_t InsnID = MatchTable[CurrentIdx++];
+
+      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+                      dbgs() << CurrentIdx
+                             << ": GIM_CheckBuildVectorAll{Zeros|Ones}(MIs["
+                             << InsnID << "])\n");
+      assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
+
+      const MachineInstr *MI = State.MIs[InsnID];
+      assert((MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR ||
+              MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR_TRUNC) &&
+             "Expected G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC");
+
+      if (MatcherOpcode == GIM_CheckIsBuildVectorAllOnes) {
+        if (!isBuildVectorAllOnes(*MI, MRI)) {
+          if (handleReject() == RejectAndGiveUp)
+            return false;
+        }
+      } else {
+        if (!isBuildVectorAllZeros(*MI, MRI)) {
+          if (handleReject() == RejectAndGiveUp)
+            return false;
+        }
+      }
+
+      break;
+    }
     case GIM_CheckCxxInsnPredicate: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t Predicate = MatchTable[CurrentIdx++];
@@ -374,8 +374,8 @@ bool InstructionSelector::executeMatchTable(
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       assert(Predicate > GIPFP_MI_Invalid && "Expected a valid predicate");
 
-      if (!testMIPredicate_MI(Predicate, *State.MIs[InsnID], 
-                              State.RecordedOperands)) 
+      if (!testMIPredicate_MI(Predicate, *State.MIs[InsnID],
+                              State.RecordedOperands))
         if (handleReject() == RejectAndGiveUp)
           return false;
       break;
@@ -625,20 +625,20 @@ bool InstructionSelector::executeMatchTable(
 
       break;
     }
-    case GIM_RecordNamedOperand: { 
-      int64_t InsnID = MatchTable[CurrentIdx++]; 
-      int64_t OpIdx = MatchTable[CurrentIdx++]; 
-      uint64_t StoreIdx = MatchTable[CurrentIdx++]; 
- 
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(), 
-                      dbgs() << CurrentIdx << ": GIM_RecordNamedOperand(MIs[" 
-                             << InsnID << "]->getOperand(" << OpIdx 
-                             << "), StoreIdx=" << StoreIdx << ")\n"); 
-      assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); 
-      assert(StoreIdx < State.RecordedOperands.size() && "Index out of range"); 
-      State.RecordedOperands[StoreIdx] = &State.MIs[InsnID]->getOperand(OpIdx); 
-      break; 
-    } 
+    case GIM_RecordNamedOperand: {
+      int64_t InsnID = MatchTable[CurrentIdx++];
+      int64_t OpIdx = MatchTable[CurrentIdx++];
+      uint64_t StoreIdx = MatchTable[CurrentIdx++];
+
+      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+                      dbgs() << CurrentIdx << ": GIM_RecordNamedOperand(MIs["
+                             << InsnID << "]->getOperand(" << OpIdx
+                             << "), StoreIdx=" << StoreIdx << ")\n");
+      assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
+      assert(StoreIdx < State.RecordedOperands.size() && "Index out of range");
+      State.RecordedOperands[StoreIdx] = &State.MIs[InsnID]->getOperand(OpIdx);
+      break;
+    }
     case GIM_CheckRegBankForClass: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
@@ -1065,12 +1065,12 @@ bool InstructionSelector::executeMatchTable(
       int64_t OpIdx = MatchTable[CurrentIdx++];
       int64_t RCEnum = MatchTable[CurrentIdx++];
       assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
-      MachineInstr &I = *OutMIs[InsnID].getInstr(); 
-      MachineFunction &MF = *I.getParent()->getParent(); 
-      MachineRegisterInfo &MRI = MF.getRegInfo(); 
-      const TargetRegisterClass &RC = *TRI.getRegClass(RCEnum); 
-      MachineOperand &MO = I.getOperand(OpIdx); 
-      constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, MO); 
+      MachineInstr &I = *OutMIs[InsnID].getInstr();
+      MachineFunction &MF = *I.getParent()->getParent();
+      MachineRegisterInfo &MRI = MF.getRegInfo();
+      const TargetRegisterClass &RC = *TRI.getRegClass(RCEnum);
+      MachineOperand &MO = I.getOperand(OpIdx);
+      constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, MO);
       DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
                       dbgs() << CurrentIdx << ": GIR_ConstrainOperandRC(OutMIs["
                              << InsnID << "], " << OpIdx << ", " << RCEnum