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authorrobot-contrib <robot-contrib@yandex-team.com>2023-11-11 02:21:37 +0300
committerrobot-contrib <robot-contrib@yandex-team.com>2023-11-11 02:40:39 +0300
commitc9eb66546bc5c72ff6a4424f5c73ada67d0aeaa8 (patch)
tree4a18f83f5979766f6a360805a97500e9b2beeb75 /contrib/libs/linux-headers/linux/elf.h
parent638336990198a7f36d43cfd21a42b25d9dcb6efc (diff)
downloadydb-c9eb66546bc5c72ff6a4424f5c73ada67d0aeaa8.tar.gz
Update contrib/libs/linux-headers to 6.5.9
Diffstat (limited to 'contrib/libs/linux-headers/linux/elf.h')
-rw-r--r--contrib/libs/linux-headers/linux/elf.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/contrib/libs/linux-headers/linux/elf.h b/contrib/libs/linux-headers/linux/elf.h
index a1ed8bb028..0b23445430 100644
--- a/contrib/libs/linux-headers/linux/elf.h
+++ b/contrib/libs/linux-headers/linux/elf.h
@@ -372,7 +372,8 @@ typedef struct elf64_shdr {
* Notes used in ET_CORE. Architectures export some of the arch register sets
* using the corresponding note types via the PTRACE_GETREGSET and
* PTRACE_SETREGSET requests.
- * The note name for all these is "LINUX".
+ * The note name for these types is "LINUX", except NT_PRFPREG that is named
+ * "CORE".
*/
#define NT_PRSTATUS 1
#define NT_PRFPREG 2
@@ -403,6 +404,8 @@ typedef struct elf64_shdr {
#define NT_PPC_TM_CPPR 0x10e /* TM checkpointed Program Priority Register */
#define NT_PPC_TM_CDSCR 0x10f /* TM checkpointed Data Stream Control Register */
#define NT_PPC_PKEY 0x110 /* Memory Protection Keys registers */
+#define NT_PPC_DEXCR 0x111 /* PowerPC DEXCR registers */
+#define NT_PPC_HASHKEYR 0x112 /* PowerPC HASHKEYR register */
#define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */
#define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */
#define NT_X86_XSTATE 0x202 /* x86 extended state using xsave */
@@ -440,6 +443,8 @@ typedef struct elf64_shdr {
#define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */
#define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode */
#define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */
+#define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */
+#define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */
#define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */
#define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */
#define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */