Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 2 of 2.

2 files changed, 174 insertions, 174 deletions

diff --git a/contrib/libs/libunwind/include/__libunwind_config.h b/contrib/libs/libunwind/include/__libunwind_config.h
index d907fdf0e9..e87bcf4003 100644
--- a/contrib/libs/libunwind/include/__libunwind_config.h
+++ b/contrib/libs/libunwind/include/__libunwind_config.h
@@ -26,12 +26,12 @@
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC64   31
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_HEXAGON   34
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV     64
-#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE        143 
+#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE        143
 
 #if defined(_LIBUNWIND_IS_NATIVE_ONLY)
-# if defined(__linux__) 
-#  define _LIBUNWIND_TARGET_LINUX 1 
-# endif 
+# if defined(__linux__)
+#  define _LIBUNWIND_TARGET_LINUX 1
+# endif
 # if defined(__i386__)
 #  define _LIBUNWIND_TARGET_I386
 #  define _LIBUNWIND_CONTEXT_SIZE 8
@@ -138,26 +138,26 @@
   #define _LIBUNWIND_CONTEXT_SIZE 16
   #define _LIBUNWIND_CURSOR_SIZE 23
 # elif defined(__riscv)
-#  define _LIBUNWIND_TARGET_RISCV 1 
-#  if defined(__riscv_flen) 
-#   define RISCV_FLEN __riscv_flen 
+#  define _LIBUNWIND_TARGET_RISCV 1
+#  if defined(__riscv_flen)
+#   define RISCV_FLEN __riscv_flen
+#  else
+#   define RISCV_FLEN 0
+#  endif
+#  define _LIBUNWIND_CONTEXT_SIZE (32 * (__riscv_xlen + RISCV_FLEN) / 64)
+#  if __riscv_xlen == 32
+#   define _LIBUNWIND_CURSOR_SIZE (_LIBUNWIND_CONTEXT_SIZE + 7)
+#  elif __riscv_xlen == 64
+#   define _LIBUNWIND_CURSOR_SIZE (_LIBUNWIND_CONTEXT_SIZE + 12)
 #  else
-#   define RISCV_FLEN 0 
+#   error "Unsupported RISC-V ABI"
 #  endif
-#  define _LIBUNWIND_CONTEXT_SIZE (32 * (__riscv_xlen + RISCV_FLEN) / 64) 
-#  if __riscv_xlen == 32 
-#   define _LIBUNWIND_CURSOR_SIZE (_LIBUNWIND_CONTEXT_SIZE + 7) 
-#  elif __riscv_xlen == 64 
-#   define _LIBUNWIND_CURSOR_SIZE (_LIBUNWIND_CONTEXT_SIZE + 12) 
-#  else 
-#   error "Unsupported RISC-V ABI" 
-#  endif 
 # define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV
-# elif defined(__ve__) 
-#  define _LIBUNWIND_TARGET_VE 1 
-#  define _LIBUNWIND_CONTEXT_SIZE 67 
-#  define _LIBUNWIND_CURSOR_SIZE 79 
-#  define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE 
+# elif defined(__ve__)
+#  define _LIBUNWIND_TARGET_VE 1
+#  define _LIBUNWIND_CONTEXT_SIZE 67
+#  define _LIBUNWIND_CURSOR_SIZE 79
+#  define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE
 # else
 #  error "Unsupported architecture."
 # endif
@@ -175,7 +175,7 @@
 # define _LIBUNWIND_TARGET_SPARC64 1
 # define _LIBUNWIND_TARGET_HEXAGON 1
 # define _LIBUNWIND_TARGET_RISCV 1
-# define _LIBUNWIND_TARGET_VE 1 
+# define _LIBUNWIND_TARGET_VE 1
 # define _LIBUNWIND_CONTEXT_SIZE 167
 # define _LIBUNWIND_CURSOR_SIZE 179
 # define _LIBUNWIND_HIGHEST_DWARF_REGISTER 287
diff --git a/contrib/libs/libunwind/include/libunwind.h b/contrib/libs/libunwind/include/libunwind.h
index 1166e0ffbb..8303c1a04c 100644
--- a/contrib/libs/libunwind/include/libunwind.h
+++ b/contrib/libs/libunwind/include/libunwind.h
@@ -1022,156 +1022,156 @@ enum {
   UNW_RISCV_F31 = 63,
 };
 
-// VE register numbers 
-enum { 
-  UNW_VE_S0   = 0, 
-  UNW_VE_S1   = 1, 
-  UNW_VE_S2   = 2, 
-  UNW_VE_S3   = 3, 
-  UNW_VE_S4   = 4, 
-  UNW_VE_S5   = 5, 
-  UNW_VE_S6   = 6, 
-  UNW_VE_S7   = 7, 
-  UNW_VE_S8   = 8, 
-  UNW_VE_S9   = 9, 
-  UNW_VE_S10  = 10, 
-  UNW_VE_S11  = 11, 
-  UNW_VE_S12  = 12, 
-  UNW_VE_S13  = 13, 
-  UNW_VE_S14  = 14, 
-  UNW_VE_S15  = 15, 
-  UNW_VE_S16  = 16, 
-  UNW_VE_S17  = 17, 
-  UNW_VE_S18  = 18, 
-  UNW_VE_S19  = 19, 
-  UNW_VE_S20  = 20, 
-  UNW_VE_S21  = 21, 
-  UNW_VE_S22  = 22, 
-  UNW_VE_S23  = 23, 
-  UNW_VE_S24  = 24, 
-  UNW_VE_S25  = 25, 
-  UNW_VE_S26  = 26, 
-  UNW_VE_S27  = 27, 
-  UNW_VE_S28  = 28, 
-  UNW_VE_S29  = 29, 
-  UNW_VE_S30  = 30, 
-  UNW_VE_S31  = 31, 
-  UNW_VE_S32  = 32, 
-  UNW_VE_S33  = 33, 
-  UNW_VE_S34  = 34, 
-  UNW_VE_S35  = 35, 
-  UNW_VE_S36  = 36, 
-  UNW_VE_S37  = 37, 
-  UNW_VE_S38  = 38, 
-  UNW_VE_S39  = 39, 
-  UNW_VE_S40  = 40, 
-  UNW_VE_S41  = 41, 
-  UNW_VE_S42  = 42, 
-  UNW_VE_S43  = 43, 
-  UNW_VE_S44  = 44, 
-  UNW_VE_S45  = 45, 
-  UNW_VE_S46  = 46, 
-  UNW_VE_S47  = 47, 
-  UNW_VE_S48  = 48, 
-  UNW_VE_S49  = 49, 
-  UNW_VE_S50  = 50, 
-  UNW_VE_S51  = 51, 
-  UNW_VE_S52  = 52, 
-  UNW_VE_S53  = 53, 
-  UNW_VE_S54  = 54, 
-  UNW_VE_S55  = 55, 
-  UNW_VE_S56  = 56, 
-  UNW_VE_S57  = 57, 
-  UNW_VE_S58  = 58, 
-  UNW_VE_S59  = 59, 
-  UNW_VE_S60  = 60, 
-  UNW_VE_S61  = 61, 
-  UNW_VE_S62  = 62, 
-  UNW_VE_S63  = 63, 
-  UNW_VE_V0   = 64 + 0, 
-  UNW_VE_V1   = 64 + 1, 
-  UNW_VE_V2   = 64 + 2, 
-  UNW_VE_V3   = 64 + 3, 
-  UNW_VE_V4   = 64 + 4, 
-  UNW_VE_V5   = 64 + 5, 
-  UNW_VE_V6   = 64 + 6, 
-  UNW_VE_V7   = 64 + 7, 
-  UNW_VE_V8   = 64 + 8, 
-  UNW_VE_V9   = 64 + 9, 
-  UNW_VE_V10  = 64 + 10, 
-  UNW_VE_V11  = 64 + 11, 
-  UNW_VE_V12  = 64 + 12, 
-  UNW_VE_V13  = 64 + 13, 
-  UNW_VE_V14  = 64 + 14, 
-  UNW_VE_V15  = 64 + 15, 
-  UNW_VE_V16  = 64 + 16, 
-  UNW_VE_V17  = 64 + 17, 
-  UNW_VE_V18  = 64 + 18, 
-  UNW_VE_V19  = 64 + 19, 
-  UNW_VE_V20  = 64 + 20, 
-  UNW_VE_V21  = 64 + 21, 
-  UNW_VE_V22  = 64 + 22, 
-  UNW_VE_V23  = 64 + 23, 
-  UNW_VE_V24  = 64 + 24, 
-  UNW_VE_V25  = 64 + 25, 
-  UNW_VE_V26  = 64 + 26, 
-  UNW_VE_V27  = 64 + 27, 
-  UNW_VE_V28  = 64 + 28, 
-  UNW_VE_V29  = 64 + 29, 
-  UNW_VE_V30  = 64 + 30, 
-  UNW_VE_V31  = 64 + 31, 
-  UNW_VE_V32  = 64 + 32, 
-  UNW_VE_V33  = 64 + 33, 
-  UNW_VE_V34  = 64 + 34, 
-  UNW_VE_V35  = 64 + 35, 
-  UNW_VE_V36  = 64 + 36, 
-  UNW_VE_V37  = 64 + 37, 
-  UNW_VE_V38  = 64 + 38, 
-  UNW_VE_V39  = 64 + 39, 
-  UNW_VE_V40  = 64 + 40, 
-  UNW_VE_V41  = 64 + 41, 
-  UNW_VE_V42  = 64 + 42, 
-  UNW_VE_V43  = 64 + 43, 
-  UNW_VE_V44  = 64 + 44, 
-  UNW_VE_V45  = 64 + 45, 
-  UNW_VE_V46  = 64 + 46, 
-  UNW_VE_V47  = 64 + 47, 
-  UNW_VE_V48  = 64 + 48, 
-  UNW_VE_V49  = 64 + 49, 
-  UNW_VE_V50  = 64 + 50, 
-  UNW_VE_V51  = 64 + 51, 
-  UNW_VE_V52  = 64 + 52, 
-  UNW_VE_V53  = 64 + 53, 
-  UNW_VE_V54  = 64 + 54, 
-  UNW_VE_V55  = 64 + 55, 
-  UNW_VE_V56  = 64 + 56, 
-  UNW_VE_V57  = 64 + 57, 
-  UNW_VE_V58  = 64 + 58, 
-  UNW_VE_V59  = 64 + 59, 
-  UNW_VE_V60  = 64 + 60, 
-  UNW_VE_V61  = 64 + 61, 
-  UNW_VE_V62  = 64 + 62, 
-  UNW_VE_V63  = 64 + 63, 
-  UNW_VE_VM0  = 128 + 0, 
-  UNW_VE_VM1  = 128 + 1, 
-  UNW_VE_VM2  = 128 + 2, 
-  UNW_VE_VM3  = 128 + 3, 
-  UNW_VE_VM4  = 128 + 4, 
-  UNW_VE_VM5  = 128 + 5, 
-  UNW_VE_VM6  = 128 + 6, 
-  UNW_VE_VM7  = 128 + 7, 
-  UNW_VE_VM8  = 128 + 8, 
-  UNW_VE_VM9  = 128 + 9, 
-  UNW_VE_VM10 = 128 + 10, 
-  UNW_VE_VM11 = 128 + 11, 
-  UNW_VE_VM12 = 128 + 12, 
-  UNW_VE_VM13 = 128 + 13, 
-  UNW_VE_VM14 = 128 + 14, 
-  UNW_VE_VM15 = 128 + 15, // = 143 
- 
-  // Following registers don't have DWARF register numbers. 
-  UNW_VE_VIXR = 144, 
-  UNW_VE_VL   = 145, 
-}; 
- 
+// VE register numbers
+enum {
+  UNW_VE_S0   = 0,
+  UNW_VE_S1   = 1,
+  UNW_VE_S2   = 2,
+  UNW_VE_S3   = 3,
+  UNW_VE_S4   = 4,
+  UNW_VE_S5   = 5,
+  UNW_VE_S6   = 6,
+  UNW_VE_S7   = 7,
+  UNW_VE_S8   = 8,
+  UNW_VE_S9   = 9,
+  UNW_VE_S10  = 10,
+  UNW_VE_S11  = 11,
+  UNW_VE_S12  = 12,
+  UNW_VE_S13  = 13,
+  UNW_VE_S14  = 14,
+  UNW_VE_S15  = 15,
+  UNW_VE_S16  = 16,
+  UNW_VE_S17  = 17,
+  UNW_VE_S18  = 18,
+  UNW_VE_S19  = 19,
+  UNW_VE_S20  = 20,
+  UNW_VE_S21  = 21,
+  UNW_VE_S22  = 22,
+  UNW_VE_S23  = 23,
+  UNW_VE_S24  = 24,
+  UNW_VE_S25  = 25,
+  UNW_VE_S26  = 26,
+  UNW_VE_S27  = 27,
+  UNW_VE_S28  = 28,
+  UNW_VE_S29  = 29,
+  UNW_VE_S30  = 30,
+  UNW_VE_S31  = 31,
+  UNW_VE_S32  = 32,
+  UNW_VE_S33  = 33,
+  UNW_VE_S34  = 34,
+  UNW_VE_S35  = 35,
+  UNW_VE_S36  = 36,
+  UNW_VE_S37  = 37,
+  UNW_VE_S38  = 38,
+  UNW_VE_S39  = 39,
+  UNW_VE_S40  = 40,
+  UNW_VE_S41  = 41,
+  UNW_VE_S42  = 42,
+  UNW_VE_S43  = 43,
+  UNW_VE_S44  = 44,
+  UNW_VE_S45  = 45,
+  UNW_VE_S46  = 46,
+  UNW_VE_S47  = 47,
+  UNW_VE_S48  = 48,
+  UNW_VE_S49  = 49,
+  UNW_VE_S50  = 50,
+  UNW_VE_S51  = 51,
+  UNW_VE_S52  = 52,
+  UNW_VE_S53  = 53,
+  UNW_VE_S54  = 54,
+  UNW_VE_S55  = 55,
+  UNW_VE_S56  = 56,
+  UNW_VE_S57  = 57,
+  UNW_VE_S58  = 58,
+  UNW_VE_S59  = 59,
+  UNW_VE_S60  = 60,
+  UNW_VE_S61  = 61,
+  UNW_VE_S62  = 62,
+  UNW_VE_S63  = 63,
+  UNW_VE_V0   = 64 + 0,
+  UNW_VE_V1   = 64 + 1,
+  UNW_VE_V2   = 64 + 2,
+  UNW_VE_V3   = 64 + 3,
+  UNW_VE_V4   = 64 + 4,
+  UNW_VE_V5   = 64 + 5,
+  UNW_VE_V6   = 64 + 6,
+  UNW_VE_V7   = 64 + 7,
+  UNW_VE_V8   = 64 + 8,
+  UNW_VE_V9   = 64 + 9,
+  UNW_VE_V10  = 64 + 10,
+  UNW_VE_V11  = 64 + 11,
+  UNW_VE_V12  = 64 + 12,
+  UNW_VE_V13  = 64 + 13,
+  UNW_VE_V14  = 64 + 14,
+  UNW_VE_V15  = 64 + 15,
+  UNW_VE_V16  = 64 + 16,
+  UNW_VE_V17  = 64 + 17,
+  UNW_VE_V18  = 64 + 18,
+  UNW_VE_V19  = 64 + 19,
+  UNW_VE_V20  = 64 + 20,
+  UNW_VE_V21  = 64 + 21,
+  UNW_VE_V22  = 64 + 22,
+  UNW_VE_V23  = 64 + 23,
+  UNW_VE_V24  = 64 + 24,
+  UNW_VE_V25  = 64 + 25,
+  UNW_VE_V26  = 64 + 26,
+  UNW_VE_V27  = 64 + 27,
+  UNW_VE_V28  = 64 + 28,
+  UNW_VE_V29  = 64 + 29,
+  UNW_VE_V30  = 64 + 30,
+  UNW_VE_V31  = 64 + 31,
+  UNW_VE_V32  = 64 + 32,
+  UNW_VE_V33  = 64 + 33,
+  UNW_VE_V34  = 64 + 34,
+  UNW_VE_V35  = 64 + 35,
+  UNW_VE_V36  = 64 + 36,
+  UNW_VE_V37  = 64 + 37,
+  UNW_VE_V38  = 64 + 38,
+  UNW_VE_V39  = 64 + 39,
+  UNW_VE_V40  = 64 + 40,
+  UNW_VE_V41  = 64 + 41,
+  UNW_VE_V42  = 64 + 42,
+  UNW_VE_V43  = 64 + 43,
+  UNW_VE_V44  = 64 + 44,
+  UNW_VE_V45  = 64 + 45,
+  UNW_VE_V46  = 64 + 46,
+  UNW_VE_V47  = 64 + 47,
+  UNW_VE_V48  = 64 + 48,
+  UNW_VE_V49  = 64 + 49,
+  UNW_VE_V50  = 64 + 50,
+  UNW_VE_V51  = 64 + 51,
+  UNW_VE_V52  = 64 + 52,
+  UNW_VE_V53  = 64 + 53,
+  UNW_VE_V54  = 64 + 54,
+  UNW_VE_V55  = 64 + 55,
+  UNW_VE_V56  = 64 + 56,
+  UNW_VE_V57  = 64 + 57,
+  UNW_VE_V58  = 64 + 58,
+  UNW_VE_V59  = 64 + 59,
+  UNW_VE_V60  = 64 + 60,
+  UNW_VE_V61  = 64 + 61,
+  UNW_VE_V62  = 64 + 62,
+  UNW_VE_V63  = 64 + 63,
+  UNW_VE_VM0  = 128 + 0,
+  UNW_VE_VM1  = 128 + 1,
+  UNW_VE_VM2  = 128 + 2,
+  UNW_VE_VM3  = 128 + 3,
+  UNW_VE_VM4  = 128 + 4,
+  UNW_VE_VM5  = 128 + 5,
+  UNW_VE_VM6  = 128 + 6,
+  UNW_VE_VM7  = 128 + 7,
+  UNW_VE_VM8  = 128 + 8,
+  UNW_VE_VM9  = 128 + 9,
+  UNW_VE_VM10 = 128 + 10,
+  UNW_VE_VM11 = 128 + 11,
+  UNW_VE_VM12 = 128 + 12,
+  UNW_VE_VM13 = 128 + 13,
+  UNW_VE_VM14 = 128 + 14,
+  UNW_VE_VM15 = 128 + 15, // = 143
+
+  // Following registers don't have DWARF register numbers.
+  UNW_VE_VIXR = 144,
+  UNW_VE_VL   = 145,
+};
+
 #endif