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authordanlark <danlark@yandex-team.ru>2022-02-10 16:46:08 +0300
committerDaniil Cherednik <dcherednik@yandex-team.ru>2022-02-10 16:46:08 +0300
commit3426a9bc7f169ae9da54cef557ad2a33f6e8eee0 (patch)
tree26154e1e9990f1bb4525d3e3fb5b6dac2c2c1da2 /contrib/libs/libaio/syscall-arm64.h
parentcb68f224c46a8ee52ac3fdd2a32534b8bb8dc134 (diff)
downloadydb-3426a9bc7f169ae9da54cef557ad2a33f6e8eee0.tar.gz
Restoring authorship annotation for <danlark@yandex-team.ru>. Commit 1 of 2.
Diffstat (limited to 'contrib/libs/libaio/syscall-arm64.h')
-rw-r--r--contrib/libs/libaio/syscall-arm64.h40
1 files changed, 20 insertions, 20 deletions
diff --git a/contrib/libs/libaio/syscall-arm64.h b/contrib/libs/libaio/syscall-arm64.h
index 031c571824..e36cd73c66 100644
--- a/contrib/libs/libaio/syscall-arm64.h
+++ b/contrib/libs/libaio/syscall-arm64.h
@@ -27,8 +27,8 @@
#define io_syscall1(type,fname,sname,type1,arg1) \
type fname(type1 arg1) { \
__SYS_REG(sname) \
- register long __x0 __asm__("x0") = (long)arg1; \
- register long __res_x0 __asm__("x0"); \
+ register long __x0 __asm__("x0") = (long)arg1; \
+ register long __res_x0 __asm__("x0"); \
__asm__ __volatile__ ( \
__syscall(sname) \
: "=r" (__res_x0) \
@@ -40,9 +40,9 @@ type fname(type1 arg1) { \
#define io_syscall2(type,fname,sname,type1,arg1,type2,arg2) \
type fname(type1 arg1,type2 arg2) { \
__SYS_REG(sname) \
- register long __x0 __asm__("x0") = (long)arg1; \
- register long __x1 __asm__("x1") = (long)arg2; \
- register long __res_x0 __asm__("x0"); \
+ register long __x0 __asm__("x0") = (long)arg1; \
+ register long __x1 __asm__("x1") = (long)arg2; \
+ register long __res_x0 __asm__("x0"); \
__asm__ __volatile__ ( \
__syscall(sname) \
: "=r" (__res_x0) \
@@ -54,10 +54,10 @@ type fname(type1 arg1,type2 arg2) { \
#define io_syscall3(type,fname,sname,type1,arg1,type2,arg2,type3,arg3) \
type fname(type1 arg1,type2 arg2,type3 arg3) { \
__SYS_REG(sname) \
- register long __x0 __asm__("x0") = (long)arg1; \
- register long __x1 __asm__("x1") = (long)arg2; \
- register long __x2 __asm__("x2") = (long)arg3; \
- register long __res_x0 __asm__("x0"); \
+ register long __x0 __asm__("x0") = (long)arg1; \
+ register long __x1 __asm__("x1") = (long)arg2; \
+ register long __x2 __asm__("x2") = (long)arg3; \
+ register long __res_x0 __asm__("x0"); \
__asm__ __volatile__ ( \
__syscall(sname) \
: "=r" (__res_x0) \
@@ -69,11 +69,11 @@ type fname(type1 arg1,type2 arg2,type3 arg3) { \
#define io_syscall4(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4)\
type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4) { \
__SYS_REG(sname) \
- register long __x0 __asm__("x0") = (long)arg1; \
- register long __x1 __asm__("x1") = (long)arg2; \
- register long __x2 __asm__("x2") = (long)arg3; \
- register long __x3 __asm__("x3") = (long)arg4; \
- register long __res_x0 __asm__("x0"); \
+ register long __x0 __asm__("x0") = (long)arg1; \
+ register long __x1 __asm__("x1") = (long)arg2; \
+ register long __x2 __asm__("x2") = (long)arg3; \
+ register long __x3 __asm__("x3") = (long)arg4; \
+ register long __res_x0 __asm__("x0"); \
__asm__ __volatile__ ( \
__syscall(sname) \
: "=r" (__res_x0) \
@@ -85,12 +85,12 @@ type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4) { \
#define io_syscall5(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \
type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) {\
__SYS_REG(sname) \
- register long __x0 __asm__("x0") = (long)arg1; \
- register long __x1 __asm__("x1") = (long)arg2; \
- register long __x2 __asm__("x2") = (long)arg3; \
- register long __x3 __asm__("x3") = (long)arg4; \
- register long __x4 __asm__("x4") = (long)arg5; \
- register long __res_x0 __asm__("x0"); \
+ register long __x0 __asm__("x0") = (long)arg1; \
+ register long __x1 __asm__("x1") = (long)arg2; \
+ register long __x2 __asm__("x2") = (long)arg3; \
+ register long __x3 __asm__("x3") = (long)arg4; \
+ register long __x4 __asm__("x4") = (long)arg5; \
+ register long __res_x0 __asm__("x0"); \
__asm__ __volatile__ ( \
__syscall(sname) \
: "=r" (__res_x0) \