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authorJaroslav Hensl <jara@hensl.cz>2025-07-03 22:56:11 +0200
committerJaroslav Hensl <jara@hensl.cz>2025-07-03 22:56:11 +0200
commit246d596f17232e8a8fc5239cb35b95f29abcb609 (patch)
tree8e53b14fd987dd1fc771182203ee688f62d5447c
parent0d4ef2ba2beff03f21152795a20134bc5241f990 (diff)
downloadvmdisp9x-246d596f17232e8a8fc5239cb35b95f29abcb609.tar.gz
vram memory management
-rw-r--r--3d_accel.h20
-rw-r--r--vxd_fbhda.c35
-rw-r--r--vxd_lib.h3
-rw-r--r--vxd_main.c2
-rw-r--r--vxd_svga.c2
-rw-r--r--vxd_vbe.c1
6 files changed, 62 insertions, 1 deletions
diff --git a/3d_accel.h b/3d_accel.h
index cf682dd..2badeb4 100644
--- a/3d_accel.h
+++ b/3d_accel.h
@@ -33,7 +33,7 @@ THE SOFTWARE.
#endif
#endif
-#define API_3DACCEL_VER 20250522
+#define API_3DACCEL_VER 20250702
#define ESCAPE_DRV_NT 0x1103 /* (4355) */
@@ -150,8 +150,26 @@ typedef struct FBHDA
DWORD gamma_update; /* INC by one everytime when the pallete is updated */
DWORD gpu_mem_total;
DWORD gpu_mem_used;
+ /* heap allocator */
+#ifndef FBHDA_SIXTEEN
+ DWORD *heap_info; /* info block (id of first block, or ~0 on free) */
+ BYTE *heap_start; /* minimal address (but allocation from end to beginning) */
+ BYTE *heap_end; /* maximal address + 1 */
+#else
+ DWORD heap_info;
+ DWORD heap_start;
+ DWORD heap_end;
+#endif
+ DWORD heap_count; /* number of blocks = heap_size_in_bytes / FB_VRAM_HEAP_GRANULARITY */
+ DWORD heap_length; /* maximum usable block with current framebuffer */
+ DWORD res1;
+ DWORD res2;
+ DWORD res3;
} FBHDA_t;
+#define FB_VRAM_HEAP_GRANULARITY (4*32)
+/* minimum of vram allocation (32px at 32bpp, or 64px at 16bpp) */
+
#define FB_SUPPORT_FLIPING 1
#define FB_ACCEL_VIRGE 2
#define FB_ACCEL_CHROMIUM 4
diff --git a/vxd_fbhda.c b/vxd_fbhda.c
index 3371de6..b8bba8c 100644
--- a/vxd_fbhda.c
+++ b/vxd_fbhda.c
@@ -65,6 +65,41 @@ BOOL FBHDA_init_hw()
return FALSE;
}
+void FBHDA_update_heap_size(BOOL init)
+{
+ if(hda)
+ {
+ DWORD bottom = hda->vram_size - hda->overlays_size;
+ DWORD blocks = bottom/FB_VRAM_HEAP_GRANULARITY;
+ DWORD blocks_size = blocks*sizeof(DWORD);
+ DWORD top;
+ DWORD start;
+
+ blocks_size += ((FB_VRAM_HEAP_GRANULARITY - (blocks_size) % FB_VRAM_HEAP_GRANULARITY)) % FB_VRAM_HEAP_GRANULARITY;
+
+ hda->heap_end = ((BYTE*)hda->vram_pm32) + (blocks*FB_VRAM_HEAP_GRANULARITY - blocks_size);
+ hda->heap_info = (DWORD*)hda->heap_end;
+
+ top = hda->system_surface + hda->stride;
+ start = hda->heap_end - ((BYTE*)hda->vram_pm32 + top);
+
+ hda->heap_count = blocks;
+ hda->heap_length = start / FB_VRAM_HEAP_GRANULARITY;
+ hda->heap_start = hda->heap_end - FB_VRAM_HEAP_GRANULARITY*hda->heap_length;
+
+ dbg_printf("FBHDA_update_heap_size(start=%lu bottom=%lu, hda->heap_length=%lu)\n", start, bottom, hda->heap_length);
+
+ if(init)
+ {
+ DWORD i;
+ for(i = 0; i < blocks; i++)
+ {
+ hda->heap_info[i] = (~0UL);
+ }
+ }
+ }
+}
+
void FBHDA_release_hw()
{
if(hda)
diff --git a/vxd_lib.h b/vxd_lib.h
index 9dcaa9d..712c911 100644
--- a/vxd_lib.h
+++ b/vxd_lib.h
@@ -102,3 +102,6 @@ void dbg_printf( const char *s, ... );
struct _VPICD_IRQ_Descriptor;
BOOL VPICD_Virtualize_IRQ(struct _VPICD_IRQ_Descriptor *vid);
+
+/* extra FBHA */
+void FBHDA_update_heap_size(BOOL init);
diff --git a/vxd_main.c b/vxd_main.c
index 9671162..425765d 100644
--- a/vxd_main.c
+++ b/vxd_main.c
@@ -515,6 +515,8 @@ static void configure_FBHDA()
{
fbhda->flags |= FB_ACCEL_QEMU3DFX;
}
+
+ FBHDA_update_heap_size(TRUE);
}
}
diff --git a/vxd_svga.c b/vxd_svga.c
index c3f1c98..68c58d6 100644
--- a/vxd_svga.c
+++ b/vxd_svga.c
@@ -944,6 +944,8 @@ BOOL SVGA_setmode(DWORD w, DWORD h, DWORD bpp)
SVGA_clear();
mouse_invalidate();
+ FBHDA_update_heap_size(FALSE);
+
FBHDA_access_end(0);
fb_lock_cnt = 0; // reset lock counters
diff --git a/vxd_vbe.c b/vxd_vbe.c
index 4d78939..b87efcc 100644
--- a/vxd_vbe.c
+++ b/vxd_vbe.c
@@ -271,6 +271,7 @@ BOOL VBE_setmode(DWORD w, DWORD h, DWORD bpp)
VBE_clear();
mouse_invalidate();
+ FBHDA_update_heap_size(FALSE);
return TRUE;
}