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* lavu/fixed_dsp: R-V V fmul_window_scaledRémi Denis-Courmont2023-11-232-1/+54
* lavu/float_dsp: optimise R-V V fmul_reverse & fmul_windowRémi Denis-Courmont2023-11-231-6/+8
* lavu/fixed_dsp: optimise R-V V fmul_reverseRémi Denis-Courmont2023-11-231-3/+4
* riscv: fix builds without Zbb supportRémi Denis-Courmont2023-11-181-0/+5
* lavu/riscv: fix typoRémi Denis-Courmont2023-10-291-1/+1
* lavu/fixed_dsp: R-V V vector_fmul_windowRémi Denis-Courmont2023-10-092-0/+50
* lavu/fixed_dsp: R-V V vector_fmulRémi Denis-Courmont2023-10-092-0/+20
* lavu/fixed_dsp: R-V V vector_fmul_reverseRémi Denis-Courmont2023-10-092-0/+27
* lavu/fixed_dsp: R-V V vector_fmul_addRémi Denis-Courmont2023-10-092-0/+26
* lavu/float_dsp: adjust multipler in R-V V fmul_windowRémi Denis-Courmont2023-10-091-1/+1
* lavu/fixed_dsp: R-V V scalarproductRémi Denis-Courmont2023-10-072-1/+27
* lavu/float_dsp: avoid reg-stride in R-V V fmul_windowRémi Denis-Courmont2023-10-031-20/+25
* lavu/float_dsp: avoid reg-stride in R-V V reverse_fmulRémi Denis-Courmont2023-10-031-6/+11
* riscv: factor out the bswap32 assemblerRémi Denis-Courmont2023-10-021-0/+65
* Revert "lavu/timer: remove gratuitous volatile"Rémi Denis-Courmont2023-09-281-2/+2
* lavu/timer: specify RISC-V time unitRémi Denis-Courmont2023-08-241-0/+1
* lavu/timer: remove gratuitous volatileRémi Denis-Courmont2023-08-241-2/+2
* lavu/timer: use time for AV_READ_TIME on RISC-VRémi Denis-Courmont2023-08-241-6/+6
* lavu/float_dsp: rework RISC-V V scalar productRémi Denis-Courmont2023-07-201-6/+8
* lavu/float_dsp: unroll RISC-V V loopsRémi Denis-Courmont2023-07-201-10/+10
* lavu: add/use flag for RISC-V Zba extensionRémi Denis-Courmont2023-07-193-16/+21
* lavu/fixed_dsp: unroll RISC-V V loopRémi Denis-Courmont2023-07-171-1/+1
* riscv/intmath: use builtins for counting onesRémi Denis-Courmont2023-05-021-26/+4
* riscv/bswap: use compiler builtinsRémi Denis-Courmont2023-05-021-47/+5
* riscv: fix scalar product initialisationRémi Denis-Courmont2022-10-131-1/+1
* lavu/riscv: helper macro for VTYPE encodingRémi Denis-Courmont2022-10-101-0/+75
* lavu/riscv: CPU flag for the Zbb extensionRémi Denis-Courmont2022-10-051-0/+6
* riscv: remove unnecessary #include'sRémi Denis-Courmont2022-10-053-4/+0
* lavu/riscv: helper to read the vector lengthRémi Denis-Courmont2022-09-281-0/+45
* lavu/fixeddsp: RISC-V V butterflies_fixedRémi Denis-Courmont2022-09-273-1/+81
* lavu/floatdsp: RISC-V V scalarproduct_floatRémi Denis-Courmont2022-09-272-0/+22
* lavu/floatdsp: RISC-V V vector_fmul_windowRémi Denis-Courmont2022-09-272-0/+36
* lavu/floatdsp: RISC-V V vector_fmul_reverseRémi Denis-Courmont2022-09-272-0/+24
* lavu/floatdsp: RISC-V V butterflies_floatRémi Denis-Courmont2022-09-272-0/+20
* lavu/floatdsp: RISC-V V vector_fmul_addRémi Denis-Courmont2022-09-272-0/+22
* lavu/floatdsp: RISC-V V vector_dmac_scalarRémi Denis-Courmont2022-09-272-0/+21
* lavu/floatdsp: RISC-V V vector_fmac_scalarRémi Denis-Courmont2022-09-272-0/+22
* lavu/floatdsp: RISC-V V vector_dmulRémi Denis-Courmont2022-09-272-1/+22
* lavu/floatdsp: RISC-V V vector_fmulRémi Denis-Courmont2022-09-272-1/+22
* lavu/floatdsp: RISC-V V vector_dmul_scalarRémi Denis-Courmont2022-09-272-0/+23
* lavu/floatdsp: RISC-V V vector_fmul_scalarRémi Denis-Courmont2022-09-273-1/+81
* lavu/riscv: fallback macros for SH{1, 2, 3}ADDRémi Denis-Courmont2022-09-271-0/+19
* lavu/cpu: CPU flags for the RISC-V Vector extensionRémi Denis-Courmont2022-09-271-0/+19
* lavu/riscv: initial common header for assembler macrosRémi Denis-Courmont2022-09-271-0/+77
* lavu/cpu: detect RISC-V base extensionsRémi Denis-Courmont2022-09-272-0/+57
* lavu/riscv: fix off-by-one in bit-magnitude clipRémi Denis-Courmont2022-09-151-2/+2
* lavu/riscv: fix av_clip_int16Rémi Denis-Courmont2022-09-141-2/+2
* lavu/riscv: add <intmath.h> optimisationsRémi Denis-Courmont2022-09-131-0/+103
* lavu/riscv: byte-swap operationsRémi Denis-Courmont2022-09-131-0/+74
* lavu/riscv: AV_READ_TIME cycle counterRémi Denis-Courmont2022-09-131-0/+53