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| author | Rémi Denis-Courmont <remi@remlab.net> | 2023-10-04 18:25:29 +0300 |
|---|---|---|
| committer | Rémi Denis-Courmont <remi@remlab.net> | 2023-10-09 19:52:28 +0300 |
| commit | da7a77fb0a6b1397f0a226ef754ff89cd2cdee35 (patch) | |
| tree | c4d37c61e1730735b129052d0cc537787176c301 /libavutil | |
| parent | bf911cc1bf7fa578ea4ab6fa552b28727ffaf8b3 (diff) | |
| download | ffmpeg-da7a77fb0a6b1397f0a226ef754ff89cd2cdee35.tar.gz | |
lavu/fixed_dsp: R-V V vector_fmul_reverse
Diffstat (limited to 'libavutil')
| -rw-r--r-- | libavutil/riscv/fixed_dsp_init.c | 3 | ||||
| -rw-r--r-- | libavutil/riscv/fixed_dsp_rvv.S | 24 |
2 files changed, 27 insertions, 0 deletions
diff --git a/libavutil/riscv/fixed_dsp_init.c b/libavutil/riscv/fixed_dsp_init.c index 4b239829f5..470b35fb63 100644 --- a/libavutil/riscv/fixed_dsp_init.c +++ b/libavutil/riscv/fixed_dsp_init.c @@ -25,6 +25,8 @@ #include "libavutil/cpu.h" #include "libavutil/fixed_dsp.h" +void ff_vector_fmul_reverse_fixed_rvv(int *dst, const int *src0, + const int *src1, int len); void ff_vector_fmul_add_fixed_rvv(int *dst, const int *src0, const int *src1, const int *src2, int len); int ff_scalarproduct_fixed_rvv(const int *v1, const int *v2, int len); @@ -36,6 +38,7 @@ av_cold void ff_fixed_dsp_init_riscv(AVFixedDSPContext *fdsp) int flags = av_get_cpu_flags(); if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB_ADDR)) { + fdsp->vector_fmul_reverse = ff_vector_fmul_reverse_fixed_rvv; fdsp->vector_fmul_add = ff_vector_fmul_add_fixed_rvv; if (flags & AV_CPU_FLAG_RVV_I64) diff --git a/libavutil/riscv/fixed_dsp_rvv.S b/libavutil/riscv/fixed_dsp_rvv.S index 1022a401d3..8a5d1853c5 100644 --- a/libavutil/riscv/fixed_dsp_rvv.S +++ b/libavutil/riscv/fixed_dsp_rvv.S @@ -20,6 +20,30 @@ #include "asm.S" +func ff_vector_fmul_reverse_fixed_rvv, zve32x + csrwi vxrm, 0 + vsetvli t0, zero, e16, m4, ta, ma + sh2add a2, a3, a2 + vid.v v0 + vadd.vi v0, v0, 1 +1: + vsetvli t0, a3, e16, m4, ta, ma + slli t1, t0, 2 + vrsub.vx v4, v0, t0 // v4[i] = [VL-1, VL-2... 1, 0] + sub a2, a2, t1 + vsetvli zero, zero, e32, m8, ta, ma + vle32.v v8, (a2) + sub a3, a3, t0 + vle32.v v16, (a1) + add a1, a1, t1 + vrgatherei16.vv v24, v8, v4 // v24 = reverse(v8) + vsmul.vv v16, v16, v24 + vse32.v v16, (a0) + add a0, a0, t1 + bnez a3, 1b + + ret +endfunc func ff_vector_fmul_add_fixed_rvv, zve32x csrwi vxrm, 0 |