lavu: add/use flag for RISC-V Zba extension

The code was blindly assuming that Zbb or V implied Zba. While the
earlier is practically always true, the later broke some QEMU setups,
as V was introduced earlier than Zba.

5 files changed, 23 insertions, 16 deletions

diff --git a/libavutil/cpu.c b/libavutil/cpu.c
index 2ffc3986aa..1e0607d581 100644
--- a/libavutil/cpu.c
+++ b/libavutil/cpu.c
@@ -190,6 +190,7 @@ int av_parse_cpu_caps(unsigned *flags, const char *s)
         { "rvv-f32",  NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F32 },     .unit = "flags" },
         { "rvv-i64",  NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_I64 },     .unit = "flags" },
         { "rvv",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F64 },     .unit = "flags" },
+        { "rvb-addr",NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_ADDR },   .unit = "flags" },
         { "rvb-basic",NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_BASIC },   .unit = "flags" },
 #endif
         { NULL },
diff --git a/libavutil/cpu.h b/libavutil/cpu.h
index da486f9c7a..8dff341886 100644
--- a/libavutil/cpu.h
+++ b/libavutil/cpu.h
@@ -89,6 +89,7 @@
 #define AV_CPU_FLAG_RVV_I64      (1 << 5) ///< Vectors of 64-bit int's */
 #define AV_CPU_FLAG_RVV_F64      (1 << 6) ///< Vectors of double's
 #define AV_CPU_FLAG_RVB_BASIC    (1 << 7) ///< Basic bit-manipulations
+#define AV_CPU_FLAG_RVB_ADDR     (1 << 8) ///< Address bit-manipulations
 
 /**
  * Return the flags which specify extensions supported by the CPU.
diff --git a/libavutil/riscv/cpu.c b/libavutil/riscv/cpu.c
index a9263dbb78..fa45c0ad83 100644
--- a/libavutil/riscv/cpu.c
+++ b/libavutil/riscv/cpu.c
@@ -41,7 +41,7 @@ int ff_get_cpu_flags_riscv(void)
     if (hwcap & HWCAP_RV('D'))
         ret |= AV_CPU_FLAG_RVD;
     if (hwcap & HWCAP_RV('B'))
-        ret |= AV_CPU_FLAG_RVB_BASIC;
+        ret |= AV_CPU_FLAG_RVB_ADDR | AV_CPU_FLAG_RVB_BASIC;
 
     /* The V extension implies all Zve* functional subsets */
     if (hwcap & HWCAP_RV('V'))
@@ -59,6 +59,9 @@ int ff_get_cpu_flags_riscv(void)
 #endif
 #endif
 
+#ifdef __riscv_zba
+    ret |= AV_CPU_FLAG_RVB_ADDR;
+#endif
 #ifdef __riscv_zbb
     ret |= AV_CPU_FLAG_RVB_BASIC;
 #endif
diff --git a/libavutil/riscv/fixed_dsp_init.c b/libavutil/riscv/fixed_dsp_init.c
index e2915f1fcd..d4ca2e2064 100644
--- a/libavutil/riscv/fixed_dsp_init.c
+++ b/libavutil/riscv/fixed_dsp_init.c
@@ -32,7 +32,7 @@ av_cold void ff_fixed_dsp_init_riscv(AVFixedDSPContext *fdsp)
 #if HAVE_RVV
     int flags = av_get_cpu_flags();
 
-    if (flags & AV_CPU_FLAG_RVV_I32)
+    if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB_ADDR))
         fdsp->butterflies_fixed = ff_butterflies_fixed_rvv;
 #endif
 }
diff --git a/libavutil/riscv/float_dsp_init.c b/libavutil/riscv/float_dsp_init.c
index e61f887862..585f237225 100644
--- a/libavutil/riscv/float_dsp_init.c
+++ b/libavutil/riscv/float_dsp_init.c
@@ -52,21 +52,23 @@ av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
 #if HAVE_RVV
     int flags = av_get_cpu_flags();
 
-    if (flags & AV_CPU_FLAG_RVV_F32) {
-        fdsp->vector_fmul = ff_vector_fmul_rvv;
-        fdsp->vector_fmac_scalar = ff_vector_fmac_scalar_rvv;
-        fdsp->vector_fmul_scalar = ff_vector_fmul_scalar_rvv;
-        fdsp->vector_fmul_window = ff_vector_fmul_window_rvv;
-        fdsp->vector_fmul_add = ff_vector_fmul_add_rvv;
-        fdsp->vector_fmul_reverse = ff_vector_fmul_reverse_rvv;
-        fdsp->butterflies_float = ff_butterflies_float_rvv;
-        fdsp->scalarproduct_float = ff_scalarproduct_float_rvv;
-    }
+    if (flags & AV_CPU_FLAG_RVB_ADDR) {
+        if (flags & AV_CPU_FLAG_RVV_F32) {
+            fdsp->vector_fmul = ff_vector_fmul_rvv;
+            fdsp->vector_fmac_scalar = ff_vector_fmac_scalar_rvv;
+            fdsp->vector_fmul_scalar = ff_vector_fmul_scalar_rvv;
+            fdsp->vector_fmul_window = ff_vector_fmul_window_rvv;
+            fdsp->vector_fmul_add = ff_vector_fmul_add_rvv;
+            fdsp->vector_fmul_reverse = ff_vector_fmul_reverse_rvv;
+            fdsp->butterflies_float = ff_butterflies_float_rvv;
+            fdsp->scalarproduct_float = ff_scalarproduct_float_rvv;
+        }
 
-    if (flags & AV_CPU_FLAG_RVV_F64) {
-        fdsp->vector_dmul = ff_vector_dmul_rvv;
-        fdsp->vector_dmac_scalar = ff_vector_dmac_scalar_rvv;
-        fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_rvv;
+        if (flags & AV_CPU_FLAG_RVV_F64) {
+            fdsp->vector_dmul = ff_vector_dmul_rvv;
+            fdsp->vector_dmac_scalar = ff_vector_dmac_scalar_rvv;
+            fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_rvv;
+        }
     }
 #endif
 }