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authorRĂ©mi Denis-Courmont <remi@remlab.net>2022-09-12 18:53:17 +0300
committerJames Almer <jamrial@gmail.com>2022-09-13 16:50:43 -0300
commitd808070547a867a8f3f7b97fdff3574576213c07 (patch)
tree08a834e08e42ee621c01a7bddae60cc20cef3628 /libavfilter/af_anull.c
parent092ce9712f63fc2641ec831d09c8ca0731083ae4 (diff)
downloadffmpeg-d808070547a867a8f3f7b97fdff3574576213c07.tar.gz
lavu/riscv: AV_READ_TIME cycle counter
This uses the architected RISC-V 64-bit cycle counter from the RISC-V unprivileged instruction set. In 64-bit and 128-bit, this is a straightforward CSR read. In 32-bit mode, the 64-bit value is exposed as two CSRs, which cannot be read atomically, so a loop is necessary to detect and fix up the race condition where the bottom half wraps exactly between the two reads.
Diffstat (limited to 'libavfilter/af_anull.c')
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