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| author | Rémi Denis-Courmont <remi@remlab.net> | 2022-09-23 18:09:54 +0300 |
|---|---|---|
| committer | Rémi Denis-Courmont <remi@remlab.net> | 2024-07-30 18:41:51 +0300 |
| commit | 262168b04e6807fce6a78507c14cfc166ba72845 (patch) | |
| tree | b5f9dc5883161891837b72b3ba1ce787afd21870 /libavcodec/riscv/Makefile | |
| parent | 4570b9f3c4e64a996bcadc5af58574f7f32ee1de (diff) | |
| download | ffmpeg-262168b04e6807fce6a78507c14cfc166ba72845.tar.gz | |
lavc/videodsp: RISC-V zicbop prefetch
There are currently no ways to run-time detect the CPU capability, so we
take it for granted (in the worst case, it will execute NOPs).
Diffstat (limited to 'libavcodec/riscv/Makefile')
| -rw-r--r-- | libavcodec/riscv/Makefile | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/libavcodec/riscv/Makefile b/libavcodec/riscv/Makefile index a6cdcb71e9..1491b6c067 100644 --- a/libavcodec/riscv/Makefile +++ b/libavcodec/riscv/Makefile @@ -67,6 +67,8 @@ RVV-OBJS-$(CONFIG_UTVIDEO_DECODER) += riscv/utvideodsp_rvv.o OBJS-$(CONFIG_VC1DSP) += riscv/vc1dsp_init.o RV-OBJS-$(CONFIG_VC1DSP) += riscv/vc1dsp_rvi.o RVV-OBJS-$(CONFIG_VC1DSP) += riscv/vc1dsp_rvv.o +OBJS-$(CONFIG_VIDEODSP) += riscv/videodsp_init.o +RV-OBJS-$(CONFIG_VIDEODSP) += riscv/videodsp.o OBJS-$(CONFIG_VP7_DECODER) += riscv/vp7dsp_init.o RVV-OBJS-$(CONFIG_VP7_DECODER) += riscv/vp7dsp_rvv.o OBJS-$(CONFIG_VP8DSP) += riscv/vp8dsp_init.o |