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| author | Jin Bo <jinbo@loongson.cn> | 2021-05-28 10:04:39 +0800 |
|---|---|---|
| committer | Michael Niedermayer <michael@niedermayer.cc> | 2021-05-28 17:31:21 +0200 |
| commit | ebedd26eefe2ff4bbf5a358907c4e8e4b0d62eae (patch) | |
| tree | b16ba0cf4b99941d2b4730bba833653d3f14f0fb /libavcodec/mips/vc1dsp_mmi.c | |
| parent | e41255cddb827ee152a58a60ed3ecd4dc6e79847 (diff) | |
| download | ffmpeg-ebedd26eefe2ff4bbf5a358907c4e8e4b0d62eae.tar.gz | |
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
Diffstat (limited to 'libavcodec/mips/vc1dsp_mmi.c')
| -rw-r--r-- | libavcodec/mips/vc1dsp_mmi.c | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/libavcodec/mips/vc1dsp_mmi.c b/libavcodec/mips/vc1dsp_mmi.c index 348ecd206f..a8ab3f6cc5 100644 --- a/libavcodec/mips/vc1dsp_mmi.c +++ b/libavcodec/mips/vc1dsp_mmi.c @@ -134,7 +134,7 @@ void ff_vc1_inv_trans_8x8_dc_mmi(uint8_t *dest, ptrdiff_t linesize, int16_t *blo dc = (3 * dc + 16) >> 5; __asm__ volatile( - "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" + "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "pshufh %[dc], %[dc], %[ftmp0] \n\t" "li %[count], 0x02 \n\t" @@ -425,7 +425,7 @@ void ff_vc1_inv_trans_8x4_dc_mmi(uint8_t *dest, ptrdiff_t linesize, int16_t *blo dc = (17 * dc + 64) >> 7; __asm__ volatile( - "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" + "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "pshufh %[dc], %[dc], %[ftmp0] \n\t" MMI_LDC1(%[ftmp1], %[dest0], 0x00) @@ -705,7 +705,7 @@ void ff_vc1_inv_trans_8x4_mmi(uint8_t *dest, ptrdiff_t linesize, int16_t *block) MMI_LWC1(%[ftmp3], %[tmp0], 0x00) PTR_ADDU "%[tmp0], %[tmp0], %[linesize] \n\t" MMI_LWC1(%[ftmp4], %[tmp0], 0x00) - "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" + "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "punpcklbh %[ftmp1], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp2], %[ftmp2], %[ftmp0] \n\t" "punpcklbh %[ftmp3], %[ftmp3], %[ftmp0] \n\t" @@ -829,7 +829,7 @@ void ff_vc1_inv_trans_8x4_mmi(uint8_t *dest, ptrdiff_t linesize, int16_t *block) MMI_LWC1(%[ftmp3], %[tmp0], 0x04) PTR_ADDU "%[tmp0], %[tmp0], %[linesize] \n\t" MMI_LWC1(%[ftmp4], %[tmp0], 0x04) - "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" + "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "punpcklbh %[ftmp1], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp2], %[ftmp2], %[ftmp0] \n\t" "punpcklbh %[ftmp3], %[ftmp3], %[ftmp0] \n\t" @@ -877,7 +877,7 @@ void ff_vc1_inv_trans_4x8_dc_mmi(uint8_t *dest, ptrdiff_t linesize, int16_t *blo dc = (12 * dc + 64) >> 7; __asm__ volatile( - "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" + "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "pshufh %[dc], %[dc], %[ftmp0] \n\t" MMI_LWC1(%[ftmp1], %[dest0], 0x00) @@ -1058,7 +1058,7 @@ void ff_vc1_inv_trans_4x8_mmi(uint8_t *dest, ptrdiff_t linesize, int16_t *block) MMI_LWC1(%[ftmp7], %[tmp0], 0x00) PTR_ADDU "%[tmp0], %[tmp0], %[linesize] \n\t" MMI_LWC1(%[ftmp8], %[tmp0], 0x00) - "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" + "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "punpcklbh %[ftmp1], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp2], %[ftmp2], %[ftmp0] \n\t" "punpcklbh %[ftmp3], %[ftmp3], %[ftmp0] \n\t" @@ -1133,7 +1133,7 @@ void ff_vc1_inv_trans_4x4_dc_mmi(uint8_t *dest, ptrdiff_t linesize, int16_t *blo dc = (17 * dc + 64) >> 7; __asm__ volatile( - "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" + "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "pshufh %[dc], %[dc], %[ftmp0] \n\t" MMI_LWC1(%[ftmp1], %[dest0], 0x00) @@ -1339,7 +1339,7 @@ void ff_vc1_inv_trans_4x4_mmi(uint8_t *dest, ptrdiff_t linesize, int16_t *block) MMI_LWC1(%[ftmp3], %[tmp0], 0x00) PTR_ADDU "%[tmp0], %[tmp0], %[linesize] \n\t" MMI_LWC1(%[ftmp4], %[tmp0], 0x00) - "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" + "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "punpcklbh %[ftmp1], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp2], %[ftmp2], %[ftmp0] \n\t" "punpcklbh %[ftmp3], %[ftmp3], %[ftmp0] \n\t" @@ -1664,7 +1664,7 @@ static void vc1_put_ver_16b_shift2_mmi(int16_t *dst, DECLARE_VAR_ADDRT; __asm__ volatile( - "xor $f0, $f0, $f0 \n\t" + "pxor $f0, $f0, $f0 \n\t" "li $8, 0x03 \n\t" LOAD_ROUNDER_MMI("%[rnd]") "ldc1 $f12, %[ff_pw_9] \n\t" @@ -1771,7 +1771,7 @@ static void OPNAME ## vc1_shift2_mmi(uint8_t *dst, const uint8_t *src, \ rnd = 8 - rnd; \ \ __asm__ volatile( \ - "xor $f0, $f0, $f0 \n\t" \ + "pxor $f0, $f0, $f0 \n\t" \ "li $10, 0x08 \n\t" \ LOAD_ROUNDER_MMI("%[rnd]") \ "ldc1 $f12, %[ff_pw_9] \n\t" \ @@ -1898,7 +1898,7 @@ vc1_put_ver_16b_ ## NAME ## _mmi(int16_t *dst, const uint8_t *src, \ src -= src_stride; \ \ __asm__ volatile( \ - "xor $f0, $f0, $f0 \n\t" \ + "pxor $f0, $f0, $f0 \n\t" \ LOAD_ROUNDER_MMI("%[rnd]") \ "ldc1 $f10, %[ff_pw_53] \n\t" \ "ldc1 $f12, %[ff_pw_18] \n\t" \ @@ -1973,7 +1973,7 @@ OPNAME ## vc1_hor_16b_ ## NAME ## _mmi(uint8_t *dst, mips_reg stride, \ rnd -= (-4+58+13-3)*256; /* Add -256 bias */ \ \ __asm__ volatile( \ - "xor $f0, $f0, $f0 \n\t" \ + "pxor $f0, $f0, $f0 \n\t" \ LOAD_ROUNDER_MMI("%[rnd]") \ "ldc1 $f10, %[ff_pw_53] \n\t" \ "ldc1 $f12, %[ff_pw_18] \n\t" \ @@ -2023,7 +2023,7 @@ OPNAME ## vc1_## NAME ## _mmi(uint8_t *dst, const uint8_t *src, \ rnd = 32-rnd; \ \ __asm__ volatile ( \ - "xor $f0, $f0, $f0 \n\t" \ + "pxor $f0, $f0, $f0 \n\t" \ LOAD_ROUNDER_MMI("%[rnd]") \ "ldc1 $f10, %[ff_pw_53] \n\t" \ "ldc1 $f12, %[ff_pw_18] \n\t" \ @@ -2259,7 +2259,7 @@ void ff_put_no_rnd_vc1_chroma_mc8_mmi(uint8_t *dst /* align 8 */, __asm__ volatile( "li %[tmp0], 0x06 \n\t" - "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" + "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "mtc1 %[tmp0], %[ftmp9] \n\t" "pshufh %[A], %[A], %[ftmp0] \n\t" "pshufh %[B], %[B], %[ftmp0] \n\t" @@ -2314,7 +2314,7 @@ void ff_put_no_rnd_vc1_chroma_mc4_mmi(uint8_t *dst /* align 8 */, __asm__ volatile( "li %[tmp0], 0x06 \n\t" - "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" + "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "mtc1 %[tmp0], %[ftmp5] \n\t" "pshufh %[A], %[A], %[ftmp0] \n\t" "pshufh %[B], %[B], %[ftmp0] \n\t" @@ -2367,7 +2367,7 @@ void ff_avg_no_rnd_vc1_chroma_mc8_mmi(uint8_t *dst /* align 8 */, __asm__ volatile( "li %[tmp0], 0x06 \n\t" - "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" + "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "mtc1 %[tmp0], %[ftmp9] \n\t" "pshufh %[A], %[A], %[ftmp0] \n\t" "pshufh %[B], %[B], %[ftmp0] \n\t" @@ -2425,7 +2425,7 @@ void ff_avg_no_rnd_vc1_chroma_mc4_mmi(uint8_t *dst /* align 8 */, __asm__ volatile( "li %[tmp0], 0x06 \n\t" - "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" + "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "mtc1 %[tmp0], %[ftmp5] \n\t" "pshufh %[A], %[A], %[ftmp0] \n\t" "pshufh %[B], %[B], %[ftmp0] \n\t" |