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authorJin Bo <jinbo@loongson.cn>2021-05-28 10:04:39 +0800
committerMichael Niedermayer <michael@niedermayer.cc>2021-05-28 17:31:21 +0200
commitebedd26eefe2ff4bbf5a358907c4e8e4b0d62eae (patch)
treeb16ba0cf4b99941d2b4730bba833653d3f14f0fb /libavcodec/mips/hpeldsp_mmi.c
parente41255cddb827ee152a58a60ed3ecd4dc6e79847 (diff)
downloadffmpeg-ebedd26eefe2ff4bbf5a358907c4e8e4b0d62eae.tar.gz
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR, gcc supports both of them, clang only supports the second type. 2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc supports both of them, clang only supports the second type. Signed-off-by: Jin Bo <jinbo@loongson.cn> Reviewed-by: yinshiyou-hf@loongson.cn Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
Diffstat (limited to 'libavcodec/mips/hpeldsp_mmi.c')
-rw-r--r--libavcodec/mips/hpeldsp_mmi.c26
1 files changed, 13 insertions, 13 deletions
diff --git a/libavcodec/mips/hpeldsp_mmi.c b/libavcodec/mips/hpeldsp_mmi.c
index e69b2bd980..bf3e4636aa 100644
--- a/libavcodec/mips/hpeldsp_mmi.c
+++ b/libavcodec/mips/hpeldsp_mmi.c
@@ -676,14 +676,14 @@ inline void ff_put_no_rnd_pixels8_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
PTR_ADDU "%[src1], %[src1], %[addr2] \n\t"
- "xor %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
- "xor %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
- "xor %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
- "xor %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
+ "pxor %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
+ "pxor %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
+ "pxor %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
+ "pxor %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
- "xor %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
- "xor %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
+ "pxor %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
+ "pxor %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
MMI_SDC1(%[ftmp0], %[dst], 0x00)
MMI_SDXC1(%[ftmp1], %[dst], %[dst_stride], 0x00)
PTR_ADDU "%[src2], %[src2], %[addr3] \n\t"
@@ -696,14 +696,14 @@ inline void ff_put_no_rnd_pixels8_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
PTR_ADDU "%[src1], %[src1], %[addr2] \n\t"
- "xor %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
- "xor %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
- "xor %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
- "xor %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
+ "pxor %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
+ "pxor %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
+ "pxor %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
+ "pxor %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
- "xor %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
- "xor %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
+ "pxor %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
+ "pxor %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
MMI_SDC1(%[ftmp0], %[dst], 0x00)
MMI_SDXC1(%[ftmp1], %[dst], %[dst_stride], 0x00)
PTR_ADDU "%[src2], %[src2], %[addr3] \n\t"
@@ -846,7 +846,7 @@ void ff_put_pixels8_xy2_8_mmi(uint8_t *block, const uint8_t *pixels,
DECLARE_VAR_ADDRT;
__asm__ volatile (
- "xor %[ftmp7], %[ftmp7], %[ftmp7] \n\t"
+ "pxor %[ftmp7], %[ftmp7], %[ftmp7] \n\t"
"dli %[addr0], 0x0f \n\t"
"pcmpeqw %[ftmp6], %[ftmp6], %[ftmp6] \n\t"
"dmtc1 %[addr0], %[ftmp8] \n\t"