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| author | Mans Rullgard <mans@mansr.com> | 2012-08-02 19:17:16 +0100 |
|---|---|---|
| committer | Mans Rullgard <mans@mansr.com> | 2012-09-20 17:07:18 +0100 |
| commit | a27a690fac6d9f42464039702f8cde6777778a53 (patch) | |
| tree | 239f30a80039406ad5a41205b0fe26a92b797928 /libavcodec/arm | |
| parent | 0122118ec32087cf3522bf14a1c4e34cb7d95a67 (diff) | |
| download | ffmpeg-a27a690fac6d9f42464039702f8cde6777778a53.tar.gz | |
ARM: swap source operands in some add instructions
This allows using a 16-bit opcode when generating Thumb2 code.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Diffstat (limited to 'libavcodec/arm')
| -rw-r--r-- | libavcodec/arm/ac3dsp_armv6.S | 2 | ||||
| -rw-r--r-- | libavcodec/arm/dsputil_arm.S | 4 | ||||
| -rw-r--r-- | libavcodec/arm/vp8_armv6.S | 6 |
3 files changed, 6 insertions, 6 deletions
diff --git a/libavcodec/arm/ac3dsp_armv6.S b/libavcodec/arm/ac3dsp_armv6.S index f6f297a532..2028d0b89f 100644 --- a/libavcodec/arm/ac3dsp_armv6.S +++ b/libavcodec/arm/ac3dsp_armv6.S @@ -32,7 +32,7 @@ function ff_ac3_bit_alloc_calc_bap_armv6, export=1 ldrb r4, [r4, r2] add r1, r1, r2, lsl #1 @ psd + start add r0, r0, r4, lsl #1 @ mask + band - add r4, lr, r4 + add r4, r4, lr add r7, r7, r2 @ bap + start 1: ldrsh r9, [r0], #2 @ mask[band] diff --git a/libavcodec/arm/dsputil_arm.S b/libavcodec/arm/dsputil_arm.S index dd65f705a7..3686befec1 100644 --- a/libavcodec/arm/dsputil_arm.S +++ b/libavcodec/arm/dsputil_arm.S @@ -632,7 +632,7 @@ function ff_add_pixels_clamped_arm, export=1 ldrsh r7, [r0, #2] and r6, r4, #0xFF and r8, r4, #0xFF00 - add r6, r5, r6 + add r6, r6, r5 add r8, r7, r8, lsr #8 mvn r5, r5 mvn r7, r7 @@ -674,7 +674,7 @@ function ff_add_pixels_clamped_arm, export=1 ldrsh r7, [r0, #10] and r6, r4, #0xFF and r8, r4, #0xFF00 - add r6, r5, r6 + add r6, r6, r5 add r8, r7, r8, lsr #8 mvn r5, r5 mvn r7, r7 diff --git a/libavcodec/arm/vp8_armv6.S b/libavcodec/arm/vp8_armv6.S index 1b668bcd2a..3863dc31a5 100644 --- a/libavcodec/arm/vp8_armv6.S +++ b/libavcodec/arm/vp8_armv6.S @@ -88,7 +88,7 @@ function ff_decode_block_coeffs_armv6, export=1 add r4, r3, r3, lsl #5 sxth r12, r11 - add r4, r2, r4 + add r4, r4, r2 adds r6, r6, r9 add r4, r4, #11 lsl r8, r8, r9 @@ -138,7 +138,7 @@ A orrcs r8, r8, r10, lsl r6 2: add r4, r3, r3, lsl #5 cmp r3, #16 - add r4, r2, r4 + add r4, r4, r2 pkhtb r11, r11, r11, asr #16 bne 0b b 6b @@ -226,7 +226,7 @@ A orrcs r8, r8, r10, lsl r6 ldr r1, [sp, #4] 4: add r4, r3, r3, lsl #5 - add r4, r2, r4 + add r4, r4, r2 add r4, r4, #22 rac_get_128 r5, r6, r7, r8, r9, r10 it ge |