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| author | Mans Rullgard <mans@mansr.com> | 2011-07-02 17:21:02 +0100 |
|---|---|---|
| committer | Mans Rullgard <mans@mansr.com> | 2011-07-02 18:24:41 +0100 |
| commit | 8aa63f0b31544a63e107c67c519d6ccd11c94810 (patch) | |
| tree | d2acc97bb78d89a133fc5bcdbb7d6f00b79a5af6 /libavcodec/arm | |
| parent | 8f440223f6cb2b557ea6e34ca4079fbe415ecb9d (diff) | |
| download | ffmpeg-8aa63f0b31544a63e107c67c519d6ccd11c94810.tar.gz | |
ARM: NEON optimised vector_clip_int32()
Signed-off-by: Mans Rullgard <mans@mansr.com>
Diffstat (limited to 'libavcodec/arm')
| -rw-r--r-- | libavcodec/arm/dsputil_init_neon.c | 3 | ||||
| -rw-r--r-- | libavcodec/arm/dsputil_neon.S | 16 |
2 files changed, 19 insertions, 0 deletions
diff --git a/libavcodec/arm/dsputil_init_neon.c b/libavcodec/arm/dsputil_init_neon.c index 3bc053c864..3f58dea9cd 100644 --- a/libavcodec/arm/dsputil_init_neon.c +++ b/libavcodec/arm/dsputil_init_neon.c @@ -160,6 +160,8 @@ void ff_vector_fmul_add_neon(float *dst, const float *src0, const float *src1, void ff_vector_clipf_neon(float *dst, const float *src, float min, float max, int len); +void ff_vector_clip_int32_neon(int32_t *dst, const int32_t *src, int32_t min, + int32_t max, unsigned int len); void ff_vorbis_inverse_coupling_neon(float *mag, float *ang, int blocksize); @@ -316,6 +318,7 @@ void ff_dsputil_init_neon(DSPContext *c, AVCodecContext *avctx) c->vector_fmul_reverse = ff_vector_fmul_reverse_neon; c->vector_fmul_add = ff_vector_fmul_add_neon; c->vector_clipf = ff_vector_clipf_neon; + c->vector_clip_int32 = ff_vector_clip_int32_neon; c->vector_fmul_sv_scalar[0] = ff_vector_fmul_sv_scalar_2_neon; c->vector_fmul_sv_scalar[1] = ff_vector_fmul_sv_scalar_4_neon; diff --git a/libavcodec/arm/dsputil_neon.S b/libavcodec/arm/dsputil_neon.S index 5e3bf27f67..3b9b542a68 100644 --- a/libavcodec/arm/dsputil_neon.S +++ b/libavcodec/arm/dsputil_neon.S @@ -815,3 +815,19 @@ function ff_apply_window_int16_neon, export=1 pop {r4,pc} endfunc + +function ff_vector_clip_int32_neon, export=1 + vdup.32 q0, r2 + vdup.32 q1, r3 + ldr r2, [sp] +1: + vld1.32 {q2-q3}, [r1,:128]! + vmin.s32 q2, q2, q1 + vmin.s32 q3, q3, q1 + vmax.s32 q2, q2, q0 + vmax.s32 q3, q3, q0 + vst1.32 {q2-q3}, [r0,:128]! + subs r2, r2, #8 + bgt 1b + bx lr +endfunc |