lavc/vp8dsp: rework R-V V idct_dc_add4y

DCT-related FFmpeg functions often add an unsigned 8-bit sample to a
signed 16-bit coefficient, then clip the result back to an unsigned
8-bit value. RISC-V has no signed 16-bit to unsigned 8-bit clip, so
instead our most common sequence is:
    VWADDU.WV
    set SEW to 16 bits
    VMAX.VV zero     # clip negative values to 0
    set SEW to 8 bits
    VNCLIPU.WI       # clip values over 255 to 255 and narrow

Here we use a different sequence which does not require toggling the
vector type. This assumes that the wide addend vector is biased by
-128:
    VWADDU.WV
    VNCLIP.WI    # clip values to signed 8-bit and narrow
    VXOR.VX 0x80 # flip sign bit (convert signed to unsigned)

Also the VMAX is effectively replaced by a VXOR of half-width. In this
function, this comes for free as we anyway add a constant to the wide
vector in the prologue.

On C908, this has no observable effects. On X60, this improves
microbenchmarks by about 20%.

0 files changed, 0 insertions, 0 deletions