diff options
| author | Rémi Denis-Courmont <remi@remlab.net> | 2024-05-26 13:19:15 +0300 |
|---|---|---|
| committer | Rémi Denis-Courmont <remi@remlab.net> | 2024-05-29 16:57:02 +0300 |
| commit | 4a0e629b6f4b6fb612ce08a471fcf3c249d35eaa (patch) | |
| tree | f46a62137b38770947136b3257b2759dc1b1d5e5 | |
| parent | fd39997f727855d7cc0118203269feac0ca2fa31 (diff) | |
| download | ffmpeg-4a0e629b6f4b6fb612ce08a471fcf3c249d35eaa.tar.gz | |
lavc/vp7dsp: revector ff_vp7_dc_wht_rvv
This prepares for some code reuse.
| -rw-r--r-- | libavcodec/riscv/vp7dsp_init.c | 3 | ||||
| -rw-r--r-- | libavcodec/riscv/vp7dsp_rvv.S | 23 |
2 files changed, 16 insertions, 10 deletions
diff --git a/libavcodec/riscv/vp7dsp_init.c b/libavcodec/riscv/vp7dsp_init.c index 5a57a39d0b..1406eb1c6a 100644 --- a/libavcodec/riscv/vp7dsp_init.c +++ b/libavcodec/riscv/vp7dsp_init.c @@ -32,7 +32,8 @@ av_cold void ff_vp7dsp_init_riscv(VP8DSPContext *c) #if HAVE_RVV int flags = av_get_cpu_flags(); - if ((flags & AV_CPU_FLAG_RVV_I32) && ff_rv_vlen_least(128)) { + if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB_ADDR) && + ff_rv_vlen_least(128)) { #if __riscv_xlen >= 64 c->vp8_luma_dc_wht = ff_vp7_luma_dc_wht_rvv; #endif diff --git a/libavcodec/riscv/vp7dsp_rvv.S b/libavcodec/riscv/vp7dsp_rvv.S index 819d2056dc..06e251f5ce 100644 --- a/libavcodec/riscv/vp7dsp_rvv.S +++ b/libavcodec/riscv/vp7dsp_rvv.S @@ -22,6 +22,15 @@ #if __riscv_xlen >= 64 func ff_vp7_luma_dc_wht_rvv, zve32x + li a2, 4 * 16 * 2 + li a7, 16 * 2 + jal t0, 1f + vsse16.v v4, (a0), a7 + vsse16.v v5, (t1), a7 + vsse16.v v6, (t2), a7 + vsse16.v v7, (t3), a7 + ret +1: csrwi vxrm, 0 li t4, 12540 vsetivli zero, 4, e16, mf2, ta, ma @@ -58,14 +67,14 @@ func ff_vp7_luma_dc_wht_rvv, zve32x vle16.v v2, (t2) vle16.v v3, (t3) vwmul.vx v8, v1, t4 - li t0, 16 * 2 vwmul.vx v9, v3, t6 - addi t1, a0, 1 * 4 * 16 * 2 + add t1, a2, a0 vwmul.vx v10, v1, t6 - addi t2, a0, 2 * 4 * 16 * 2 + sh1add t2, a2, a0 vwmul.vx v11, v3, t4 - addi t3, a0, 3 * 4 * 16 * 2 + sh1add a2, a2, a2 # a2 *= 3 vwadd.vv v4, v0, v2 + add t3, a2, a0 vwsub.vv v5, v0, v2 vsetvli zero, zero, e32, m1, ta, ma vmul.vx v4, v4, t5 @@ -86,10 +95,6 @@ func ff_vp7_luma_dc_wht_rvv, zve32x vnclip.wi v5, v1, 18 vnclip.wi v6, v2, 18 vnclip.wi v7, v3, 18 - vsse16.v v4, (a0), t0 - vsse16.v v5, (t1), t0 - vsse16.v v6, (t2), t0 - vsse16.v v7, (t3), t0 - ret + jr t0 endfunc #endif |