# Generated by devtools/yamaker. LIBRARY() LICENSE( Apache-2.0 WITH LLVM-exception AND BSD-2-Clause AND CC0-1.0 AND MIT AND Public-Domain AND Unicode ) LICENSE_TEXTS(.yandex_meta/licenses.list.txt) PROVIDES(llvm) VERSION(18.1.8) PEERDIR( contrib/libs/llvm18 ) NO_UTIL() RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/ExecutionEngine/JITLink -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/lib/ExecutionEngine/JITLink/COFFOptions.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/ExecutionEngine/JITLink/COFFOptions.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/ExecutionEngine/JITLink/COFFOptions.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/ExecutionEngine/JITLink/COFFOptions.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/ExecutionEngine/JITLink/COFFOptions.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/ExecutionEngine/JITLink/COFFOptions.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-matcher -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenAsmMatcher.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenAsmMatcher.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenAsmMatcher.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenAsmMatcher.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenAsmWriter.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenAsmWriter.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenAsmWriter.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenAsmWriter.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-writer -asmwriternum=1 -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenAsmWriter1.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenAsmWriter1.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenAsmWriter1.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenAsmWriter1.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-callingconv -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenCallingConv.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenCallingConv.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenCallingConv.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenCallingConv.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target -omit-comments contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenDAGISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenDAGISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenDAGISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenDAGISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-disassembler -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenDisassemblerTables.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenDisassemblerTables.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/MC/MCSubtargetInfo.h llvm/Support/DataTypes.h llvm/Support/Debug.h llvm/Support/LEB128.h llvm/Support/raw_ostream.h llvm/TargetParser/SubtargetFeature.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenDisassemblerTables.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenDisassemblerTables.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-exegesis -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenExegesis.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenExegesis.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenExegesis.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenExegesis.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-fast-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenFastISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenFastISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenFastISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenFastISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-global-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenGlobalISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenGlobalISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenGlobalISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenGlobalISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenInstrInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenInstrInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES sstream OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenInstrInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenInstrInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-pseudo-lowering -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-global-isel-combiner -combiners=AArch64O0PreLegalizerCombiner -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenO0PreLegalizeGICombiner.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenO0PreLegalizeGICombiner.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/ADT/SparseBitVector.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenO0PreLegalizeGICombiner.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenO0PreLegalizeGICombiner.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-global-isel-combiner -combiners=AArch64PostLegalizerCombiner -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/ADT/SparseBitVector.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-global-isel-combiner -combiners=AArch64PostLegalizerLowering -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/ADT/SparseBitVector.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-global-isel-combiner -combiners=AArch64PreLegalizerCombiner -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/ADT/SparseBitVector.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-register-bank -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenRegisterBank.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenRegisterBank.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenRegisterBank.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenRegisterBank.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-register-info -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenRegisterInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenRegisterInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenRegisterInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenRegisterInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenSubtargetInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenSubtargetInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenSubtargetInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenSubtargetInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-searchable-tables -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/AArch64 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/AArch64/AArch64.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenSystemOperands.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenSystemOperands.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/AArch64/AArch64.td contrib/libs/llvm18/lib/Target/AArch64/AArch64CallingConvention.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Combine.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrAtomics.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrGISel.td contrib/libs/llvm18/lib/Target/AArch64/AArch64InstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64PfmCounters.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterBanks.td contrib/libs/llvm18/lib/Target/AArch64/AArch64RegisterInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SMEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SVEInstrInfo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA510.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA53.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA55.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA57WriteRes.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedA64FX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedAmpere1B.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedCyclone.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM3.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM4.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedExynosM5.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkor.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedFalkorDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryo.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedKryoDetails.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseN2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV1.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedNeoverseV2.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredExynos.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredNeoverse.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedPredicates.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedTSV110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX2T99.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SchedThunderX3T110.td contrib/libs/llvm18/lib/Target/AArch64/AArch64Schedule.td contrib/libs/llvm18/lib/Target/AArch64/AArch64SystemOperands.td contrib/libs/llvm18/lib/Target/AArch64/SMEInstrFormats.td contrib/libs/llvm18/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenSystemOperands.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/AArch64/AArch64GenSystemOperands.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-matcher -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/ARM -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/ARM/ARM.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenAsmMatcher.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenAsmMatcher.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/ARM/ARM.td contrib/libs/llvm18/lib/Target/ARM/ARMCallingConv.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrCDE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrFormats.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrMVE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrVFP.td contrib/libs/llvm18/lib/Target/ARM/ARMPredicates.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterBanks.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57WriteRes.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA8.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA9.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM4.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM55.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM7.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM85.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleR52.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleSwift.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleV6.td contrib/libs/llvm18/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenAsmMatcher.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenAsmMatcher.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/ARM -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/ARM/ARM.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenAsmWriter.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenAsmWriter.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/ARM/ARM.td contrib/libs/llvm18/lib/Target/ARM/ARMCallingConv.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrCDE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrFormats.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrMVE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrVFP.td contrib/libs/llvm18/lib/Target/ARM/ARMPredicates.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterBanks.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57WriteRes.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA8.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA9.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM4.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM55.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM7.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM85.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleR52.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleSwift.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleV6.td contrib/libs/llvm18/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenAsmWriter.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenAsmWriter.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-callingconv -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/ARM -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/ARM/ARM.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenCallingConv.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenCallingConv.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/ARM/ARM.td contrib/libs/llvm18/lib/Target/ARM/ARMCallingConv.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrCDE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrFormats.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrMVE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrVFP.td contrib/libs/llvm18/lib/Target/ARM/ARMPredicates.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterBanks.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57WriteRes.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA8.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA9.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM4.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM55.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM7.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM85.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleR52.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleSwift.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleV6.td contrib/libs/llvm18/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenCallingConv.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenCallingConv.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/ARM -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target -omit-comments contrib/libs/llvm18/lib/Target/ARM/ARM.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenDAGISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenDAGISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/ARM/ARM.td contrib/libs/llvm18/lib/Target/ARM/ARMCallingConv.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrCDE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrFormats.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrMVE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrVFP.td contrib/libs/llvm18/lib/Target/ARM/ARMPredicates.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterBanks.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57WriteRes.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA8.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA9.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM4.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM55.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM7.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM85.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleR52.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleSwift.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleV6.td contrib/libs/llvm18/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenDAGISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenDAGISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-disassembler -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/ARM -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/ARM/ARM.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenDisassemblerTables.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenDisassemblerTables.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/ARM/ARM.td contrib/libs/llvm18/lib/Target/ARM/ARMCallingConv.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrCDE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrFormats.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrMVE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrVFP.td contrib/libs/llvm18/lib/Target/ARM/ARMPredicates.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterBanks.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57WriteRes.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA8.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA9.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM4.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM55.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM7.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM85.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleR52.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleSwift.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleV6.td contrib/libs/llvm18/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/MC/MCSubtargetInfo.h llvm/Support/DataTypes.h llvm/Support/Debug.h llvm/Support/LEB128.h llvm/Support/raw_ostream.h llvm/TargetParser/SubtargetFeature.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenDisassemblerTables.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenDisassemblerTables.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-fast-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/ARM -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/ARM/ARM.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenFastISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenFastISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/ARM/ARM.td contrib/libs/llvm18/lib/Target/ARM/ARMCallingConv.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrCDE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrFormats.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrMVE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrVFP.td contrib/libs/llvm18/lib/Target/ARM/ARMPredicates.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterBanks.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57WriteRes.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA8.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA9.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM4.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM55.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM7.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM85.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleR52.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleSwift.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleV6.td contrib/libs/llvm18/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenFastISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenFastISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-global-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/ARM -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/ARM/ARM.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenGlobalISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenGlobalISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/ARM/ARM.td contrib/libs/llvm18/lib/Target/ARM/ARMCallingConv.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrCDE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrFormats.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrMVE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrVFP.td contrib/libs/llvm18/lib/Target/ARM/ARMPredicates.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterBanks.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57WriteRes.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA8.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA9.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM4.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM55.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM7.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM85.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleR52.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleSwift.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleV6.td contrib/libs/llvm18/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenGlobalISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenGlobalISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/ARM -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/ARM/ARM.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenInstrInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenInstrInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/ARM/ARM.td contrib/libs/llvm18/lib/Target/ARM/ARMCallingConv.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrCDE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrFormats.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrMVE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrVFP.td contrib/libs/llvm18/lib/Target/ARM/ARMPredicates.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterBanks.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57WriteRes.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA8.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA9.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM4.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM55.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM7.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM85.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleR52.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleSwift.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleV6.td contrib/libs/llvm18/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES sstream OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenInstrInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenInstrInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/ARM -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/ARM/ARM.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenMCCodeEmitter.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenMCCodeEmitter.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/ARM/ARM.td contrib/libs/llvm18/lib/Target/ARM/ARMCallingConv.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrCDE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrFormats.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrMVE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrVFP.td contrib/libs/llvm18/lib/Target/ARM/ARMPredicates.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterBanks.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57WriteRes.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA8.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA9.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM4.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM55.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM7.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM85.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleR52.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleSwift.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleV6.td contrib/libs/llvm18/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenMCCodeEmitter.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenMCCodeEmitter.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-pseudo-lowering -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/ARM -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/ARM/ARM.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenMCPseudoLowering.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenMCPseudoLowering.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/ARM/ARM.td contrib/libs/llvm18/lib/Target/ARM/ARMCallingConv.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrCDE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrFormats.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrMVE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrVFP.td contrib/libs/llvm18/lib/Target/ARM/ARMPredicates.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterBanks.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57WriteRes.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA8.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA9.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM4.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM55.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM7.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM85.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleR52.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleSwift.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleV6.td contrib/libs/llvm18/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenMCPseudoLowering.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenMCPseudoLowering.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-register-bank -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/ARM -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/ARM/ARM.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenRegisterBank.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenRegisterBank.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/ARM/ARM.td contrib/libs/llvm18/lib/Target/ARM/ARMCallingConv.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrCDE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrFormats.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrMVE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrVFP.td contrib/libs/llvm18/lib/Target/ARM/ARMPredicates.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterBanks.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57WriteRes.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA8.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA9.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM4.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM55.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM7.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM85.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleR52.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleSwift.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleV6.td contrib/libs/llvm18/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenRegisterBank.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenRegisterBank.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-register-info -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/ARM -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/ARM/ARM.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenRegisterInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenRegisterInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/ARM/ARM.td contrib/libs/llvm18/lib/Target/ARM/ARMCallingConv.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrCDE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrFormats.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrMVE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrVFP.td contrib/libs/llvm18/lib/Target/ARM/ARMPredicates.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterBanks.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57WriteRes.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA8.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA9.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM4.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM55.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM7.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM85.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleR52.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleSwift.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleV6.td contrib/libs/llvm18/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenRegisterInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenRegisterInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/ARM -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/ARM/ARM.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenSubtargetInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenSubtargetInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/ARM/ARM.td contrib/libs/llvm18/lib/Target/ARM/ARMCallingConv.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrCDE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrFormats.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrMVE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrVFP.td contrib/libs/llvm18/lib/Target/ARM/ARMPredicates.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterBanks.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57WriteRes.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA8.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA9.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM4.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM55.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM7.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM85.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleR52.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleSwift.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleV6.td contrib/libs/llvm18/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenSubtargetInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenSubtargetInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-searchable-tables -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/ARM -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/ARM/ARM.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenSystemRegister.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenSystemRegister.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/ARM/ARM.td contrib/libs/llvm18/lib/Target/ARM/ARMCallingConv.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrCDE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrFormats.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrMVE.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm18/lib/Target/ARM/ARMInstrVFP.td contrib/libs/llvm18/lib/Target/ARM/ARMPredicates.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterBanks.td contrib/libs/llvm18/lib/Target/ARM/ARMRegisterInfo.td contrib/libs/llvm18/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA57WriteRes.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA8.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleA9.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM4.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM55.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM7.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleM85.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleR52.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleSwift.td contrib/libs/llvm18/lib/Target/ARM/ARMScheduleV6.td contrib/libs/llvm18/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenSystemRegister.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/ARM/ARMGenSystemRegister.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-matcher -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/BPF -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/BPF/BPF.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenAsmMatcher.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenAsmMatcher.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/BPF/BPF.td contrib/libs/llvm18/lib/Target/BPF/BPFCallingConv.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrFormats.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrInfo.td contrib/libs/llvm18/lib/Target/BPF/BPFRegisterInfo.td contrib/libs/llvm18/lib/Target/BPF/GISel/BPFRegisterBanks.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenAsmMatcher.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenAsmMatcher.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/BPF -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/BPF/BPF.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenAsmWriter.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenAsmWriter.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/BPF/BPF.td contrib/libs/llvm18/lib/Target/BPF/BPFCallingConv.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrFormats.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrInfo.td contrib/libs/llvm18/lib/Target/BPF/BPFRegisterInfo.td contrib/libs/llvm18/lib/Target/BPF/GISel/BPFRegisterBanks.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenAsmWriter.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenAsmWriter.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-callingconv -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/BPF -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/BPF/BPF.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenCallingConv.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenCallingConv.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/BPF/BPF.td contrib/libs/llvm18/lib/Target/BPF/BPFCallingConv.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrFormats.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrInfo.td contrib/libs/llvm18/lib/Target/BPF/BPFRegisterInfo.td contrib/libs/llvm18/lib/Target/BPF/GISel/BPFRegisterBanks.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenCallingConv.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenCallingConv.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/BPF -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target -omit-comments contrib/libs/llvm18/lib/Target/BPF/BPF.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenDAGISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenDAGISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/BPF/BPF.td contrib/libs/llvm18/lib/Target/BPF/BPFCallingConv.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrFormats.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrInfo.td contrib/libs/llvm18/lib/Target/BPF/BPFRegisterInfo.td contrib/libs/llvm18/lib/Target/BPF/GISel/BPFRegisterBanks.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenDAGISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenDAGISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-disassembler -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/BPF -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/BPF/BPF.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenDisassemblerTables.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenDisassemblerTables.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/BPF/BPF.td contrib/libs/llvm18/lib/Target/BPF/BPFCallingConv.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrFormats.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrInfo.td contrib/libs/llvm18/lib/Target/BPF/BPFRegisterInfo.td contrib/libs/llvm18/lib/Target/BPF/GISel/BPFRegisterBanks.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/MC/MCSubtargetInfo.h llvm/Support/DataTypes.h llvm/Support/Debug.h llvm/Support/LEB128.h llvm/Support/raw_ostream.h llvm/TargetParser/SubtargetFeature.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenDisassemblerTables.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenDisassemblerTables.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-global-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/BPF -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/BPF/BPF.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenGlobalISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenGlobalISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/BPF/BPF.td contrib/libs/llvm18/lib/Target/BPF/BPFCallingConv.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrFormats.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrInfo.td contrib/libs/llvm18/lib/Target/BPF/BPFRegisterInfo.td contrib/libs/llvm18/lib/Target/BPF/GISel/BPFRegisterBanks.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenGlobalISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenGlobalISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/BPF -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/BPF/BPF.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenInstrInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenInstrInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/BPF/BPF.td contrib/libs/llvm18/lib/Target/BPF/BPFCallingConv.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrFormats.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrInfo.td contrib/libs/llvm18/lib/Target/BPF/BPFRegisterInfo.td contrib/libs/llvm18/lib/Target/BPF/GISel/BPFRegisterBanks.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES sstream OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenInstrInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenInstrInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/BPF -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/BPF/BPF.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenMCCodeEmitter.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenMCCodeEmitter.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/BPF/BPF.td contrib/libs/llvm18/lib/Target/BPF/BPFCallingConv.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrFormats.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrInfo.td contrib/libs/llvm18/lib/Target/BPF/BPFRegisterInfo.td contrib/libs/llvm18/lib/Target/BPF/GISel/BPFRegisterBanks.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenMCCodeEmitter.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenMCCodeEmitter.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-register-bank -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/BPF -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/BPF/BPF.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenRegisterBank.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenRegisterBank.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/BPF/BPF.td contrib/libs/llvm18/lib/Target/BPF/BPFCallingConv.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrFormats.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrInfo.td contrib/libs/llvm18/lib/Target/BPF/BPFRegisterInfo.td contrib/libs/llvm18/lib/Target/BPF/GISel/BPFRegisterBanks.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenRegisterBank.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenRegisterBank.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-register-info -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/BPF -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/BPF/BPF.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenRegisterInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenRegisterInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/BPF/BPF.td contrib/libs/llvm18/lib/Target/BPF/BPFCallingConv.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrFormats.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrInfo.td contrib/libs/llvm18/lib/Target/BPF/BPFRegisterInfo.td contrib/libs/llvm18/lib/Target/BPF/GISel/BPFRegisterBanks.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenRegisterInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenRegisterInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/BPF -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/BPF/BPF.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenSubtargetInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenSubtargetInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/BPF/BPF.td contrib/libs/llvm18/lib/Target/BPF/BPFCallingConv.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrFormats.td contrib/libs/llvm18/lib/Target/BPF/BPFInstrInfo.td contrib/libs/llvm18/lib/Target/BPF/BPFRegisterInfo.td contrib/libs/llvm18/lib/Target/BPF/GISel/BPFRegisterBanks.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenSubtargetInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/BPF/BPFGenSubtargetInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-matcher -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenAsmMatcher.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenAsmMatcher.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchCallingConv.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloatInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLVZInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenAsmMatcher.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenAsmMatcher.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenAsmWriter.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenAsmWriter.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchCallingConv.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloatInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLVZInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenAsmWriter.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenAsmWriter.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target -omit-comments contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenDAGISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenDAGISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchCallingConv.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloatInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLVZInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenDAGISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenDAGISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-disassembler -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenDisassemblerTables.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenDisassemblerTables.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchCallingConv.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloatInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLVZInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/MC/MCSubtargetInfo.h llvm/Support/DataTypes.h llvm/Support/Debug.h llvm/Support/LEB128.h llvm/Support/raw_ostream.h llvm/TargetParser/SubtargetFeature.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenDisassemblerTables.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenDisassemblerTables.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenInstrInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenInstrInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchCallingConv.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloatInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLVZInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES sstream OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenInstrInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenInstrInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenMCCodeEmitter.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenMCCodeEmitter.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchCallingConv.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloatInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLVZInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenMCCodeEmitter.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenMCCodeEmitter.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-pseudo-lowering -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenMCPseudoLowering.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenMCPseudoLowering.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchCallingConv.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloatInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLVZInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenMCPseudoLowering.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenMCPseudoLowering.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-register-info -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenRegisterInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenRegisterInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchCallingConv.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloatInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLVZInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenRegisterInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenRegisterInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenSubtargetInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenSubtargetInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/LoongArch/LoongArch.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchCallingConv.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchFloatInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLASXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLBTInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrFormats.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLSXInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchLVZInstrInfo.td contrib/libs/llvm18/lib/Target/LoongArch/LoongArchRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenSubtargetInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/LoongArch/LoongArchGenSubtargetInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/NVPTX/NVPTX.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenAsmWriter.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenAsmWriter.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXInstrFormats.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXInstrInfo.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXIntrinsics.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenAsmWriter.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenAsmWriter.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target -omit-comments contrib/libs/llvm18/lib/Target/NVPTX/NVPTX.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenDAGISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenDAGISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXInstrFormats.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXInstrInfo.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXIntrinsics.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenDAGISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenDAGISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/NVPTX/NVPTX.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenInstrInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenInstrInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXInstrFormats.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXInstrInfo.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXIntrinsics.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES sstream OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenInstrInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenInstrInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-register-info -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/NVPTX/NVPTX.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXInstrFormats.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXInstrInfo.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXIntrinsics.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/NVPTX/NVPTX.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXInstrFormats.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXInstrInfo.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXIntrinsics.td contrib/libs/llvm18/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-matcher -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/PowerPC/PPC.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenAsmMatcher.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenAsmMatcher.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/PowerPC/GISel/PPCRegisterBanks.td contrib/libs/llvm18/lib/Target/PowerPC/P10InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/P9InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/PPC.td contrib/libs/llvm18/lib/Target/PowerPC/PPCCallingConv.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstr64Bit.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrAltivec.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrDFP.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFormats.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFuture.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFutureMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrHTM.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrSPE.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrVSX.td contrib/libs/llvm18/lib/Target/PowerPC/PPCPfmCounters.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoDMR.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedPredicates.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule440.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleA2.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500mc.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE5500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG3.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4Plus.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG5.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP7.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP8.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenAsmMatcher.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenAsmMatcher.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/PowerPC/PPC.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenAsmWriter.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenAsmWriter.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/PowerPC/GISel/PPCRegisterBanks.td contrib/libs/llvm18/lib/Target/PowerPC/P10InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/P9InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/PPC.td contrib/libs/llvm18/lib/Target/PowerPC/PPCCallingConv.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstr64Bit.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrAltivec.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrDFP.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFormats.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFuture.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFutureMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrHTM.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrSPE.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrVSX.td contrib/libs/llvm18/lib/Target/PowerPC/PPCPfmCounters.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoDMR.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedPredicates.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule440.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleA2.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500mc.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE5500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG3.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4Plus.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG5.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP7.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP8.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenAsmWriter.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenAsmWriter.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-callingconv -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/PowerPC/PPC.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenCallingConv.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenCallingConv.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/PowerPC/GISel/PPCRegisterBanks.td contrib/libs/llvm18/lib/Target/PowerPC/P10InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/P9InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/PPC.td contrib/libs/llvm18/lib/Target/PowerPC/PPCCallingConv.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstr64Bit.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrAltivec.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrDFP.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFormats.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFuture.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFutureMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrHTM.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrSPE.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrVSX.td contrib/libs/llvm18/lib/Target/PowerPC/PPCPfmCounters.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoDMR.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedPredicates.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule440.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleA2.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500mc.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE5500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG3.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4Plus.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG5.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP7.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP8.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenCallingConv.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenCallingConv.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target -omit-comments contrib/libs/llvm18/lib/Target/PowerPC/PPC.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenDAGISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenDAGISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/PowerPC/GISel/PPCRegisterBanks.td contrib/libs/llvm18/lib/Target/PowerPC/P10InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/P9InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/PPC.td contrib/libs/llvm18/lib/Target/PowerPC/PPCCallingConv.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstr64Bit.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrAltivec.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrDFP.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFormats.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFuture.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFutureMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrHTM.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrSPE.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrVSX.td contrib/libs/llvm18/lib/Target/PowerPC/PPCPfmCounters.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoDMR.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedPredicates.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule440.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleA2.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500mc.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE5500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG3.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4Plus.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG5.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP7.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP8.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenDAGISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenDAGISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-disassembler -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/PowerPC/PPC.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenDisassemblerTables.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenDisassemblerTables.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/PowerPC/GISel/PPCRegisterBanks.td contrib/libs/llvm18/lib/Target/PowerPC/P10InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/P9InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/PPC.td contrib/libs/llvm18/lib/Target/PowerPC/PPCCallingConv.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstr64Bit.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrAltivec.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrDFP.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFormats.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFuture.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFutureMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrHTM.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrSPE.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrVSX.td contrib/libs/llvm18/lib/Target/PowerPC/PPCPfmCounters.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoDMR.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedPredicates.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule440.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleA2.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500mc.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE5500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG3.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4Plus.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG5.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP7.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP8.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/MC/MCSubtargetInfo.h llvm/Support/DataTypes.h llvm/Support/Debug.h llvm/Support/LEB128.h llvm/Support/raw_ostream.h llvm/TargetParser/SubtargetFeature.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenDisassemblerTables.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenDisassemblerTables.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-exegesis -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/PowerPC/PPC.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenExegesis.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenExegesis.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/PowerPC/GISel/PPCRegisterBanks.td contrib/libs/llvm18/lib/Target/PowerPC/P10InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/P9InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/PPC.td contrib/libs/llvm18/lib/Target/PowerPC/PPCCallingConv.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstr64Bit.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrAltivec.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrDFP.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFormats.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFuture.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFutureMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrHTM.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrSPE.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrVSX.td contrib/libs/llvm18/lib/Target/PowerPC/PPCPfmCounters.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoDMR.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedPredicates.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule440.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleA2.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500mc.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE5500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG3.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4Plus.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG5.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP7.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP8.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenExegesis.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenExegesis.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-fast-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/PowerPC/PPC.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenFastISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenFastISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/PowerPC/GISel/PPCRegisterBanks.td contrib/libs/llvm18/lib/Target/PowerPC/P10InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/P9InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/PPC.td contrib/libs/llvm18/lib/Target/PowerPC/PPCCallingConv.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstr64Bit.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrAltivec.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrDFP.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFormats.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFuture.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFutureMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrHTM.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrSPE.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrVSX.td contrib/libs/llvm18/lib/Target/PowerPC/PPCPfmCounters.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoDMR.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedPredicates.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule440.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleA2.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500mc.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE5500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG3.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4Plus.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG5.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP7.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP8.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenFastISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenFastISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-global-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/PowerPC/PPC.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenGlobalISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenGlobalISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/PowerPC/GISel/PPCRegisterBanks.td contrib/libs/llvm18/lib/Target/PowerPC/P10InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/P9InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/PPC.td contrib/libs/llvm18/lib/Target/PowerPC/PPCCallingConv.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstr64Bit.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrAltivec.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrDFP.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFormats.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFuture.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFutureMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrHTM.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrSPE.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrVSX.td contrib/libs/llvm18/lib/Target/PowerPC/PPCPfmCounters.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoDMR.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedPredicates.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule440.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleA2.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500mc.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE5500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG3.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4Plus.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG5.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP7.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP8.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenGlobalISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenGlobalISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/PowerPC/PPC.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenInstrInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenInstrInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/PowerPC/GISel/PPCRegisterBanks.td contrib/libs/llvm18/lib/Target/PowerPC/P10InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/P9InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/PPC.td contrib/libs/llvm18/lib/Target/PowerPC/PPCCallingConv.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstr64Bit.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrAltivec.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrDFP.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFormats.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFuture.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFutureMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrHTM.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrSPE.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrVSX.td contrib/libs/llvm18/lib/Target/PowerPC/PPCPfmCounters.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoDMR.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedPredicates.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule440.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleA2.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500mc.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE5500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG3.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4Plus.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG5.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP7.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP8.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES sstream OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenInstrInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenInstrInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/PowerPC/PPC.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/PowerPC/GISel/PPCRegisterBanks.td contrib/libs/llvm18/lib/Target/PowerPC/P10InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/P9InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/PPC.td contrib/libs/llvm18/lib/Target/PowerPC/PPCCallingConv.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstr64Bit.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrAltivec.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrDFP.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFormats.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFuture.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFutureMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrHTM.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrSPE.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrVSX.td contrib/libs/llvm18/lib/Target/PowerPC/PPCPfmCounters.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoDMR.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedPredicates.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule440.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleA2.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500mc.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE5500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG3.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4Plus.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG5.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP7.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP8.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-register-bank -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/PowerPC/PPC.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenRegisterBank.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenRegisterBank.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/PowerPC/GISel/PPCRegisterBanks.td contrib/libs/llvm18/lib/Target/PowerPC/P10InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/P9InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/PPC.td contrib/libs/llvm18/lib/Target/PowerPC/PPCCallingConv.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstr64Bit.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrAltivec.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrDFP.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFormats.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFuture.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFutureMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrHTM.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrSPE.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrVSX.td contrib/libs/llvm18/lib/Target/PowerPC/PPCPfmCounters.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoDMR.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedPredicates.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule440.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleA2.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500mc.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE5500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG3.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4Plus.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG5.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP7.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP8.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenRegisterBank.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenRegisterBank.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-register-info -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/PowerPC/PPC.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenRegisterInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenRegisterInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/PowerPC/GISel/PPCRegisterBanks.td contrib/libs/llvm18/lib/Target/PowerPC/P10InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/P9InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/PPC.td contrib/libs/llvm18/lib/Target/PowerPC/PPCCallingConv.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstr64Bit.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrAltivec.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrDFP.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFormats.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFuture.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFutureMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrHTM.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrSPE.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrVSX.td contrib/libs/llvm18/lib/Target/PowerPC/PPCPfmCounters.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoDMR.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedPredicates.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule440.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleA2.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500mc.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE5500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG3.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4Plus.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG5.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP7.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP8.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenRegisterInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenRegisterInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/PowerPC/PPC.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenSubtargetInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenSubtargetInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/PowerPC/GISel/PPCRegisterBanks.td contrib/libs/llvm18/lib/Target/PowerPC/P10InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/P9InstrResources.td contrib/libs/llvm18/lib/Target/PowerPC/PPC.td contrib/libs/llvm18/lib/Target/PowerPC/PPCCallingConv.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstr64Bit.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrAltivec.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrDFP.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFormats.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFuture.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrFutureMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrHTM.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrSPE.td contrib/libs/llvm18/lib/Target/PowerPC/PPCInstrVSX.td contrib/libs/llvm18/lib/Target/PowerPC/PPCPfmCounters.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfo.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoDMR.td contrib/libs/llvm18/lib/Target/PowerPC/PPCRegisterInfoMMA.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedPredicates.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule.td contrib/libs/llvm18/lib/Target/PowerPC/PPCSchedule440.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleA2.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE500mc.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleE5500.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG3.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG4Plus.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleG5.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP10.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP7.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP8.td contrib/libs/llvm18/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenSubtargetInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/PowerPC/PPCGenSubtargetInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-matcher -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenAsmMatcher.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenAsmMatcher.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrCall.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrControl.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrConv.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFloat.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFormats.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInfo.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInteger.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrRef.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrTable.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenAsmMatcher.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenAsmMatcher.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenAsmWriter.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenAsmWriter.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrCall.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrControl.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrConv.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFloat.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFormats.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInfo.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInteger.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrRef.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrTable.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenAsmWriter.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenAsmWriter.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target -omit-comments contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrCall.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrControl.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrConv.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFloat.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFormats.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInfo.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInteger.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrRef.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrTable.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-disassembler -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenDisassemblerTables.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenDisassemblerTables.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrCall.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrControl.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrConv.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFloat.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFormats.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInfo.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInteger.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrRef.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrTable.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES MCTargetDesc/WebAssemblyMCTargetDesc.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenDisassemblerTables.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenDisassemblerTables.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-fast-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrCall.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrControl.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrConv.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFloat.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFormats.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInfo.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInteger.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrRef.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrTable.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrCall.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrControl.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrConv.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFloat.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFormats.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInfo.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInteger.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrRef.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrTable.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES sstream OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenMCCodeEmitter.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenMCCodeEmitter.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrCall.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrControl.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrConv.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFloat.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFormats.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInfo.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInteger.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrRef.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrTable.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenMCCodeEmitter.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenMCCodeEmitter.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-register-info -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrCall.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrControl.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrConv.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFloat.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFormats.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInfo.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInteger.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrRef.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrTable.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenSubtargetInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenSubtargetInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/WebAssembly/WebAssembly.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrCall.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrControl.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrConv.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFloat.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrFormats.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInfo.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrInteger.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrMemory.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrRef.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyInstrTable.td contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenSubtargetInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/WebAssembly/WebAssemblyGenSubtargetInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-matcher -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/X86 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/X86/X86.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenAsmMatcher.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenAsmMatcher.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/X86/X86.td contrib/libs/llvm18/lib/Target/X86/X86CallingConv.td contrib/libs/llvm18/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm18/lib/Target/X86/X86InstrAMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrAVX512.td contrib/libs/llvm18/lib/Target/X86/X86InstrArithmetic.td contrib/libs/llvm18/lib/Target/X86/X86InstrAsmAlias.td contrib/libs/llvm18/lib/Target/X86/X86InstrCMovSetCC.td contrib/libs/llvm18/lib/Target/X86/X86InstrCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrControl.td contrib/libs/llvm18/lib/Target/X86/X86InstrExtension.td contrib/libs/llvm18/lib/Target/X86/X86InstrFMA.td contrib/libs/llvm18/lib/Target/X86/X86InstrFPStack.td contrib/libs/llvm18/lib/Target/X86/X86InstrFormats.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragments.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragmentsSIMD.td contrib/libs/llvm18/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm18/lib/Target/X86/X86InstrKL.td contrib/libs/llvm18/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrMisc.td contrib/libs/llvm18/lib/Target/X86/X86InstrOperands.td contrib/libs/llvm18/lib/Target/X86/X86InstrPredicates.td contrib/libs/llvm18/lib/Target/X86/X86InstrRAOINT.td contrib/libs/llvm18/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm18/lib/Target/X86/X86InstrSNP.td contrib/libs/llvm18/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm18/lib/Target/X86/X86InstrSVM.td contrib/libs/llvm18/lib/Target/X86/X86InstrShiftRotate.td contrib/libs/llvm18/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm18/lib/Target/X86/X86InstrTBM.td contrib/libs/llvm18/lib/Target/X86/X86InstrTDX.td contrib/libs/llvm18/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm18/lib/Target/X86/X86InstrUtils.td contrib/libs/llvm18/lib/Target/X86/X86InstrVMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrVecCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm18/lib/Target/X86/X86PfmCounters.td contrib/libs/llvm18/lib/Target/X86/X86RegisterBanks.td contrib/libs/llvm18/lib/Target/X86/X86RegisterInfo.td contrib/libs/llvm18/lib/Target/X86/X86SchedAlderlakeP.td contrib/libs/llvm18/lib/Target/X86/X86SchedBroadwell.td contrib/libs/llvm18/lib/Target/X86/X86SchedHaswell.td contrib/libs/llvm18/lib/Target/X86/X86SchedIceLake.td contrib/libs/llvm18/lib/Target/X86/X86SchedPredicates.td contrib/libs/llvm18/lib/Target/X86/X86SchedSandyBridge.td contrib/libs/llvm18/lib/Target/X86/X86SchedSapphireRapids.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeClient.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeServer.td contrib/libs/llvm18/lib/Target/X86/X86Schedule.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleAtom.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBdVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBtVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleSLM.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver1.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver3.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver4.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenAsmMatcher.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenAsmMatcher.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/X86 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/X86/X86.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenAsmWriter.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenAsmWriter.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/X86/X86.td contrib/libs/llvm18/lib/Target/X86/X86CallingConv.td contrib/libs/llvm18/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm18/lib/Target/X86/X86InstrAMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrAVX512.td contrib/libs/llvm18/lib/Target/X86/X86InstrArithmetic.td contrib/libs/llvm18/lib/Target/X86/X86InstrAsmAlias.td contrib/libs/llvm18/lib/Target/X86/X86InstrCMovSetCC.td contrib/libs/llvm18/lib/Target/X86/X86InstrCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrControl.td contrib/libs/llvm18/lib/Target/X86/X86InstrExtension.td contrib/libs/llvm18/lib/Target/X86/X86InstrFMA.td contrib/libs/llvm18/lib/Target/X86/X86InstrFPStack.td contrib/libs/llvm18/lib/Target/X86/X86InstrFormats.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragments.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragmentsSIMD.td contrib/libs/llvm18/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm18/lib/Target/X86/X86InstrKL.td contrib/libs/llvm18/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrMisc.td contrib/libs/llvm18/lib/Target/X86/X86InstrOperands.td contrib/libs/llvm18/lib/Target/X86/X86InstrPredicates.td contrib/libs/llvm18/lib/Target/X86/X86InstrRAOINT.td contrib/libs/llvm18/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm18/lib/Target/X86/X86InstrSNP.td contrib/libs/llvm18/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm18/lib/Target/X86/X86InstrSVM.td contrib/libs/llvm18/lib/Target/X86/X86InstrShiftRotate.td contrib/libs/llvm18/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm18/lib/Target/X86/X86InstrTBM.td contrib/libs/llvm18/lib/Target/X86/X86InstrTDX.td contrib/libs/llvm18/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm18/lib/Target/X86/X86InstrUtils.td contrib/libs/llvm18/lib/Target/X86/X86InstrVMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrVecCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm18/lib/Target/X86/X86PfmCounters.td contrib/libs/llvm18/lib/Target/X86/X86RegisterBanks.td contrib/libs/llvm18/lib/Target/X86/X86RegisterInfo.td contrib/libs/llvm18/lib/Target/X86/X86SchedAlderlakeP.td contrib/libs/llvm18/lib/Target/X86/X86SchedBroadwell.td contrib/libs/llvm18/lib/Target/X86/X86SchedHaswell.td contrib/libs/llvm18/lib/Target/X86/X86SchedIceLake.td contrib/libs/llvm18/lib/Target/X86/X86SchedPredicates.td contrib/libs/llvm18/lib/Target/X86/X86SchedSandyBridge.td contrib/libs/llvm18/lib/Target/X86/X86SchedSapphireRapids.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeClient.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeServer.td contrib/libs/llvm18/lib/Target/X86/X86Schedule.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleAtom.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBdVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBtVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleSLM.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver1.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver3.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver4.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenAsmWriter.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenAsmWriter.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-asm-writer -asmwriternum=1 -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/X86 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/X86/X86.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenAsmWriter1.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenAsmWriter1.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/X86/X86.td contrib/libs/llvm18/lib/Target/X86/X86CallingConv.td contrib/libs/llvm18/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm18/lib/Target/X86/X86InstrAMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrAVX512.td contrib/libs/llvm18/lib/Target/X86/X86InstrArithmetic.td contrib/libs/llvm18/lib/Target/X86/X86InstrAsmAlias.td contrib/libs/llvm18/lib/Target/X86/X86InstrCMovSetCC.td contrib/libs/llvm18/lib/Target/X86/X86InstrCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrControl.td contrib/libs/llvm18/lib/Target/X86/X86InstrExtension.td contrib/libs/llvm18/lib/Target/X86/X86InstrFMA.td contrib/libs/llvm18/lib/Target/X86/X86InstrFPStack.td contrib/libs/llvm18/lib/Target/X86/X86InstrFormats.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragments.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragmentsSIMD.td contrib/libs/llvm18/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm18/lib/Target/X86/X86InstrKL.td contrib/libs/llvm18/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrMisc.td contrib/libs/llvm18/lib/Target/X86/X86InstrOperands.td contrib/libs/llvm18/lib/Target/X86/X86InstrPredicates.td contrib/libs/llvm18/lib/Target/X86/X86InstrRAOINT.td contrib/libs/llvm18/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm18/lib/Target/X86/X86InstrSNP.td contrib/libs/llvm18/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm18/lib/Target/X86/X86InstrSVM.td contrib/libs/llvm18/lib/Target/X86/X86InstrShiftRotate.td contrib/libs/llvm18/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm18/lib/Target/X86/X86InstrTBM.td contrib/libs/llvm18/lib/Target/X86/X86InstrTDX.td contrib/libs/llvm18/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm18/lib/Target/X86/X86InstrUtils.td contrib/libs/llvm18/lib/Target/X86/X86InstrVMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrVecCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm18/lib/Target/X86/X86PfmCounters.td contrib/libs/llvm18/lib/Target/X86/X86RegisterBanks.td contrib/libs/llvm18/lib/Target/X86/X86RegisterInfo.td contrib/libs/llvm18/lib/Target/X86/X86SchedAlderlakeP.td contrib/libs/llvm18/lib/Target/X86/X86SchedBroadwell.td contrib/libs/llvm18/lib/Target/X86/X86SchedHaswell.td contrib/libs/llvm18/lib/Target/X86/X86SchedIceLake.td contrib/libs/llvm18/lib/Target/X86/X86SchedPredicates.td contrib/libs/llvm18/lib/Target/X86/X86SchedSandyBridge.td contrib/libs/llvm18/lib/Target/X86/X86SchedSapphireRapids.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeClient.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeServer.td contrib/libs/llvm18/lib/Target/X86/X86Schedule.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleAtom.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBdVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBtVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleSLM.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver1.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver3.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver4.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenAsmWriter1.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenAsmWriter1.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-callingconv -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/X86 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/X86/X86.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenCallingConv.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenCallingConv.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/X86/X86.td contrib/libs/llvm18/lib/Target/X86/X86CallingConv.td contrib/libs/llvm18/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm18/lib/Target/X86/X86InstrAMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrAVX512.td contrib/libs/llvm18/lib/Target/X86/X86InstrArithmetic.td contrib/libs/llvm18/lib/Target/X86/X86InstrAsmAlias.td contrib/libs/llvm18/lib/Target/X86/X86InstrCMovSetCC.td contrib/libs/llvm18/lib/Target/X86/X86InstrCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrControl.td contrib/libs/llvm18/lib/Target/X86/X86InstrExtension.td contrib/libs/llvm18/lib/Target/X86/X86InstrFMA.td contrib/libs/llvm18/lib/Target/X86/X86InstrFPStack.td contrib/libs/llvm18/lib/Target/X86/X86InstrFormats.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragments.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragmentsSIMD.td contrib/libs/llvm18/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm18/lib/Target/X86/X86InstrKL.td contrib/libs/llvm18/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrMisc.td contrib/libs/llvm18/lib/Target/X86/X86InstrOperands.td contrib/libs/llvm18/lib/Target/X86/X86InstrPredicates.td contrib/libs/llvm18/lib/Target/X86/X86InstrRAOINT.td contrib/libs/llvm18/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm18/lib/Target/X86/X86InstrSNP.td contrib/libs/llvm18/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm18/lib/Target/X86/X86InstrSVM.td contrib/libs/llvm18/lib/Target/X86/X86InstrShiftRotate.td contrib/libs/llvm18/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm18/lib/Target/X86/X86InstrTBM.td contrib/libs/llvm18/lib/Target/X86/X86InstrTDX.td contrib/libs/llvm18/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm18/lib/Target/X86/X86InstrUtils.td contrib/libs/llvm18/lib/Target/X86/X86InstrVMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrVecCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm18/lib/Target/X86/X86PfmCounters.td contrib/libs/llvm18/lib/Target/X86/X86RegisterBanks.td contrib/libs/llvm18/lib/Target/X86/X86RegisterInfo.td contrib/libs/llvm18/lib/Target/X86/X86SchedAlderlakeP.td contrib/libs/llvm18/lib/Target/X86/X86SchedBroadwell.td contrib/libs/llvm18/lib/Target/X86/X86SchedHaswell.td contrib/libs/llvm18/lib/Target/X86/X86SchedIceLake.td contrib/libs/llvm18/lib/Target/X86/X86SchedPredicates.td contrib/libs/llvm18/lib/Target/X86/X86SchedSandyBridge.td contrib/libs/llvm18/lib/Target/X86/X86SchedSapphireRapids.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeClient.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeServer.td contrib/libs/llvm18/lib/Target/X86/X86Schedule.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleAtom.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBdVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBtVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleSLM.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver1.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver3.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver4.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenCallingConv.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenCallingConv.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-x86-compress-evex-tables -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/X86 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/X86/X86.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenCompressEVEXTables.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenCompressEVEXTables.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/X86/X86.td contrib/libs/llvm18/lib/Target/X86/X86CallingConv.td contrib/libs/llvm18/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm18/lib/Target/X86/X86InstrAMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrAVX512.td contrib/libs/llvm18/lib/Target/X86/X86InstrArithmetic.td contrib/libs/llvm18/lib/Target/X86/X86InstrAsmAlias.td contrib/libs/llvm18/lib/Target/X86/X86InstrCMovSetCC.td contrib/libs/llvm18/lib/Target/X86/X86InstrCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrControl.td contrib/libs/llvm18/lib/Target/X86/X86InstrExtension.td contrib/libs/llvm18/lib/Target/X86/X86InstrFMA.td contrib/libs/llvm18/lib/Target/X86/X86InstrFPStack.td contrib/libs/llvm18/lib/Target/X86/X86InstrFormats.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragments.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragmentsSIMD.td contrib/libs/llvm18/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm18/lib/Target/X86/X86InstrKL.td contrib/libs/llvm18/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrMisc.td contrib/libs/llvm18/lib/Target/X86/X86InstrOperands.td contrib/libs/llvm18/lib/Target/X86/X86InstrPredicates.td contrib/libs/llvm18/lib/Target/X86/X86InstrRAOINT.td contrib/libs/llvm18/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm18/lib/Target/X86/X86InstrSNP.td contrib/libs/llvm18/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm18/lib/Target/X86/X86InstrSVM.td contrib/libs/llvm18/lib/Target/X86/X86InstrShiftRotate.td contrib/libs/llvm18/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm18/lib/Target/X86/X86InstrTBM.td contrib/libs/llvm18/lib/Target/X86/X86InstrTDX.td contrib/libs/llvm18/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm18/lib/Target/X86/X86InstrUtils.td contrib/libs/llvm18/lib/Target/X86/X86InstrVMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrVecCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm18/lib/Target/X86/X86PfmCounters.td contrib/libs/llvm18/lib/Target/X86/X86RegisterBanks.td contrib/libs/llvm18/lib/Target/X86/X86RegisterInfo.td contrib/libs/llvm18/lib/Target/X86/X86SchedAlderlakeP.td contrib/libs/llvm18/lib/Target/X86/X86SchedBroadwell.td contrib/libs/llvm18/lib/Target/X86/X86SchedHaswell.td contrib/libs/llvm18/lib/Target/X86/X86SchedIceLake.td contrib/libs/llvm18/lib/Target/X86/X86SchedPredicates.td contrib/libs/llvm18/lib/Target/X86/X86SchedSandyBridge.td contrib/libs/llvm18/lib/Target/X86/X86SchedSapphireRapids.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeClient.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeServer.td contrib/libs/llvm18/lib/Target/X86/X86Schedule.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleAtom.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBdVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBtVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleSLM.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver1.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver3.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver4.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenCompressEVEXTables.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenCompressEVEXTables.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/X86 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target -omit-comments contrib/libs/llvm18/lib/Target/X86/X86.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenDAGISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenDAGISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/X86/X86.td contrib/libs/llvm18/lib/Target/X86/X86CallingConv.td contrib/libs/llvm18/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm18/lib/Target/X86/X86InstrAMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrAVX512.td contrib/libs/llvm18/lib/Target/X86/X86InstrArithmetic.td contrib/libs/llvm18/lib/Target/X86/X86InstrAsmAlias.td contrib/libs/llvm18/lib/Target/X86/X86InstrCMovSetCC.td contrib/libs/llvm18/lib/Target/X86/X86InstrCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrControl.td contrib/libs/llvm18/lib/Target/X86/X86InstrExtension.td contrib/libs/llvm18/lib/Target/X86/X86InstrFMA.td contrib/libs/llvm18/lib/Target/X86/X86InstrFPStack.td contrib/libs/llvm18/lib/Target/X86/X86InstrFormats.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragments.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragmentsSIMD.td contrib/libs/llvm18/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm18/lib/Target/X86/X86InstrKL.td contrib/libs/llvm18/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrMisc.td contrib/libs/llvm18/lib/Target/X86/X86InstrOperands.td contrib/libs/llvm18/lib/Target/X86/X86InstrPredicates.td contrib/libs/llvm18/lib/Target/X86/X86InstrRAOINT.td contrib/libs/llvm18/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm18/lib/Target/X86/X86InstrSNP.td contrib/libs/llvm18/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm18/lib/Target/X86/X86InstrSVM.td contrib/libs/llvm18/lib/Target/X86/X86InstrShiftRotate.td contrib/libs/llvm18/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm18/lib/Target/X86/X86InstrTBM.td contrib/libs/llvm18/lib/Target/X86/X86InstrTDX.td contrib/libs/llvm18/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm18/lib/Target/X86/X86InstrUtils.td contrib/libs/llvm18/lib/Target/X86/X86InstrVMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrVecCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm18/lib/Target/X86/X86PfmCounters.td contrib/libs/llvm18/lib/Target/X86/X86RegisterBanks.td contrib/libs/llvm18/lib/Target/X86/X86RegisterInfo.td contrib/libs/llvm18/lib/Target/X86/X86SchedAlderlakeP.td contrib/libs/llvm18/lib/Target/X86/X86SchedBroadwell.td contrib/libs/llvm18/lib/Target/X86/X86SchedHaswell.td contrib/libs/llvm18/lib/Target/X86/X86SchedIceLake.td contrib/libs/llvm18/lib/Target/X86/X86SchedPredicates.td contrib/libs/llvm18/lib/Target/X86/X86SchedSandyBridge.td contrib/libs/llvm18/lib/Target/X86/X86SchedSapphireRapids.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeClient.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeServer.td contrib/libs/llvm18/lib/Target/X86/X86Schedule.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleAtom.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBdVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBtVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleSLM.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver1.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver3.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver4.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenDAGISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenDAGISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-disassembler -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/X86 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/X86/X86.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenDisassemblerTables.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenDisassemblerTables.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/X86/X86.td contrib/libs/llvm18/lib/Target/X86/X86CallingConv.td contrib/libs/llvm18/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm18/lib/Target/X86/X86InstrAMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrAVX512.td contrib/libs/llvm18/lib/Target/X86/X86InstrArithmetic.td contrib/libs/llvm18/lib/Target/X86/X86InstrAsmAlias.td contrib/libs/llvm18/lib/Target/X86/X86InstrCMovSetCC.td contrib/libs/llvm18/lib/Target/X86/X86InstrCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrControl.td contrib/libs/llvm18/lib/Target/X86/X86InstrExtension.td contrib/libs/llvm18/lib/Target/X86/X86InstrFMA.td contrib/libs/llvm18/lib/Target/X86/X86InstrFPStack.td contrib/libs/llvm18/lib/Target/X86/X86InstrFormats.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragments.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragmentsSIMD.td contrib/libs/llvm18/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm18/lib/Target/X86/X86InstrKL.td contrib/libs/llvm18/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrMisc.td contrib/libs/llvm18/lib/Target/X86/X86InstrOperands.td contrib/libs/llvm18/lib/Target/X86/X86InstrPredicates.td contrib/libs/llvm18/lib/Target/X86/X86InstrRAOINT.td contrib/libs/llvm18/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm18/lib/Target/X86/X86InstrSNP.td contrib/libs/llvm18/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm18/lib/Target/X86/X86InstrSVM.td contrib/libs/llvm18/lib/Target/X86/X86InstrShiftRotate.td contrib/libs/llvm18/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm18/lib/Target/X86/X86InstrTBM.td contrib/libs/llvm18/lib/Target/X86/X86InstrTDX.td contrib/libs/llvm18/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm18/lib/Target/X86/X86InstrUtils.td contrib/libs/llvm18/lib/Target/X86/X86InstrVMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrVecCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm18/lib/Target/X86/X86PfmCounters.td contrib/libs/llvm18/lib/Target/X86/X86RegisterBanks.td contrib/libs/llvm18/lib/Target/X86/X86RegisterInfo.td contrib/libs/llvm18/lib/Target/X86/X86SchedAlderlakeP.td contrib/libs/llvm18/lib/Target/X86/X86SchedBroadwell.td contrib/libs/llvm18/lib/Target/X86/X86SchedHaswell.td contrib/libs/llvm18/lib/Target/X86/X86SchedIceLake.td contrib/libs/llvm18/lib/Target/X86/X86SchedPredicates.td contrib/libs/llvm18/lib/Target/X86/X86SchedSandyBridge.td contrib/libs/llvm18/lib/Target/X86/X86SchedSapphireRapids.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeClient.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeServer.td contrib/libs/llvm18/lib/Target/X86/X86Schedule.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleAtom.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBdVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBtVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleSLM.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver1.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver3.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver4.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenDisassemblerTables.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenDisassemblerTables.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-exegesis -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/X86 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/X86/X86.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenExegesis.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenExegesis.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/X86/X86.td contrib/libs/llvm18/lib/Target/X86/X86CallingConv.td contrib/libs/llvm18/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm18/lib/Target/X86/X86InstrAMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrAVX512.td contrib/libs/llvm18/lib/Target/X86/X86InstrArithmetic.td contrib/libs/llvm18/lib/Target/X86/X86InstrAsmAlias.td contrib/libs/llvm18/lib/Target/X86/X86InstrCMovSetCC.td contrib/libs/llvm18/lib/Target/X86/X86InstrCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrControl.td contrib/libs/llvm18/lib/Target/X86/X86InstrExtension.td contrib/libs/llvm18/lib/Target/X86/X86InstrFMA.td contrib/libs/llvm18/lib/Target/X86/X86InstrFPStack.td contrib/libs/llvm18/lib/Target/X86/X86InstrFormats.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragments.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragmentsSIMD.td contrib/libs/llvm18/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm18/lib/Target/X86/X86InstrKL.td contrib/libs/llvm18/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrMisc.td contrib/libs/llvm18/lib/Target/X86/X86InstrOperands.td contrib/libs/llvm18/lib/Target/X86/X86InstrPredicates.td contrib/libs/llvm18/lib/Target/X86/X86InstrRAOINT.td contrib/libs/llvm18/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm18/lib/Target/X86/X86InstrSNP.td contrib/libs/llvm18/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm18/lib/Target/X86/X86InstrSVM.td contrib/libs/llvm18/lib/Target/X86/X86InstrShiftRotate.td contrib/libs/llvm18/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm18/lib/Target/X86/X86InstrTBM.td contrib/libs/llvm18/lib/Target/X86/X86InstrTDX.td contrib/libs/llvm18/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm18/lib/Target/X86/X86InstrUtils.td contrib/libs/llvm18/lib/Target/X86/X86InstrVMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrVecCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm18/lib/Target/X86/X86PfmCounters.td contrib/libs/llvm18/lib/Target/X86/X86RegisterBanks.td contrib/libs/llvm18/lib/Target/X86/X86RegisterInfo.td contrib/libs/llvm18/lib/Target/X86/X86SchedAlderlakeP.td contrib/libs/llvm18/lib/Target/X86/X86SchedBroadwell.td contrib/libs/llvm18/lib/Target/X86/X86SchedHaswell.td contrib/libs/llvm18/lib/Target/X86/X86SchedIceLake.td contrib/libs/llvm18/lib/Target/X86/X86SchedPredicates.td contrib/libs/llvm18/lib/Target/X86/X86SchedSandyBridge.td contrib/libs/llvm18/lib/Target/X86/X86SchedSapphireRapids.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeClient.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeServer.td contrib/libs/llvm18/lib/Target/X86/X86Schedule.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleAtom.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBdVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBtVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleSLM.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver1.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver3.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver4.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenExegesis.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenExegesis.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-fast-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/X86 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/X86/X86.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenFastISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenFastISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/X86/X86.td contrib/libs/llvm18/lib/Target/X86/X86CallingConv.td contrib/libs/llvm18/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm18/lib/Target/X86/X86InstrAMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrAVX512.td contrib/libs/llvm18/lib/Target/X86/X86InstrArithmetic.td contrib/libs/llvm18/lib/Target/X86/X86InstrAsmAlias.td contrib/libs/llvm18/lib/Target/X86/X86InstrCMovSetCC.td contrib/libs/llvm18/lib/Target/X86/X86InstrCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrControl.td contrib/libs/llvm18/lib/Target/X86/X86InstrExtension.td contrib/libs/llvm18/lib/Target/X86/X86InstrFMA.td contrib/libs/llvm18/lib/Target/X86/X86InstrFPStack.td contrib/libs/llvm18/lib/Target/X86/X86InstrFormats.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragments.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragmentsSIMD.td contrib/libs/llvm18/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm18/lib/Target/X86/X86InstrKL.td contrib/libs/llvm18/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrMisc.td contrib/libs/llvm18/lib/Target/X86/X86InstrOperands.td contrib/libs/llvm18/lib/Target/X86/X86InstrPredicates.td contrib/libs/llvm18/lib/Target/X86/X86InstrRAOINT.td contrib/libs/llvm18/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm18/lib/Target/X86/X86InstrSNP.td contrib/libs/llvm18/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm18/lib/Target/X86/X86InstrSVM.td contrib/libs/llvm18/lib/Target/X86/X86InstrShiftRotate.td contrib/libs/llvm18/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm18/lib/Target/X86/X86InstrTBM.td contrib/libs/llvm18/lib/Target/X86/X86InstrTDX.td contrib/libs/llvm18/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm18/lib/Target/X86/X86InstrUtils.td contrib/libs/llvm18/lib/Target/X86/X86InstrVMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrVecCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm18/lib/Target/X86/X86PfmCounters.td contrib/libs/llvm18/lib/Target/X86/X86RegisterBanks.td contrib/libs/llvm18/lib/Target/X86/X86RegisterInfo.td contrib/libs/llvm18/lib/Target/X86/X86SchedAlderlakeP.td contrib/libs/llvm18/lib/Target/X86/X86SchedBroadwell.td contrib/libs/llvm18/lib/Target/X86/X86SchedHaswell.td contrib/libs/llvm18/lib/Target/X86/X86SchedIceLake.td contrib/libs/llvm18/lib/Target/X86/X86SchedPredicates.td contrib/libs/llvm18/lib/Target/X86/X86SchedSandyBridge.td contrib/libs/llvm18/lib/Target/X86/X86SchedSapphireRapids.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeClient.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeServer.td contrib/libs/llvm18/lib/Target/X86/X86Schedule.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleAtom.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBdVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBtVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleSLM.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver1.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver3.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver4.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenFastISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenFastISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-x86-fold-tables -asmwriternum=1 -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/X86 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/X86/X86.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenFoldTables.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenFoldTables.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/X86/X86.td contrib/libs/llvm18/lib/Target/X86/X86CallingConv.td contrib/libs/llvm18/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm18/lib/Target/X86/X86InstrAMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrAVX512.td contrib/libs/llvm18/lib/Target/X86/X86InstrArithmetic.td contrib/libs/llvm18/lib/Target/X86/X86InstrAsmAlias.td contrib/libs/llvm18/lib/Target/X86/X86InstrCMovSetCC.td contrib/libs/llvm18/lib/Target/X86/X86InstrCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrControl.td contrib/libs/llvm18/lib/Target/X86/X86InstrExtension.td contrib/libs/llvm18/lib/Target/X86/X86InstrFMA.td contrib/libs/llvm18/lib/Target/X86/X86InstrFPStack.td contrib/libs/llvm18/lib/Target/X86/X86InstrFormats.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragments.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragmentsSIMD.td contrib/libs/llvm18/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm18/lib/Target/X86/X86InstrKL.td contrib/libs/llvm18/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrMisc.td contrib/libs/llvm18/lib/Target/X86/X86InstrOperands.td contrib/libs/llvm18/lib/Target/X86/X86InstrPredicates.td contrib/libs/llvm18/lib/Target/X86/X86InstrRAOINT.td contrib/libs/llvm18/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm18/lib/Target/X86/X86InstrSNP.td contrib/libs/llvm18/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm18/lib/Target/X86/X86InstrSVM.td contrib/libs/llvm18/lib/Target/X86/X86InstrShiftRotate.td contrib/libs/llvm18/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm18/lib/Target/X86/X86InstrTBM.td contrib/libs/llvm18/lib/Target/X86/X86InstrTDX.td contrib/libs/llvm18/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm18/lib/Target/X86/X86InstrUtils.td contrib/libs/llvm18/lib/Target/X86/X86InstrVMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrVecCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm18/lib/Target/X86/X86PfmCounters.td contrib/libs/llvm18/lib/Target/X86/X86RegisterBanks.td contrib/libs/llvm18/lib/Target/X86/X86RegisterInfo.td contrib/libs/llvm18/lib/Target/X86/X86SchedAlderlakeP.td contrib/libs/llvm18/lib/Target/X86/X86SchedBroadwell.td contrib/libs/llvm18/lib/Target/X86/X86SchedHaswell.td contrib/libs/llvm18/lib/Target/X86/X86SchedIceLake.td contrib/libs/llvm18/lib/Target/X86/X86SchedPredicates.td contrib/libs/llvm18/lib/Target/X86/X86SchedSandyBridge.td contrib/libs/llvm18/lib/Target/X86/X86SchedSapphireRapids.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeClient.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeServer.td contrib/libs/llvm18/lib/Target/X86/X86Schedule.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleAtom.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBdVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBtVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleSLM.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver1.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver3.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver4.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenFoldTables.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenFoldTables.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-global-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/X86 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/X86/X86.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenGlobalISel.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenGlobalISel.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/X86/X86.td contrib/libs/llvm18/lib/Target/X86/X86CallingConv.td contrib/libs/llvm18/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm18/lib/Target/X86/X86InstrAMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrAVX512.td contrib/libs/llvm18/lib/Target/X86/X86InstrArithmetic.td contrib/libs/llvm18/lib/Target/X86/X86InstrAsmAlias.td contrib/libs/llvm18/lib/Target/X86/X86InstrCMovSetCC.td contrib/libs/llvm18/lib/Target/X86/X86InstrCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrControl.td contrib/libs/llvm18/lib/Target/X86/X86InstrExtension.td contrib/libs/llvm18/lib/Target/X86/X86InstrFMA.td contrib/libs/llvm18/lib/Target/X86/X86InstrFPStack.td contrib/libs/llvm18/lib/Target/X86/X86InstrFormats.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragments.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragmentsSIMD.td contrib/libs/llvm18/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm18/lib/Target/X86/X86InstrKL.td contrib/libs/llvm18/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrMisc.td contrib/libs/llvm18/lib/Target/X86/X86InstrOperands.td contrib/libs/llvm18/lib/Target/X86/X86InstrPredicates.td contrib/libs/llvm18/lib/Target/X86/X86InstrRAOINT.td contrib/libs/llvm18/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm18/lib/Target/X86/X86InstrSNP.td contrib/libs/llvm18/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm18/lib/Target/X86/X86InstrSVM.td contrib/libs/llvm18/lib/Target/X86/X86InstrShiftRotate.td contrib/libs/llvm18/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm18/lib/Target/X86/X86InstrTBM.td contrib/libs/llvm18/lib/Target/X86/X86InstrTDX.td contrib/libs/llvm18/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm18/lib/Target/X86/X86InstrUtils.td contrib/libs/llvm18/lib/Target/X86/X86InstrVMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrVecCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm18/lib/Target/X86/X86PfmCounters.td contrib/libs/llvm18/lib/Target/X86/X86RegisterBanks.td contrib/libs/llvm18/lib/Target/X86/X86RegisterInfo.td contrib/libs/llvm18/lib/Target/X86/X86SchedAlderlakeP.td contrib/libs/llvm18/lib/Target/X86/X86SchedBroadwell.td contrib/libs/llvm18/lib/Target/X86/X86SchedHaswell.td contrib/libs/llvm18/lib/Target/X86/X86SchedIceLake.td contrib/libs/llvm18/lib/Target/X86/X86SchedPredicates.td contrib/libs/llvm18/lib/Target/X86/X86SchedSandyBridge.td contrib/libs/llvm18/lib/Target/X86/X86SchedSapphireRapids.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeClient.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeServer.td contrib/libs/llvm18/lib/Target/X86/X86Schedule.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleAtom.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBdVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBtVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleSLM.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver1.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver3.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver4.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenGlobalISel.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenGlobalISel.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-instr-info -instr-info-expand-mi-operand-info=0 -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/X86 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/X86/X86.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenInstrInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenInstrInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/X86/X86.td contrib/libs/llvm18/lib/Target/X86/X86CallingConv.td contrib/libs/llvm18/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm18/lib/Target/X86/X86InstrAMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrAVX512.td contrib/libs/llvm18/lib/Target/X86/X86InstrArithmetic.td contrib/libs/llvm18/lib/Target/X86/X86InstrAsmAlias.td contrib/libs/llvm18/lib/Target/X86/X86InstrCMovSetCC.td contrib/libs/llvm18/lib/Target/X86/X86InstrCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrControl.td contrib/libs/llvm18/lib/Target/X86/X86InstrExtension.td contrib/libs/llvm18/lib/Target/X86/X86InstrFMA.td contrib/libs/llvm18/lib/Target/X86/X86InstrFPStack.td contrib/libs/llvm18/lib/Target/X86/X86InstrFormats.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragments.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragmentsSIMD.td contrib/libs/llvm18/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm18/lib/Target/X86/X86InstrKL.td contrib/libs/llvm18/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrMisc.td contrib/libs/llvm18/lib/Target/X86/X86InstrOperands.td contrib/libs/llvm18/lib/Target/X86/X86InstrPredicates.td contrib/libs/llvm18/lib/Target/X86/X86InstrRAOINT.td contrib/libs/llvm18/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm18/lib/Target/X86/X86InstrSNP.td contrib/libs/llvm18/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm18/lib/Target/X86/X86InstrSVM.td contrib/libs/llvm18/lib/Target/X86/X86InstrShiftRotate.td contrib/libs/llvm18/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm18/lib/Target/X86/X86InstrTBM.td contrib/libs/llvm18/lib/Target/X86/X86InstrTDX.td contrib/libs/llvm18/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm18/lib/Target/X86/X86InstrUtils.td contrib/libs/llvm18/lib/Target/X86/X86InstrVMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrVecCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm18/lib/Target/X86/X86PfmCounters.td contrib/libs/llvm18/lib/Target/X86/X86RegisterBanks.td contrib/libs/llvm18/lib/Target/X86/X86RegisterInfo.td contrib/libs/llvm18/lib/Target/X86/X86SchedAlderlakeP.td contrib/libs/llvm18/lib/Target/X86/X86SchedBroadwell.td contrib/libs/llvm18/lib/Target/X86/X86SchedHaswell.td contrib/libs/llvm18/lib/Target/X86/X86SchedIceLake.td contrib/libs/llvm18/lib/Target/X86/X86SchedPredicates.td contrib/libs/llvm18/lib/Target/X86/X86SchedSandyBridge.td contrib/libs/llvm18/lib/Target/X86/X86SchedSapphireRapids.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeClient.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeServer.td contrib/libs/llvm18/lib/Target/X86/X86Schedule.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleAtom.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBdVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBtVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleSLM.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver1.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver3.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver4.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES sstream OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenInstrInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenInstrInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-x86-mnemonic-tables -asmwriternum=1 -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/X86 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/X86/X86.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenMnemonicTables.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenMnemonicTables.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/X86/X86.td contrib/libs/llvm18/lib/Target/X86/X86CallingConv.td contrib/libs/llvm18/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm18/lib/Target/X86/X86InstrAMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrAVX512.td contrib/libs/llvm18/lib/Target/X86/X86InstrArithmetic.td contrib/libs/llvm18/lib/Target/X86/X86InstrAsmAlias.td contrib/libs/llvm18/lib/Target/X86/X86InstrCMovSetCC.td contrib/libs/llvm18/lib/Target/X86/X86InstrCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrControl.td contrib/libs/llvm18/lib/Target/X86/X86InstrExtension.td contrib/libs/llvm18/lib/Target/X86/X86InstrFMA.td contrib/libs/llvm18/lib/Target/X86/X86InstrFPStack.td contrib/libs/llvm18/lib/Target/X86/X86InstrFormats.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragments.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragmentsSIMD.td contrib/libs/llvm18/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm18/lib/Target/X86/X86InstrKL.td contrib/libs/llvm18/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrMisc.td contrib/libs/llvm18/lib/Target/X86/X86InstrOperands.td contrib/libs/llvm18/lib/Target/X86/X86InstrPredicates.td contrib/libs/llvm18/lib/Target/X86/X86InstrRAOINT.td contrib/libs/llvm18/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm18/lib/Target/X86/X86InstrSNP.td contrib/libs/llvm18/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm18/lib/Target/X86/X86InstrSVM.td contrib/libs/llvm18/lib/Target/X86/X86InstrShiftRotate.td contrib/libs/llvm18/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm18/lib/Target/X86/X86InstrTBM.td contrib/libs/llvm18/lib/Target/X86/X86InstrTDX.td contrib/libs/llvm18/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm18/lib/Target/X86/X86InstrUtils.td contrib/libs/llvm18/lib/Target/X86/X86InstrVMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrVecCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm18/lib/Target/X86/X86PfmCounters.td contrib/libs/llvm18/lib/Target/X86/X86RegisterBanks.td contrib/libs/llvm18/lib/Target/X86/X86RegisterInfo.td contrib/libs/llvm18/lib/Target/X86/X86SchedAlderlakeP.td contrib/libs/llvm18/lib/Target/X86/X86SchedBroadwell.td contrib/libs/llvm18/lib/Target/X86/X86SchedHaswell.td contrib/libs/llvm18/lib/Target/X86/X86SchedIceLake.td contrib/libs/llvm18/lib/Target/X86/X86SchedPredicates.td contrib/libs/llvm18/lib/Target/X86/X86SchedSandyBridge.td contrib/libs/llvm18/lib/Target/X86/X86SchedSapphireRapids.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeClient.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeServer.td contrib/libs/llvm18/lib/Target/X86/X86Schedule.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleAtom.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBdVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBtVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleSLM.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver1.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver3.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver4.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenMnemonicTables.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenMnemonicTables.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-register-bank -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/X86 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/X86/X86.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenRegisterBank.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenRegisterBank.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/X86/X86.td contrib/libs/llvm18/lib/Target/X86/X86CallingConv.td contrib/libs/llvm18/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm18/lib/Target/X86/X86InstrAMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrAVX512.td contrib/libs/llvm18/lib/Target/X86/X86InstrArithmetic.td contrib/libs/llvm18/lib/Target/X86/X86InstrAsmAlias.td contrib/libs/llvm18/lib/Target/X86/X86InstrCMovSetCC.td contrib/libs/llvm18/lib/Target/X86/X86InstrCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrControl.td contrib/libs/llvm18/lib/Target/X86/X86InstrExtension.td contrib/libs/llvm18/lib/Target/X86/X86InstrFMA.td contrib/libs/llvm18/lib/Target/X86/X86InstrFPStack.td contrib/libs/llvm18/lib/Target/X86/X86InstrFormats.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragments.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragmentsSIMD.td contrib/libs/llvm18/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm18/lib/Target/X86/X86InstrKL.td contrib/libs/llvm18/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrMisc.td contrib/libs/llvm18/lib/Target/X86/X86InstrOperands.td contrib/libs/llvm18/lib/Target/X86/X86InstrPredicates.td contrib/libs/llvm18/lib/Target/X86/X86InstrRAOINT.td contrib/libs/llvm18/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm18/lib/Target/X86/X86InstrSNP.td contrib/libs/llvm18/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm18/lib/Target/X86/X86InstrSVM.td contrib/libs/llvm18/lib/Target/X86/X86InstrShiftRotate.td contrib/libs/llvm18/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm18/lib/Target/X86/X86InstrTBM.td contrib/libs/llvm18/lib/Target/X86/X86InstrTDX.td contrib/libs/llvm18/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm18/lib/Target/X86/X86InstrUtils.td contrib/libs/llvm18/lib/Target/X86/X86InstrVMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrVecCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm18/lib/Target/X86/X86PfmCounters.td contrib/libs/llvm18/lib/Target/X86/X86RegisterBanks.td contrib/libs/llvm18/lib/Target/X86/X86RegisterInfo.td contrib/libs/llvm18/lib/Target/X86/X86SchedAlderlakeP.td contrib/libs/llvm18/lib/Target/X86/X86SchedBroadwell.td contrib/libs/llvm18/lib/Target/X86/X86SchedHaswell.td contrib/libs/llvm18/lib/Target/X86/X86SchedIceLake.td contrib/libs/llvm18/lib/Target/X86/X86SchedPredicates.td contrib/libs/llvm18/lib/Target/X86/X86SchedSandyBridge.td contrib/libs/llvm18/lib/Target/X86/X86SchedSapphireRapids.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeClient.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeServer.td contrib/libs/llvm18/lib/Target/X86/X86Schedule.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleAtom.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBdVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBtVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleSLM.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver1.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver3.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver4.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenRegisterBank.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenRegisterBank.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-register-info -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/X86 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/X86/X86.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenRegisterInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenRegisterInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/X86/X86.td contrib/libs/llvm18/lib/Target/X86/X86CallingConv.td contrib/libs/llvm18/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm18/lib/Target/X86/X86InstrAMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrAVX512.td contrib/libs/llvm18/lib/Target/X86/X86InstrArithmetic.td contrib/libs/llvm18/lib/Target/X86/X86InstrAsmAlias.td contrib/libs/llvm18/lib/Target/X86/X86InstrCMovSetCC.td contrib/libs/llvm18/lib/Target/X86/X86InstrCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrControl.td contrib/libs/llvm18/lib/Target/X86/X86InstrExtension.td contrib/libs/llvm18/lib/Target/X86/X86InstrFMA.td contrib/libs/llvm18/lib/Target/X86/X86InstrFPStack.td contrib/libs/llvm18/lib/Target/X86/X86InstrFormats.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragments.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragmentsSIMD.td contrib/libs/llvm18/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm18/lib/Target/X86/X86InstrKL.td contrib/libs/llvm18/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrMisc.td contrib/libs/llvm18/lib/Target/X86/X86InstrOperands.td contrib/libs/llvm18/lib/Target/X86/X86InstrPredicates.td contrib/libs/llvm18/lib/Target/X86/X86InstrRAOINT.td contrib/libs/llvm18/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm18/lib/Target/X86/X86InstrSNP.td contrib/libs/llvm18/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm18/lib/Target/X86/X86InstrSVM.td contrib/libs/llvm18/lib/Target/X86/X86InstrShiftRotate.td contrib/libs/llvm18/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm18/lib/Target/X86/X86InstrTBM.td contrib/libs/llvm18/lib/Target/X86/X86InstrTDX.td contrib/libs/llvm18/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm18/lib/Target/X86/X86InstrUtils.td contrib/libs/llvm18/lib/Target/X86/X86InstrVMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrVecCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm18/lib/Target/X86/X86PfmCounters.td contrib/libs/llvm18/lib/Target/X86/X86RegisterBanks.td contrib/libs/llvm18/lib/Target/X86/X86RegisterInfo.td contrib/libs/llvm18/lib/Target/X86/X86SchedAlderlakeP.td contrib/libs/llvm18/lib/Target/X86/X86SchedBroadwell.td contrib/libs/llvm18/lib/Target/X86/X86SchedHaswell.td contrib/libs/llvm18/lib/Target/X86/X86SchedIceLake.td contrib/libs/llvm18/lib/Target/X86/X86SchedPredicates.td contrib/libs/llvm18/lib/Target/X86/X86SchedSandyBridge.td contrib/libs/llvm18/lib/Target/X86/X86SchedSapphireRapids.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeClient.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeServer.td contrib/libs/llvm18/lib/Target/X86/X86Schedule.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleAtom.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBdVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBtVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleSLM.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver1.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver3.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver4.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenRegisterInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenRegisterInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target/X86 -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/Target contrib/libs/llvm18/lib/Target/X86/X86.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenSubtargetInfo.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenSubtargetInfo.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/Target/X86/X86.td contrib/libs/llvm18/lib/Target/X86/X86CallingConv.td contrib/libs/llvm18/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm18/lib/Target/X86/X86InstrAMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrAVX512.td contrib/libs/llvm18/lib/Target/X86/X86InstrArithmetic.td contrib/libs/llvm18/lib/Target/X86/X86InstrAsmAlias.td contrib/libs/llvm18/lib/Target/X86/X86InstrCMovSetCC.td contrib/libs/llvm18/lib/Target/X86/X86InstrCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrControl.td contrib/libs/llvm18/lib/Target/X86/X86InstrExtension.td contrib/libs/llvm18/lib/Target/X86/X86InstrFMA.td contrib/libs/llvm18/lib/Target/X86/X86InstrFPStack.td contrib/libs/llvm18/lib/Target/X86/X86InstrFormats.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragments.td contrib/libs/llvm18/lib/Target/X86/X86InstrFragmentsSIMD.td contrib/libs/llvm18/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm18/lib/Target/X86/X86InstrKL.td contrib/libs/llvm18/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrMisc.td contrib/libs/llvm18/lib/Target/X86/X86InstrOperands.td contrib/libs/llvm18/lib/Target/X86/X86InstrPredicates.td contrib/libs/llvm18/lib/Target/X86/X86InstrRAOINT.td contrib/libs/llvm18/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm18/lib/Target/X86/X86InstrSNP.td contrib/libs/llvm18/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm18/lib/Target/X86/X86InstrSVM.td contrib/libs/llvm18/lib/Target/X86/X86InstrShiftRotate.td contrib/libs/llvm18/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm18/lib/Target/X86/X86InstrTBM.td contrib/libs/llvm18/lib/Target/X86/X86InstrTDX.td contrib/libs/llvm18/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm18/lib/Target/X86/X86InstrUtils.td contrib/libs/llvm18/lib/Target/X86/X86InstrVMX.td contrib/libs/llvm18/lib/Target/X86/X86InstrVecCompiler.td contrib/libs/llvm18/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm18/lib/Target/X86/X86PfmCounters.td contrib/libs/llvm18/lib/Target/X86/X86RegisterBanks.td contrib/libs/llvm18/lib/Target/X86/X86RegisterInfo.td contrib/libs/llvm18/lib/Target/X86/X86SchedAlderlakeP.td contrib/libs/llvm18/lib/Target/X86/X86SchedBroadwell.td contrib/libs/llvm18/lib/Target/X86/X86SchedHaswell.td contrib/libs/llvm18/lib/Target/X86/X86SchedIceLake.td contrib/libs/llvm18/lib/Target/X86/X86SchedPredicates.td contrib/libs/llvm18/lib/Target/X86/X86SchedSandyBridge.td contrib/libs/llvm18/lib/Target/X86/X86SchedSapphireRapids.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeClient.td contrib/libs/llvm18/lib/Target/X86/X86SchedSkylakeServer.td contrib/libs/llvm18/lib/Target/X86/X86Schedule.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleAtom.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBdVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleBtVer2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleSLM.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver1.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver2.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver3.td contrib/libs/llvm18/lib/Target/X86/X86ScheduleZnver4.td llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsDirectX.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsLoongArch.td llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsRISCVXCV.td llvm/IR/IntrinsicsRISCVXTHead.td llvm/IR/IntrinsicsRISCVXsf.td llvm/IR/IntrinsicsSPIRV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenSubtargetInfo.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/Target/X86/X86GenSubtargetInfo.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/ToolDrivers/llvm-dlltool -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/lib/ToolDrivers/llvm-dlltool/Options.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/ToolDrivers/llvm-dlltool/Options.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/ToolDrivers/llvm-dlltool/Options.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/ToolDrivers/llvm-dlltool/Options.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/ToolDrivers/llvm-dlltool/Options.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/ToolDrivers/llvm-dlltool/Options.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/lib/ToolDrivers/llvm-lib -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/lib/ToolDrivers/llvm-lib/Options.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/ToolDrivers/llvm-lib/Options.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/ToolDrivers/llvm-lib/Options.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/lib/ToolDrivers/llvm-lib/Options.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/ToolDrivers/llvm-lib/Options.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/lib/ToolDrivers/llvm-lib/Options.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/dsymutil -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/dsymutil/Options.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/dsymutil/Options.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/dsymutil/Options.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/dsymutil/Options.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/dsymutil/Options.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/dsymutil/Options.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-cvtres -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-cvtres/Opts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-cvtres/Opts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-cvtres/Opts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-cvtres/Opts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-cvtres/Opts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-cvtres/Opts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-cxxfilt -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-cxxfilt/Opts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-cxxfilt/Opts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-cxxfilt/Opts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-cxxfilt/Opts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-cxxfilt/Opts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-cxxfilt/Opts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-dwp -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-dwp/Opts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-dwp/Opts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-dwp/Opts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-dwp/Opts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-dwp/Opts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-dwp/Opts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-gsymutil -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-gsymutil/Opts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-gsymutil/Opts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-gsymutil/Opts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-gsymutil/Opts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-gsymutil/Opts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-gsymutil/Opts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-ifs -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-ifs/Opts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-ifs/Opts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-ifs/Opts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-ifs/Opts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-ifs/Opts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-ifs/Opts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-libtool-darwin -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-libtool-darwin/Opts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-libtool-darwin/Opts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-libtool-darwin/Opts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-libtool-darwin/Opts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-libtool-darwin/Opts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-libtool-darwin/Opts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-lipo -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-lipo/LipoOpts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-lipo/LipoOpts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-lipo/LipoOpts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-lipo/LipoOpts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-lipo/LipoOpts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-lipo/LipoOpts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-ml -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-ml/Opts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-ml/Opts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-ml/Opts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-ml/Opts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-ml/Opts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-ml/Opts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-mt -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-mt/Opts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-mt/Opts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-mt/Opts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-mt/Opts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-mt/Opts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-mt/Opts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-nm -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-nm/Opts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-nm/Opts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-nm/Opts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-nm/Opts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-nm/Opts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-nm/Opts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-objcopy/BitcodeStripOpts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy/BitcodeStripOpts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy/BitcodeStripOpts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-objcopy/BitcodeStripOpts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy/BitcodeStripOpts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy/BitcodeStripOpts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-objcopy/InstallNameToolOpts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy/InstallNameToolOpts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy/InstallNameToolOpts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-objcopy/InstallNameToolOpts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy/InstallNameToolOpts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy/InstallNameToolOpts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-objcopy/ObjcopyOpts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy/ObjcopyOpts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy/ObjcopyOpts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-objcopy/CommonOpts.td contrib/libs/llvm18/tools/llvm-objcopy/ObjcopyOpts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy/ObjcopyOpts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy/ObjcopyOpts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-objcopy/StripOpts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy/StripOpts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy/StripOpts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-objcopy/CommonOpts.td contrib/libs/llvm18/tools/llvm-objcopy/StripOpts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy/StripOpts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objcopy/StripOpts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-objdump -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-objdump/ObjdumpOpts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objdump/ObjdumpOpts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objdump/ObjdumpOpts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-objdump/ObjdumpOpts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objdump/ObjdumpOpts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objdump/ObjdumpOpts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-objdump -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-objdump/OtoolOpts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objdump/OtoolOpts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objdump/OtoolOpts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-objdump/OtoolOpts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objdump/OtoolOpts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-objdump/OtoolOpts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-rc -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-rc/Opts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-rc/Opts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-rc/Opts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-rc/Opts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-rc/Opts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-rc/Opts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-rc -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-rc/WindresOpts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-rc/WindresOpts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-rc/WindresOpts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-rc/WindresOpts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-rc/WindresOpts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-rc/WindresOpts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-readobj -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-readobj/Opts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-readobj/Opts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-readobj/Opts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-readobj/Opts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-readobj/Opts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-readobj/Opts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-size -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-size/Opts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-size/Opts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-size/Opts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-size/Opts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-size/Opts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-size/Opts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-strings -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-strings/Opts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-strings/Opts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-strings/Opts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-strings/Opts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-strings/Opts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-strings/Opts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/llvm-symbolizer -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/llvm-symbolizer/Opts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-symbolizer/Opts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-symbolizer/Opts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/llvm-symbolizer/Opts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-symbolizer/Opts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/llvm-symbolizer/Opts.inc.d ) RUN_PROGRAM( contrib/libs/llvm18/utils/TableGen -gen-opt-parser-defs -I ${ARCADIA_ROOT}/contrib/libs/llvm18/tools/sancov -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm18/include contrib/libs/llvm18/tools/sancov/Opts.td --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/sancov/Opts.inc -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/sancov/Opts.inc.d CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18 IN contrib/libs/llvm18/tools/sancov/Opts.td llvm/Option/OptParser.td OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/sancov/Opts.inc ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm18/tools/sancov/Opts.inc.d ) END()