From 2598ef1d0aee359b4b6d5fdd1758916d5907d04f Mon Sep 17 00:00:00 2001
From: shadchin <shadchin@yandex-team.ru>
Date: Thu, 10 Feb 2022 16:44:30 +0300
Subject: Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit
1 of 2.
---
.../libs/llvm12/lib/Target/X86/Disassembler/X86Disassembler.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
(limited to 'contrib/libs/llvm12/lib/Target/X86/Disassembler/X86Disassembler.cpp')
diff --git a/contrib/libs/llvm12/lib/Target/X86/Disassembler/X86Disassembler.cpp b/contrib/libs/llvm12/lib/Target/X86/Disassembler/X86Disassembler.cpp
index 4e6d8e8e1a..1d396796e7 100644
--- a/contrib/libs/llvm12/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/contrib/libs/llvm12/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -492,7 +492,7 @@ static int readPrefixes(struct InternalInstruction *insn) {
insn->addressSize = (insn->hasAdSize ? 4 : 8);
insn->displacementSize = 4;
insn->immediateSize = 4;
- insn->hasOpSize = false;
+ insn->hasOpSize = false;
} else {
insn->registerSize = (insn->hasOpSize ? 2 : 4);
insn->addressSize = (insn->hasAdSize ? 4 : 8);
@@ -1663,9 +1663,9 @@ namespace X86 {
sib = 504,
sib64 = 505
};
-} // namespace X86
+} // namespace X86
-} // namespace llvm
+} // namespace llvm
static bool translateInstruction(MCInst &target,
InternalInstruction &source,
@@ -1690,7 +1690,7 @@ private:
DisassemblerMode fMode;
};
-} // namespace
+} // namespace
X86GenericDisassembler::X86GenericDisassembler(
const MCSubtargetInfo &STI,
--
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