Restoring authorship annotation for Anton Samokhvalov <pg83@yandex.ru>. Commit 1 of 2.

1 files changed, 97 insertions, 97 deletions

diff --git a/util/system/cpu_id_ut.cpp b/util/system/cpu_id_ut.cpp
index 68f1f8aac7..150c72330d 100644
--- a/util/system/cpu_id_ut.cpp
+++ b/util/system/cpu_id_ut.cpp
@@ -1,9 +1,9 @@
-#include "cpu_id.h"
-
+#include "cpu_id.h" 
+ 
 #include "platform.h"
 
 #include <library/cpp/testing/unittest/registar.h>
-
+ 
 // There are no tests yet for instructions that use 512-bit wide registers because they are not
 // supported by some compilers yet.
 // Relevant review in LLVM https://reviews.llvm.org/D16757, we should wait untill it will be in our
@@ -46,92 +46,92 @@ static void ExecutePCOMMITInstruction();
 static void ExecuteCLFLUSHOPTInstruction();
 static void ExecuteCLWBInstruction();
 
-static void ExecuteFMAInstruction() {
-}
-
-static void ExecuteRDTSCPInstruction() {
-}
-
-static void ExecuteXSAVEInstruction() {
-}
-
-static void ExecuteOSXSAVEInstruction() {
-}
-
+static void ExecuteFMAInstruction() { 
+} 
+ 
+static void ExecuteRDTSCPInstruction() { 
+} 
+ 
+static void ExecuteXSAVEInstruction() { 
+} 
+ 
+static void ExecuteOSXSAVEInstruction() { 
+} 
+ 
 Y_UNIT_TEST_SUITE(TestCpuId) {
 #define DECLARE_TEST_HAVE_INSTRUCTION(name) \
-    Y_UNIT_TEST(Test##Have##name) {         \
+    Y_UNIT_TEST(Test##Have##name) {         \ 
         if (NX86::Have##name()) {           \
             Execute##name##Instruction();   \
         }                                   \
-    }
-
-    Y_CPU_ID_ENUMERATE(DECLARE_TEST_HAVE_INSTRUCTION)
+    } 
+ 
+    Y_CPU_ID_ENUMERATE(DECLARE_TEST_HAVE_INSTRUCTION) 
 #undef DECLARE_TEST_HAVE_INSTRUCTION
 
     Y_UNIT_TEST(TestSSE2) {
-#if defined(_x86_64_)
-        UNIT_ASSERT(NX86::HaveSSE2());
-#endif
-    }
-
+#if defined(_x86_64_) 
+        UNIT_ASSERT(NX86::HaveSSE2()); 
+#endif 
+    } 
+ 
     Y_UNIT_TEST(TestCpuBrand) {
-        ui32 store[12];
-
-        //Cout << CpuBrand(store) << Endl;;
-
-        UNIT_ASSERT(strlen(CpuBrand(store)) > 0);
-    }
+        ui32 store[12]; 
+ 
+        //Cout << CpuBrand(store) << Endl;; 
+ 
+        UNIT_ASSERT(strlen(CpuBrand(store)) > 0); 
+    } 
 
     Y_UNIT_TEST(TestCachedAndNoncached) {
-#define Y_DEF_NAME(X) UNIT_ASSERT_VALUES_EQUAL(NX86::Have##X(), NX86::CachedHave##X());
-        Y_CPU_ID_ENUMERATE(Y_DEF_NAME)
-#undef Y_DEF_NAME
+#define Y_DEF_NAME(X) UNIT_ASSERT_VALUES_EQUAL(NX86::Have##X(), NX86::CachedHave##X()); 
+        Y_CPU_ID_ENUMERATE(Y_DEF_NAME) 
+#undef Y_DEF_NAME 
     }
-}
+} 
 
 #if defined(_x86_64_)
-    #if defined(__GNUC__)
+    #if defined(__GNUC__) 
 void ExecuteSSEInstruction() {
-    __asm__ __volatile__("xorps %%xmm0, %%xmm0\n"
-                         :
-                         :
-                         : "xmm0");
+    __asm__ __volatile__("xorps %%xmm0, %%xmm0\n" 
+                         : 
+                         : 
+                         : "xmm0"); 
 }
 
 void ExecuteSSE2Instruction() {
-    __asm__ __volatile__("psrldq $0, %%xmm0\n"
-                         :
-                         :
-                         : "xmm0");
+    __asm__ __volatile__("psrldq $0, %%xmm0\n" 
+                         : 
+                         : 
+                         : "xmm0"); 
 }
 
 void ExecuteSSE3Instruction() {
-    __asm__ __volatile__("addsubpd %%xmm0, %%xmm0\n"
-                         :
-                         :
-                         : "xmm0");
+    __asm__ __volatile__("addsubpd %%xmm0, %%xmm0\n" 
+                         : 
+                         : 
+                         : "xmm0"); 
 }
 
 void ExecuteSSSE3Instruction() {
-    __asm__ __volatile__("psignb %%xmm0, %%xmm0\n"
-                         :
-                         :
-                         : "xmm0");
+    __asm__ __volatile__("psignb %%xmm0, %%xmm0\n" 
+                         : 
+                         : 
+                         : "xmm0"); 
 }
 
 void ExecuteSSE41Instruction() {
-    __asm__ __volatile__("pmuldq %%xmm0, %%xmm0\n"
-                         :
-                         :
-                         : "xmm0");
+    __asm__ __volatile__("pmuldq %%xmm0, %%xmm0\n" 
+                         : 
+                         : 
+                         : "xmm0"); 
 }
 
 void ExecuteSSE42Instruction() {
-    __asm__ __volatile__("crc32 %%eax, %%eax\n"
-                         :
-                         :
-                         : "eax");
+    __asm__ __volatile__("crc32 %%eax, %%eax\n" 
+                         : 
+                         : 
+                         : "eax"); 
 }
 
 void ExecuteF16CInstruction() {
@@ -142,30 +142,30 @@ void ExecuteF16CInstruction() {
 }
 
 void ExecuteAVXInstruction() {
-    __asm__ __volatile__("vzeroupper\n"
-                         :
-                         :
-                         : "xmm0");
+    __asm__ __volatile__("vzeroupper\n" 
+                         : 
+                         : 
+                         : "xmm0"); 
 }
 
 void ExecuteAVX2Instruction() {
-    __asm__ __volatile__("vpunpcklbw %%ymm0, %%ymm0, %%ymm0\n"
-                         :
-                         :
-                         : "xmm0");
+    __asm__ __volatile__("vpunpcklbw %%ymm0, %%ymm0, %%ymm0\n" 
+                         : 
+                         : 
+                         : "xmm0"); 
 }
 
 void ExecutePOPCNTInstruction() {
-    __asm__ __volatile__("popcnt %%eax, %%eax\n"
-                         :
-                         :
-                         : "eax");
+    __asm__ __volatile__("popcnt %%eax, %%eax\n" 
+                         : 
+                         : 
+                         : "eax"); 
 }
 
 void ExecuteBMI1Instruction() {
     __asm__ __volatile__("tzcnt %%eax, %%eax\n"
-                         :
-                         :
+                         : 
+                         : 
                          : "eax");
 }
 
@@ -184,10 +184,10 @@ void ExecutePCLMULInstruction() {
 }
 
 void ExecuteAESInstruction() {
-    __asm__ __volatile__("aesimc %%xmm0, %%xmm0\n"
-                         :
-                         :
-                         : "xmm0");
+    __asm__ __volatile__("aesimc %%xmm0, %%xmm0\n" 
+                         : 
+                         : 
+                         : "xmm0"); 
 }
 
 void ExecuteAVX512FInstruction() {
@@ -221,31 +221,31 @@ void ExecutePREFETCHWT1Instruction() {
 }
 
 void ExecuteSHAInstruction() {
-    __asm__ __volatile__("sha1msg1 %%xmm0, %%xmm0\n"
-                         :
-                         :
-                         : "xmm0");
+    __asm__ __volatile__("sha1msg1 %%xmm0, %%xmm0\n" 
+                         : 
+                         : 
+                         : "xmm0"); 
 }
 
 void ExecuteADXInstruction() {
-    __asm__ __volatile__("adcx %%eax, %%eax\n"
-                         :
-                         :
-                         : "eax");
+    __asm__ __volatile__("adcx %%eax, %%eax\n" 
+                         : 
+                         : 
+                         : "eax"); 
 }
 
 void ExecuteRDRANDInstruction() {
-    __asm__ __volatile__("rdrand %%eax"
-                         :
-                         :
-                         : "eax");
+    __asm__ __volatile__("rdrand %%eax" 
+                         : 
+                         : 
+                         : "eax"); 
 }
 
 void ExecuteRDSEEDInstruction() {
-    __asm__ __volatile__("rdseed %%eax"
-                         :
-                         :
-                         : "eax");
+    __asm__ __volatile__("rdseed %%eax" 
+                         : 
+                         : 
+                         : "eax"); 
 }
 
 void ExecutePCOMMITInstruction() {
@@ -257,7 +257,7 @@ void ExecuteCLFLUSHOPTInstruction() {
 void ExecuteCLWBInstruction() {
 }
 
-    #elif defined(_MSC_VER)
+    #elif defined(_MSC_VER) 
 void ExecuteSSEInstruction() {
 }
 
@@ -351,9 +351,9 @@ void ExecuteCLFLUSHOPTInstruction() {
 void ExecuteCLWBInstruction() {
 }
 
-    #else
-        #error "unknown compiler"
-    #endif
+    #else 
+        #error "unknown compiler" 
+    #endif 
 #else
 void ExecuteSSEInstruction() {
 }