Restoring authorship annotation for <yazevnul@yandex-team.ru>. Commit 2 of 2.

1 files changed, 111 insertions, 111 deletions

diff --git a/util/system/cpu_id.cpp b/util/system/cpu_id.cpp
index 37f923932a..598c71f4d9 100644
--- a/util/system/cpu_id.cpp
+++ b/util/system/cpu_id.cpp
@@ -4,53 +4,53 @@
 
 #include <util/generic/singleton.h>
 
-#if defined(_win_) 
+#if defined(_win_)
     #include <intrin.h>
     #include <immintrin.h>
-#elif defined(_x86_) 
+#elif defined(_x86_)
     #include <cpuid.h>
 #endif
 
 #include <string.h>
 
-#if defined(_x86_) && !defined(_win_) 
-static ui64 _xgetbv(ui32 xcr) { 
-    ui32 eax; 
-    ui32 edx; 
+#if defined(_x86_) && !defined(_win_)
+static ui64 _xgetbv(ui32 xcr) {
+    ui32 eax;
+    ui32 edx;
     __asm__ volatile(
         "xgetbv"
         : "=a"(eax), "=d"(edx)
         : "c"(xcr));
-    return (static_cast<ui64>(edx) << 32) | eax; 
-} 
-#endif 
- 
-bool NX86::CpuId(ui32 op, ui32 subOp, ui32* res) noexcept { 
-#if defined(_x86_) 
+    return (static_cast<ui64>(edx) << 32) | eax;
+}
+#endif
+
+bool NX86::CpuId(ui32 op, ui32 subOp, ui32* res) noexcept {
+#if defined(_x86_)
     #if defined(_MSC_VER)
-    static_assert(sizeof(int) == sizeof(ui32), "ups, something wrong here"); 
-    __cpuidex((int*)res, op, subOp); 
+    static_assert(sizeof(int) == sizeof(ui32), "ups, something wrong here");
+    __cpuidex((int*)res, op, subOp);
     #else
-    __cpuid_count(op, subOp, res[0], res[1], res[2], res[3]); 
+    __cpuid_count(op, subOp, res[0], res[1], res[2], res[3]);
     #endif
-    return true; 
-#else 
-    (void)op; 
-    (void)subOp; 
- 
-    memset(res, 0, 4 * sizeof(ui32)); 
- 
-    return false; 
-#endif 
-} 
- 
-bool NX86::CpuId(ui32 op, ui32* res) noexcept { 
+    return true;
+#else
+    (void)op;
+    (void)subOp;
+
+    memset(res, 0, 4 * sizeof(ui32));
+
+    return false;
+#endif
+}
+
+bool NX86::CpuId(ui32 op, ui32* res) noexcept {
 #if defined(_x86_)
     #if defined(_MSC_VER)
     static_assert(sizeof(int) == sizeof(ui32), "ups, something wrong here");
     __cpuid((int*)res, op);
     #else
-    __cpuid(op, res[0], res[1], res[2], res[3]); 
+    __cpuid(op, res[0], res[1], res[2], res[3]);
     #endif
     return true;
 #else
@@ -73,13 +73,13 @@ namespace {
             ui32 EDX;
         };
 
-        inline TX86CpuInfo(ui32 op) noexcept { 
+        inline TX86CpuInfo(ui32 op) noexcept {
             NX86::CpuId(op, Info);
         }
- 
-        inline TX86CpuInfo(ui32 op, ui32 subOp) noexcept { 
-            NX86::CpuId(op, subOp, Info); 
-        } 
+
+        inline TX86CpuInfo(ui32 op, ui32 subOp) noexcept {
+            NX86::CpuId(op, subOp, Info);
+        }
     };
 
     static_assert(sizeof(TX86CpuInfo) == 16, "please, fix me");
@@ -90,15 +90,15 @@ bool NX86::HaveRDTSCP() noexcept {
     return (TX86CpuInfo(0x80000001).EDX >> 27) & 1u;
 }
 
-bool NX86::HaveSSE() noexcept { 
+bool NX86::HaveSSE() noexcept {
     return (TX86CpuInfo(0x1).EDX >> 25) & 1u;
 }
 
-bool NX86::HaveSSE2() noexcept { 
+bool NX86::HaveSSE2() noexcept {
     return (TX86CpuInfo(0x1).EDX >> 26) & 1u;
 }
 
-bool NX86::HaveSSE3() noexcept { 
+bool NX86::HaveSSE3() noexcept {
     return TX86CpuInfo(0x1).ECX & 1u;
 }
 
@@ -106,15 +106,15 @@ bool NX86::HavePCLMUL() noexcept {
     return (TX86CpuInfo(0x1).ECX >> 1) & 1u;
 }
 
-bool NX86::HaveSSSE3() noexcept { 
+bool NX86::HaveSSSE3() noexcept {
     return (TX86CpuInfo(0x1).ECX >> 9) & 1u;
 }
 
-bool NX86::HaveSSE41() noexcept { 
+bool NX86::HaveSSE41() noexcept {
     return (TX86CpuInfo(0x1).ECX >> 19) & 1u;
 }
 
-bool NX86::HaveSSE42() noexcept { 
+bool NX86::HaveSSE42() noexcept {
     return (TX86CpuInfo(0x1).ECX >> 20) & 1u;
 }
 
@@ -122,51 +122,51 @@ bool NX86::HaveF16C() noexcept {
     return (TX86CpuInfo(0x1).ECX >> 29) & 1u;
 }
 
-bool NX86::HavePOPCNT() noexcept { 
+bool NX86::HavePOPCNT() noexcept {
     return (TX86CpuInfo(0x1).ECX >> 23) & 1u;
 }
 
-bool NX86::HaveAES() noexcept { 
+bool NX86::HaveAES() noexcept {
     return (TX86CpuInfo(0x1).ECX >> 25) & 1u;
 }
 
-bool NX86::HaveXSAVE() noexcept { 
-    return (TX86CpuInfo(0x1).ECX >> 26) & 1u; 
-} 
- 
-bool NX86::HaveOSXSAVE() noexcept { 
-    return (TX86CpuInfo(0x1).ECX >> 27) & 1u; 
-} 
- 
-bool NX86::HaveAVX() noexcept { 
+bool NX86::HaveXSAVE() noexcept {
+    return (TX86CpuInfo(0x1).ECX >> 26) & 1u;
+}
+
+bool NX86::HaveOSXSAVE() noexcept {
+    return (TX86CpuInfo(0x1).ECX >> 27) & 1u;
+}
+
+bool NX86::HaveAVX() noexcept {
 #if defined(_x86_)
     // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
-    // https://bugs.chromium.org/p/chromium/issues/detail?id=375968 
+    // https://bugs.chromium.org/p/chromium/issues/detail?id=375968
     return HaveOSXSAVE()                           // implies HaveXSAVE()
            && (_xgetbv(0) & 6u) == 6u              // XMM state and YMM state are enabled by OS
            && ((TX86CpuInfo(0x1).ECX >> 28) & 1u); // AVX bit
-#else 
+#else
     return false;
-#endif 
+#endif
 }
 
-bool NX86::HaveFMA() noexcept { 
+bool NX86::HaveFMA() noexcept {
     return HaveAVX() && ((TX86CpuInfo(0x1).ECX >> 12) & 1u);
 }
 
-bool NX86::HaveAVX2() noexcept { 
+bool NX86::HaveAVX2() noexcept {
     return HaveAVX() && ((TX86CpuInfo(0x7, 0).EBX >> 5) & 1u);
-} 
- 
-bool NX86::HaveBMI1() noexcept { 
-    return (TX86CpuInfo(0x7, 0).EBX >> 3) & 1u; 
-} 
- 
+}
+
+bool NX86::HaveBMI1() noexcept {
+    return (TX86CpuInfo(0x7, 0).EBX >> 3) & 1u;
+}
+
 bool NX86::HaveBMI2() noexcept {
     return (TX86CpuInfo(0x7, 0).EBX >> 8) & 1u;
 }
 
-bool NX86::HaveAVX512F() noexcept { 
+bool NX86::HaveAVX512F() noexcept {
 #if defined(_x86_)
     // https://software.intel.com/en-us/articles/how-to-detect-knl-instruction-support
     return HaveOSXSAVE()                           // implies HaveXSAVE()
@@ -177,73 +177,73 @@ bool NX86::HaveAVX512F() noexcept {
 #else
     return false;
 #endif
-} 
- 
-bool NX86::HaveAVX512DQ() noexcept { 
+}
+
+bool NX86::HaveAVX512DQ() noexcept {
     return HaveAVX512F() && ((TX86CpuInfo(0x7, 0).EBX >> 17) & 1u);
-} 
- 
-bool NX86::HaveRDSEED() noexcept { 
+}
+
+bool NX86::HaveRDSEED() noexcept {
     return TX86CpuInfo(0x0).EAX >= 0x7 && ((TX86CpuInfo(0x7, 0).EBX >> 18) & 1u);
-} 
- 
-bool NX86::HaveADX() noexcept { 
+}
+
+bool NX86::HaveADX() noexcept {
     return TX86CpuInfo(0x0).EAX >= 0x7 && ((TX86CpuInfo(0x7, 0).EBX >> 19) & 1u);
-} 
- 
-bool NX86::HaveAVX512IFMA() noexcept { 
+}
+
+bool NX86::HaveAVX512IFMA() noexcept {
     return HaveAVX512F() && ((TX86CpuInfo(0x7, 0).EBX >> 21) & 1u);
-} 
- 
-bool NX86::HavePCOMMIT() noexcept { 
+}
+
+bool NX86::HavePCOMMIT() noexcept {
     return TX86CpuInfo(0x0).EAX >= 0x7 && ((TX86CpuInfo(0x7, 0).EBX >> 22) & 1u);
-} 
- 
-bool NX86::HaveCLFLUSHOPT() noexcept { 
+}
+
+bool NX86::HaveCLFLUSHOPT() noexcept {
     return TX86CpuInfo(0x0).EAX >= 0x7 && ((TX86CpuInfo(0x7, 0).EBX >> 23) & 1u);
-} 
- 
-bool NX86::HaveCLWB() noexcept { 
+}
+
+bool NX86::HaveCLWB() noexcept {
     return TX86CpuInfo(0x0).EAX >= 0x7 && ((TX86CpuInfo(0x7, 0).EBX >> 24) & 1u);
-} 
- 
-bool NX86::HaveAVX512PF() noexcept { 
+}
+
+bool NX86::HaveAVX512PF() noexcept {
     return HaveAVX512F() && ((TX86CpuInfo(0x7, 0).EBX >> 26) & 1u);
-} 
- 
-bool NX86::HaveAVX512ER() noexcept { 
+}
+
+bool NX86::HaveAVX512ER() noexcept {
     return HaveAVX512F() && ((TX86CpuInfo(0x7, 0).EBX >> 27) & 1u);
-} 
- 
-bool NX86::HaveAVX512CD() noexcept { 
+}
+
+bool NX86::HaveAVX512CD() noexcept {
     return HaveAVX512F() && ((TX86CpuInfo(0x7, 0).EBX >> 28) & 1u);
-} 
- 
-bool NX86::HaveSHA() noexcept { 
+}
+
+bool NX86::HaveSHA() noexcept {
     return TX86CpuInfo(0x0).EAX >= 0x7 && ((TX86CpuInfo(0x7, 0).EBX >> 29) & 1u);
-} 
- 
-bool NX86::HaveAVX512BW() noexcept { 
+}
+
+bool NX86::HaveAVX512BW() noexcept {
     return HaveAVX512F() && ((TX86CpuInfo(0x7, 0).EBX >> 30) & 1u);
-} 
- 
-bool NX86::HaveAVX512VL() noexcept { 
+}
+
+bool NX86::HaveAVX512VL() noexcept {
     return HaveAVX512F() && ((TX86CpuInfo(0x7, 0).EBX >> 31) & 1u);
-} 
- 
-bool NX86::HavePREFETCHWT1() noexcept { 
+}
+
+bool NX86::HavePREFETCHWT1() noexcept {
     return TX86CpuInfo(0x0).EAX >= 0x7 && ((TX86CpuInfo(0x7, 0).ECX >> 0) & 1u);
-} 
- 
-bool NX86::HaveAVX512VBMI() noexcept { 
+}
+
+bool NX86::HaveAVX512VBMI() noexcept {
     return HaveAVX512F() && ((TX86CpuInfo(0x7, 0).ECX >> 1) & 1u);
-} 
- 
-bool NX86::HaveRDRAND() noexcept { 
+}
+
+bool NX86::HaveRDRAND() noexcept {
     return TX86CpuInfo(0x0).EAX >= 0x7 && ((TX86CpuInfo(0x1).ECX >> 30) & 1u);
 }
 
-const char* CpuBrand(ui32* store) noexcept { 
+const char* CpuBrand(ui32* store) noexcept {
     memset(store, 0, 12 * sizeof(*store));
 
 #if defined(_x86_)