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| author | shadchin <shadchin@yandex-team.ru> | 2022-02-10 16:44:39 +0300 |
|---|---|---|
| committer | Daniil Cherednik <dcherednik@yandex-team.ru> | 2022-02-10 16:44:39 +0300 |
| commit | e9656aae26e0358d5378e5b63dcac5c8dbe0e4d0 (patch) | |
| tree | 64175d5cadab313b3e7039ebaa06c5bc3295e274 /contrib/libs/llvm12/utils/TableGen/CodeGenRegisters.cpp | |
| parent | 2598ef1d0aee359b4b6d5fdd1758916d5907d04f (diff) | |
| download | ydb-e9656aae26e0358d5378e5b63dcac5c8dbe0e4d0.tar.gz | |
Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 2 of 2.
Diffstat (limited to 'contrib/libs/llvm12/utils/TableGen/CodeGenRegisters.cpp')
| -rw-r--r-- | contrib/libs/llvm12/utils/TableGen/CodeGenRegisters.cpp | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/contrib/libs/llvm12/utils/TableGen/CodeGenRegisters.cpp b/contrib/libs/llvm12/utils/TableGen/CodeGenRegisters.cpp index 48e91b05cd..f9a7ba6bba 100644 --- a/contrib/libs/llvm12/utils/TableGen/CodeGenRegisters.cpp +++ b/contrib/libs/llvm12/utils/TableGen/CodeGenRegisters.cpp @@ -196,7 +196,7 @@ void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) { } } -StringRef CodeGenRegister::getName() const { +StringRef CodeGenRegister::getName() const { assert(TheDef && "no def"); return TheDef->getName(); } @@ -496,10 +496,10 @@ void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) { assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct"); for (CodeGenRegister *SubReg : Cand->ExplicitSubRegs) { if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) { - if (SubRegIdx->ConcatenationOf.empty()) + if (SubRegIdx->ConcatenationOf.empty()) Parts.push_back(SubRegIdx); - else - append_range(Parts, SubRegIdx->ConcatenationOf); + else + append_range(Parts, SubRegIdx->ConcatenationOf); } else { // Sub-register doesn't exist. Parts.clear(); @@ -742,8 +742,8 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1) { GeneratePressureSet = R->getValueAsBit("GeneratePressureSet"); std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes"); - if (TypeList.empty()) - PrintFatalError(R->getLoc(), "RegTypes list must not be empty!"); + if (TypeList.empty()) + PrintFatalError(R->getLoc(), "RegTypes list must not be empty!"); for (unsigned i = 0, e = TypeList.size(); i != e; ++i) { Record *Type = TypeList[i]; if (!Type->isSubClassOf("ValueType")) @@ -998,8 +998,8 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs( const CodeGenRegisterClass *B) { // If there are multiple, identical register classes, prefer the original // register class. - if (A == B) - return false; + if (A == B) + return false; if (A->getMembers().size() == B->getMembers().size()) return A == this; return A->getMembers().size() > B->getMembers().size(); @@ -1237,7 +1237,7 @@ CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) { const CodeGenSubRegIndex * CodeGenRegBank::findSubRegIdx(const Record* Def) const { - return Def2SubRegIdx.lookup(Def); + return Def2SubRegIdx.lookup(Def); } CodeGenRegister *CodeGenRegBank::getReg(Record *Def) { @@ -2009,7 +2009,7 @@ void CodeGenRegBank::computeRegUnitSets() { if (RCRegUnits.empty()) continue; - LLVM_DEBUG(dbgs() << "RC " << RC.getName() << " Units:\n"; + LLVM_DEBUG(dbgs() << "RC " << RC.getName() << " Units:\n"; for (auto U : RCRegUnits) printRegUnitName(U); dbgs() << "\n UnitSetIDs:"); |