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author | shadchin <shadchin@yandex-team.ru> | 2022-02-10 16:44:30 +0300 |
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committer | Daniil Cherednik <dcherednik@yandex-team.ru> | 2022-02-10 16:44:30 +0300 |
commit | 2598ef1d0aee359b4b6d5fdd1758916d5907d04f (patch) | |
tree | 012bb94d777798f1f56ac1cec429509766d05181 /contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td | |
parent | 6751af0b0c1b952fede40b19b71da8025b5d8bcf (diff) | |
download | ydb-2598ef1d0aee359b4b6d5fdd1758916d5907d04f.tar.gz |
Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 1 of 2.
Diffstat (limited to 'contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td')
-rw-r--r-- | contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td | 94 |
1 files changed, 47 insertions, 47 deletions
diff --git a/contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td b/contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td index de59f3fe27..be95d70282 100644 --- a/contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td +++ b/contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td @@ -1,47 +1,47 @@ -//===-- X86InstrSNP.td - SNP Instruction Set Extension -----*- tablegen -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file describes the instructions that make up the AMD Secure Nested -// Paging (SNP) instruction set. -// -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// SNP instructions - -let SchedRW = [WriteSystem] in { -// F3 0F 01 FF -let Uses = [RAX] in -def PSMASH: I<0x01, MRM_FF, (outs), (ins), "psmash", []>, XS, - Requires<[In64BitMode]>; - -// F2 0F 01 FF -let Uses = [RAX] in -def PVALIDATE64: I<0x01, MRM_FF, (outs), (ins), "pvalidate",[]>, - XD, Requires<[In64BitMode]>; - -let Uses = [EAX] in -def PVALIDATE32: I<0x01, MRM_FF, (outs), (ins), "pvalidate",[]>, - XD, Requires<[Not64BitMode]>; - -// F2 0F 01 FE -let Uses = [RAX] in -def RMPUPDATE: I<0x01, MRM_FE, (outs), (ins), "rmpupdate", []>, XD, - Requires<[In64BitMode]>; - -// F3 0F 01 FE -let Uses = [RAX] in -def RMPADJUST: I<0x01, MRM_FE, (outs), (ins), "rmpadjust", []>, XS, - Requires<[In64BitMode]>; -} // SchedRW - -def : InstAlias<"psmash\t{%rax|rax}", (PSMASH)>, Requires<[In64BitMode]>; -def : InstAlias<"pvalidate\t{%rax|rax}", (PVALIDATE64)>, Requires<[In64BitMode]>; -def : InstAlias<"pvalidate\t{%eax|eax}", (PVALIDATE32)>, Requires<[Not64BitMode]>; -def : InstAlias<"rmpupdate\t{%rax|rax}", (RMPUPDATE)>, Requires<[In64BitMode]>; -def : InstAlias<"rmpadjust\t{%rax|rax}", (RMPADJUST)>, Requires<[In64BitMode]>; +//===-- X86InstrSNP.td - SNP Instruction Set Extension -----*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the instructions that make up the AMD Secure Nested +// Paging (SNP) instruction set. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// SNP instructions + +let SchedRW = [WriteSystem] in { +// F3 0F 01 FF +let Uses = [RAX] in +def PSMASH: I<0x01, MRM_FF, (outs), (ins), "psmash", []>, XS, + Requires<[In64BitMode]>; + +// F2 0F 01 FF +let Uses = [RAX] in +def PVALIDATE64: I<0x01, MRM_FF, (outs), (ins), "pvalidate",[]>, + XD, Requires<[In64BitMode]>; + +let Uses = [EAX] in +def PVALIDATE32: I<0x01, MRM_FF, (outs), (ins), "pvalidate",[]>, + XD, Requires<[Not64BitMode]>; + +// F2 0F 01 FE +let Uses = [RAX] in +def RMPUPDATE: I<0x01, MRM_FE, (outs), (ins), "rmpupdate", []>, XD, + Requires<[In64BitMode]>; + +// F3 0F 01 FE +let Uses = [RAX] in +def RMPADJUST: I<0x01, MRM_FE, (outs), (ins), "rmpadjust", []>, XS, + Requires<[In64BitMode]>; +} // SchedRW + +def : InstAlias<"psmash\t{%rax|rax}", (PSMASH)>, Requires<[In64BitMode]>; +def : InstAlias<"pvalidate\t{%rax|rax}", (PVALIDATE64)>, Requires<[In64BitMode]>; +def : InstAlias<"pvalidate\t{%eax|eax}", (PVALIDATE32)>, Requires<[Not64BitMode]>; +def : InstAlias<"rmpupdate\t{%rax|rax}", (RMPUPDATE)>, Requires<[In64BitMode]>; +def : InstAlias<"rmpadjust\t{%rax|rax}", (RMPADJUST)>, Requires<[In64BitMode]>; |