Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 1 of 2.

1 files changed, 26 insertions, 26 deletions

diff --git a/contrib/libs/llvm12/lib/Target/X86/X86EvexToVex.cpp b/contrib/libs/llvm12/lib/Target/X86/X86EvexToVex.cpp
index 97f843fa24..1ac8851ecd 100644
--- a/contrib/libs/llvm12/lib/Target/X86/X86EvexToVex.cpp
+++ b/contrib/libs/llvm12/lib/Target/X86/X86EvexToVex.cpp
@@ -85,8 +85,8 @@ public:
 private:
   /// Machine instruction info used throughout the class.
   const X86InstrInfo *TII = nullptr;
-
-  const X86Subtarget *ST = nullptr;
+ 
+  const X86Subtarget *ST = nullptr; 
 };
 
 } // end anonymous namespace
@@ -96,8 +96,8 @@ char EvexToVexInstPass::ID = 0;
 bool EvexToVexInstPass::runOnMachineFunction(MachineFunction &MF) {
   TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
 
-  ST = &MF.getSubtarget<X86Subtarget>();
-  if (!ST->hasAVX512())
+  ST = &MF.getSubtarget<X86Subtarget>(); 
+  if (!ST->hasAVX512()) 
     return false;
 
   bool Changed = false;
@@ -146,29 +146,29 @@ static bool usesExtendedRegister(const MachineInstr &MI) {
 }
 
 // Do any custom cleanup needed to finalize the conversion.
-static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc,
-                                     const X86Subtarget *ST) {
+static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc, 
+                                     const X86Subtarget *ST) { 
   (void)NewOpc;
   unsigned Opc = MI.getOpcode();
   switch (Opc) {
-  case X86::VPDPBUSDSZ256m:
-  case X86::VPDPBUSDSZ256r:
-  case X86::VPDPBUSDSZ128m:
-  case X86::VPDPBUSDSZ128r:
-  case X86::VPDPBUSDZ256m:
-  case X86::VPDPBUSDZ256r:
-  case X86::VPDPBUSDZ128m:
-  case X86::VPDPBUSDZ128r:
-  case X86::VPDPWSSDSZ256m:
-  case X86::VPDPWSSDSZ256r:
-  case X86::VPDPWSSDSZ128m:
-  case X86::VPDPWSSDSZ128r:
-  case X86::VPDPWSSDZ256m:
-  case X86::VPDPWSSDZ256r:
-  case X86::VPDPWSSDZ128m:
-  case X86::VPDPWSSDZ128r:
-    // These can only VEX convert if AVXVNNI is enabled.
-    return ST->hasAVXVNNI();
+  case X86::VPDPBUSDSZ256m: 
+  case X86::VPDPBUSDSZ256r: 
+  case X86::VPDPBUSDSZ128m: 
+  case X86::VPDPBUSDSZ128r: 
+  case X86::VPDPBUSDZ256m: 
+  case X86::VPDPBUSDZ256r: 
+  case X86::VPDPBUSDZ128m: 
+  case X86::VPDPBUSDZ128r: 
+  case X86::VPDPWSSDSZ256m: 
+  case X86::VPDPWSSDSZ256r: 
+  case X86::VPDPWSSDSZ128m: 
+  case X86::VPDPWSSDSZ128r: 
+  case X86::VPDPWSSDZ256m: 
+  case X86::VPDPWSSDZ256r: 
+  case X86::VPDPWSSDZ128m: 
+  case X86::VPDPWSSDZ128r: 
+    // These can only VEX convert if AVXVNNI is enabled. 
+    return ST->hasAVXVNNI(); 
   case X86::VALIGNDZ128rri:
   case X86::VALIGNDZ128rmi:
   case X86::VALIGNQZ128rri:
@@ -271,7 +271,7 @@ bool EvexToVexInstPass::CompressEvexToVexImpl(MachineInstr &MI) const {
     (Desc.TSFlags & X86II::VEX_L) ? makeArrayRef(X86EvexToVex256CompressTable)
                                   : makeArrayRef(X86EvexToVex128CompressTable);
 
-  const auto *I = llvm::lower_bound(Table, MI.getOpcode());
+  const auto *I = llvm::lower_bound(Table, MI.getOpcode()); 
   if (I == Table.end() || I->EvexOpcode != MI.getOpcode())
     return false;
 
@@ -280,7 +280,7 @@ bool EvexToVexInstPass::CompressEvexToVexImpl(MachineInstr &MI) const {
   if (usesExtendedRegister(MI))
     return false;
 
-  if (!performCustomAdjustments(MI, NewOpc, ST))
+  if (!performCustomAdjustments(MI, NewOpc, ST)) 
     return false;
 
   MI.setDesc(TII->get(NewOpc));