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author | shadchin <shadchin@yandex-team.ru> | 2022-02-10 16:44:30 +0300 |
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committer | Daniil Cherednik <dcherednik@yandex-team.ru> | 2022-02-10 16:44:30 +0300 |
commit | 2598ef1d0aee359b4b6d5fdd1758916d5907d04f (patch) | |
tree | 012bb94d777798f1f56ac1cec429509766d05181 /contrib/libs/llvm12/lib/Target/X86/X86.td | |
parent | 6751af0b0c1b952fede40b19b71da8025b5d8bcf (diff) | |
download | ydb-2598ef1d0aee359b4b6d5fdd1758916d5907d04f.tar.gz |
Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 1 of 2.
Diffstat (limited to 'contrib/libs/llvm12/lib/Target/X86/X86.td')
-rw-r--r-- | contrib/libs/llvm12/lib/Target/X86/X86.td | 988 |
1 files changed, 494 insertions, 494 deletions
diff --git a/contrib/libs/llvm12/lib/Target/X86/X86.td b/contrib/libs/llvm12/lib/Target/X86/X86.td index c492d686c5..d17c7f4f9b 100644 --- a/contrib/libs/llvm12/lib/Target/X86/X86.td +++ b/contrib/libs/llvm12/lib/Target/X86/X86.td @@ -171,9 +171,9 @@ def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true", def FeatureVNNI : SubtargetFeature<"avx512vnni", "HasVNNI", "true", "Enable AVX-512 Vector Neural Network Instructions", [FeatureAVX512]>; -def FeatureAVXVNNI : SubtargetFeature<"avxvnni", "HasAVXVNNI", "true", - "Support AVX_VNNI encoding", - [FeatureAVX2]>; +def FeatureAVXVNNI : SubtargetFeature<"avxvnni", "HasAVXVNNI", "true", + "Support AVX_VNNI encoding", + [FeatureAVX2]>; def FeatureBF16 : SubtargetFeature<"avx512bf16", "HasBF16", "true", "Support bfloat16 floating point", [FeatureBWI]>; @@ -237,8 +237,8 @@ def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true", "Support PRFCHW instructions">; def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true", "Support RDSEED instruction">; -def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF64", "true", - "Support LAHF and SAHF instructions in 64-bit mode">; +def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF64", "true", + "Support LAHF and SAHF instructions in 64-bit mode">; def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true", "Enable MONITORX/MWAITX timer functionality">; def FeatureCLZERO : SubtargetFeature<"clzero", "HasCLZERO", "true", @@ -282,20 +282,20 @@ def FeatureWAITPKG : SubtargetFeature<"waitpkg", "HasWAITPKG", "true", "Wait and pause enhancements">; def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true", "Has ENQCMD instructions">; -def FeatureKL : SubtargetFeature<"kl", "HasKL", "true", - "Support Key Locker kl Instructions", - [FeatureSSE2]>; -def FeatureWIDEKL : SubtargetFeature<"widekl", "HasWIDEKL", "true", - "Support Key Locker wide Instructions", - [FeatureKL]>; -def FeatureHRESET : SubtargetFeature<"hreset", "HasHRESET", "true", - "Has hreset instruction">; +def FeatureKL : SubtargetFeature<"kl", "HasKL", "true", + "Support Key Locker kl Instructions", + [FeatureSSE2]>; +def FeatureWIDEKL : SubtargetFeature<"widekl", "HasWIDEKL", "true", + "Support Key Locker wide Instructions", + [FeatureKL]>; +def FeatureHRESET : SubtargetFeature<"hreset", "HasHRESET", "true", + "Has hreset instruction">; def FeatureSERIALIZE : SubtargetFeature<"serialize", "HasSERIALIZE", "true", "Has serialize instruction">; def FeatureTSXLDTRK : SubtargetFeature<"tsxldtrk", "HasTSXLDTRK", "true", "Support TSXLDTRK instructions">; -def FeatureUINTR : SubtargetFeature<"uintr", "HasUINTR", "true", - "Has UINTR Instructions">; +def FeatureUINTR : SubtargetFeature<"uintr", "HasUINTR", "true", + "Has UINTR Instructions">; // On some processors, instructions that implicitly take two memory operands are // slow. In practice, this means that CALL, PUSH, and POP with memory operands // should be avoided in favor of a MOV + register CALL/PUSH/POP. @@ -385,12 +385,12 @@ def FeatureERMSB "ermsb", "HasERMSB", "true", "REP MOVS/STOS are fast">; -// Icelake and newer processors have Fast Short REP MOV. -def FeatureFSRM - : SubtargetFeature< - "fsrm", "HasFSRM", "true", - "REP MOVSB of short lengths is faster">; - +// Icelake and newer processors have Fast Short REP MOV. +def FeatureFSRM + : SubtargetFeature< + "fsrm", "HasFSRM", "true", + "REP MOVSB of short lengths is faster">; + // Bulldozer and newer processors can merge CMP/TEST (but not other // instructions) with conditional branches. def FeatureBranchFusion @@ -565,59 +565,59 @@ include "X86SchedSkylakeServer.td" //===----------------------------------------------------------------------===// def ProcessorFeatures { - // x86-64 and x86-64-v[234] - list<SubtargetFeature> X86_64V1Features = [ - FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, FeatureMMX, FeatureSSE2, - FeatureFXSR, FeatureNOPL, Feature64Bit - ]; - list<SubtargetFeature> X86_64V2Features = !listconcat( - X86_64V1Features, - [FeatureCMPXCHG16B, FeatureLAHFSAHF, FeaturePOPCNT, FeatureSSE42]); - list<SubtargetFeature> X86_64V3Features = !listconcat(X86_64V2Features, [ - FeatureAVX2, FeatureBMI, FeatureBMI2, FeatureF16C, FeatureFMA, FeatureLZCNT, - FeatureMOVBE, FeatureXSAVE - ]); - list<SubtargetFeature> X86_64V4Features = !listconcat(X86_64V3Features, [ - FeatureBWI, - FeatureCDI, - FeatureDQI, - FeatureVLX, - ]); - + // x86-64 and x86-64-v[234] + list<SubtargetFeature> X86_64V1Features = [ + FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, FeatureMMX, FeatureSSE2, + FeatureFXSR, FeatureNOPL, Feature64Bit + ]; + list<SubtargetFeature> X86_64V2Features = !listconcat( + X86_64V1Features, + [FeatureCMPXCHG16B, FeatureLAHFSAHF, FeaturePOPCNT, FeatureSSE42]); + list<SubtargetFeature> X86_64V3Features = !listconcat(X86_64V2Features, [ + FeatureAVX2, FeatureBMI, FeatureBMI2, FeatureF16C, FeatureFMA, FeatureLZCNT, + FeatureMOVBE, FeatureXSAVE + ]); + list<SubtargetFeature> X86_64V4Features = !listconcat(X86_64V3Features, [ + FeatureBWI, + FeatureCDI, + FeatureDQI, + FeatureVLX, + ]); + // Nehalem - list<SubtargetFeature> NHMFeatures = X86_64V2Features; - list<SubtargetFeature> NHMTuning = [FeatureMacroFusion, - FeatureInsertVZEROUPPER]; + list<SubtargetFeature> NHMFeatures = X86_64V2Features; + list<SubtargetFeature> NHMTuning = [FeatureMacroFusion, + FeatureInsertVZEROUPPER]; // Westmere list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL]; - list<SubtargetFeature> WSMTuning = NHMTuning; + list<SubtargetFeature> WSMTuning = NHMTuning; list<SubtargetFeature> WSMFeatures = - !listconcat(NHMFeatures, WSMAdditionalFeatures); + !listconcat(NHMFeatures, WSMAdditionalFeatures); // Sandybridge list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX, FeatureXSAVE, - FeatureXSAVEOPT]; - list<SubtargetFeature> SNBTuning = [FeatureMacroFusion, - FeatureSlow3OpsLEA, - FeatureSlowDivide64, - FeatureSlowUAMem32, - FeatureFastScalarFSQRT, - FeatureFastSHLDRotate, - FeatureFast15ByteNOP, - FeaturePOPCNTFalseDeps, - FeatureInsertVZEROUPPER]; + FeatureXSAVEOPT]; + list<SubtargetFeature> SNBTuning = [FeatureMacroFusion, + FeatureSlow3OpsLEA, + FeatureSlowDivide64, + FeatureSlowUAMem32, + FeatureFastScalarFSQRT, + FeatureFastSHLDRotate, + FeatureFast15ByteNOP, + FeaturePOPCNTFalseDeps, + FeatureInsertVZEROUPPER]; list<SubtargetFeature> SNBFeatures = - !listconcat(WSMFeatures, SNBAdditionalFeatures); + !listconcat(WSMFeatures, SNBAdditionalFeatures); // Ivybridge list<SubtargetFeature> IVBAdditionalFeatures = [FeatureRDRAND, FeatureF16C, FeatureFSGSBase]; - list<SubtargetFeature> IVBTuning = SNBTuning; + list<SubtargetFeature> IVBTuning = SNBTuning; list<SubtargetFeature> IVBFeatures = - !listconcat(SNBFeatures, IVBAdditionalFeatures); + !listconcat(SNBFeatures, IVBAdditionalFeatures); // Haswell list<SubtargetFeature> HSWAdditionalFeatures = [FeatureAVX2, @@ -627,86 +627,86 @@ def ProcessorFeatures { FeatureFMA, FeatureINVPCID, FeatureLZCNT, - FeatureMOVBE]; - list<SubtargetFeature> HSWTuning = [FeatureMacroFusion, - FeatureSlow3OpsLEA, - FeatureSlowDivide64, - FeatureFastScalarFSQRT, - FeatureFastSHLDRotate, - FeatureFast15ByteNOP, - FeatureFastVariableShuffle, - FeaturePOPCNTFalseDeps, - FeatureLZCNTFalseDeps, - FeatureInsertVZEROUPPER]; + FeatureMOVBE]; + list<SubtargetFeature> HSWTuning = [FeatureMacroFusion, + FeatureSlow3OpsLEA, + FeatureSlowDivide64, + FeatureFastScalarFSQRT, + FeatureFastSHLDRotate, + FeatureFast15ByteNOP, + FeatureFastVariableShuffle, + FeaturePOPCNTFalseDeps, + FeatureLZCNTFalseDeps, + FeatureInsertVZEROUPPER]; list<SubtargetFeature> HSWFeatures = - !listconcat(IVBFeatures, HSWAdditionalFeatures); + !listconcat(IVBFeatures, HSWAdditionalFeatures); // Broadwell list<SubtargetFeature> BDWAdditionalFeatures = [FeatureADX, FeatureRDSEED, FeaturePRFCHW]; - list<SubtargetFeature> BDWTuning = HSWTuning; + list<SubtargetFeature> BDWTuning = HSWTuning; list<SubtargetFeature> BDWFeatures = - !listconcat(HSWFeatures, BDWAdditionalFeatures); + !listconcat(HSWFeatures, BDWAdditionalFeatures); // Skylake list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES, FeatureXSAVEC, FeatureXSAVES, FeatureCLFLUSHOPT, - FeatureSGX]; - list<SubtargetFeature> SKLTuning = [FeatureHasFastGather, - FeatureMacroFusion, - FeatureSlow3OpsLEA, - FeatureSlowDivide64, - FeatureFastScalarFSQRT, - FeatureFastVectorFSQRT, - FeatureFastSHLDRotate, - FeatureFast15ByteNOP, - FeatureFastVariableShuffle, - FeaturePOPCNTFalseDeps, - FeatureInsertVZEROUPPER]; + FeatureSGX]; + list<SubtargetFeature> SKLTuning = [FeatureHasFastGather, + FeatureMacroFusion, + FeatureSlow3OpsLEA, + FeatureSlowDivide64, + FeatureFastScalarFSQRT, + FeatureFastVectorFSQRT, + FeatureFastSHLDRotate, + FeatureFast15ByteNOP, + FeatureFastVariableShuffle, + FeaturePOPCNTFalseDeps, + FeatureInsertVZEROUPPER]; list<SubtargetFeature> SKLFeatures = - !listconcat(BDWFeatures, SKLAdditionalFeatures); + !listconcat(BDWFeatures, SKLAdditionalFeatures); // Skylake-AVX512 - list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAES, - FeatureXSAVEC, - FeatureXSAVES, - FeatureCLFLUSHOPT, - FeatureAVX512, + list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAES, + FeatureXSAVEC, + FeatureXSAVES, + FeatureCLFLUSHOPT, + FeatureAVX512, FeatureCDI, FeatureDQI, FeatureBWI, FeatureVLX, FeaturePKU, FeatureCLWB]; - list<SubtargetFeature> SKXTuning = [FeatureHasFastGather, - FeatureMacroFusion, - FeatureSlow3OpsLEA, - FeatureSlowDivide64, - FeatureFastScalarFSQRT, - FeatureFastVectorFSQRT, - FeatureFastSHLDRotate, - FeatureFast15ByteNOP, - FeatureFastVariableShuffle, - FeaturePrefer256Bit, - FeaturePOPCNTFalseDeps, - FeatureInsertVZEROUPPER]; + list<SubtargetFeature> SKXTuning = [FeatureHasFastGather, + FeatureMacroFusion, + FeatureSlow3OpsLEA, + FeatureSlowDivide64, + FeatureFastScalarFSQRT, + FeatureFastVectorFSQRT, + FeatureFastSHLDRotate, + FeatureFast15ByteNOP, + FeatureFastVariableShuffle, + FeaturePrefer256Bit, + FeaturePOPCNTFalseDeps, + FeatureInsertVZEROUPPER]; list<SubtargetFeature> SKXFeatures = - !listconcat(BDWFeatures, SKXAdditionalFeatures); + !listconcat(BDWFeatures, SKXAdditionalFeatures); // Cascadelake list<SubtargetFeature> CLXAdditionalFeatures = [FeatureVNNI]; - list<SubtargetFeature> CLXTuning = SKXTuning; + list<SubtargetFeature> CLXTuning = SKXTuning; list<SubtargetFeature> CLXFeatures = - !listconcat(SKXFeatures, CLXAdditionalFeatures); + !listconcat(SKXFeatures, CLXAdditionalFeatures); // Cooperlake list<SubtargetFeature> CPXAdditionalFeatures = [FeatureBF16]; - list<SubtargetFeature> CPXTuning = SKXTuning; + list<SubtargetFeature> CPXTuning = SKXTuning; list<SubtargetFeature> CPXFeatures = - !listconcat(CLXFeatures, CPXAdditionalFeatures); + !listconcat(CLXFeatures, CPXAdditionalFeatures); // Cannonlake list<SubtargetFeature> CNLAdditionalFeatures = [FeatureAVX512, @@ -717,20 +717,20 @@ def ProcessorFeatures { FeaturePKU, FeatureVBMI, FeatureIFMA, - FeatureSHA]; - list<SubtargetFeature> CNLTuning = [FeatureHasFastGather, - FeatureMacroFusion, - FeatureSlow3OpsLEA, - FeatureSlowDivide64, - FeatureFastScalarFSQRT, - FeatureFastVectorFSQRT, - FeatureFastSHLDRotate, - FeatureFast15ByteNOP, - FeatureFastVariableShuffle, - FeaturePrefer256Bit, - FeatureInsertVZEROUPPER]; + FeatureSHA]; + list<SubtargetFeature> CNLTuning = [FeatureHasFastGather, + FeatureMacroFusion, + FeatureSlow3OpsLEA, + FeatureSlowDivide64, + FeatureFastScalarFSQRT, + FeatureFastVectorFSQRT, + FeatureFastSHLDRotate, + FeatureFast15ByteNOP, + FeatureFastVariableShuffle, + FeaturePrefer256Bit, + FeatureInsertVZEROUPPER]; list<SubtargetFeature> CNLFeatures = - !listconcat(SKLFeatures, CNLAdditionalFeatures); + !listconcat(SKLFeatures, CNLAdditionalFeatures); // Icelake list<SubtargetFeature> ICLAdditionalFeatures = [FeatureBITALG, @@ -741,81 +741,81 @@ def ProcessorFeatures { FeatureVPOPCNTDQ, FeatureGFNI, FeatureCLWB, - FeatureRDPID, - FeatureFSRM]; - list<SubtargetFeature> ICLTuning = CNLTuning; + FeatureRDPID, + FeatureFSRM]; + list<SubtargetFeature> ICLTuning = CNLTuning; list<SubtargetFeature> ICLFeatures = - !listconcat(CNLFeatures, ICLAdditionalFeatures); + !listconcat(CNLFeatures, ICLAdditionalFeatures); // Icelake Server - list<SubtargetFeature> ICXAdditionalFeatures = [FeaturePCONFIG, - FeatureWBNOINVD]; - list<SubtargetFeature> ICXTuning = CNLTuning; + list<SubtargetFeature> ICXAdditionalFeatures = [FeaturePCONFIG, + FeatureWBNOINVD]; + list<SubtargetFeature> ICXTuning = CNLTuning; list<SubtargetFeature> ICXFeatures = - !listconcat(ICLFeatures, ICXAdditionalFeatures); + !listconcat(ICLFeatures, ICXAdditionalFeatures); //Tigerlake list<SubtargetFeature> TGLAdditionalFeatures = [FeatureVP2INTERSECT, FeatureMOVDIRI, FeatureMOVDIR64B, FeatureSHSTK]; - list<SubtargetFeature> TGLTuning = CNLTuning; + list<SubtargetFeature> TGLTuning = CNLTuning; list<SubtargetFeature> TGLFeatures = - !listconcat(ICLFeatures, TGLAdditionalFeatures ); - - //Sapphirerapids - list<SubtargetFeature> SPRAdditionalFeatures = [FeatureAMXTILE, - FeatureAMXINT8, - FeatureAMXBF16, - FeatureBF16, - FeatureSERIALIZE, - FeatureCLDEMOTE, - FeatureWAITPKG, - FeaturePTWRITE, - FeatureAVXVNNI, - FeatureTSXLDTRK, - FeatureENQCMD, - FeatureSHSTK, - FeatureVP2INTERSECT, - FeatureMOVDIRI, - FeatureMOVDIR64B, - FeatureUINTR]; - list<SubtargetFeature> SPRTuning = ICXTuning; - list<SubtargetFeature> SPRFeatures = - !listconcat(ICXFeatures, SPRAdditionalFeatures); - - // Alderlake - list<SubtargetFeature> ADLAdditionalFeatures = [FeatureAVXVNNI, - FeatureCLDEMOTE, - FeatureHRESET, - FeaturePTWRITE, - FeatureSERIALIZE, - FeatureWAITPKG]; - list<SubtargetFeature> ADLTuning = SKLTuning; - list<SubtargetFeature> ADLFeatures = - !listconcat(SKLFeatures, ADLAdditionalFeatures); - + !listconcat(ICLFeatures, TGLAdditionalFeatures ); + + //Sapphirerapids + list<SubtargetFeature> SPRAdditionalFeatures = [FeatureAMXTILE, + FeatureAMXINT8, + FeatureAMXBF16, + FeatureBF16, + FeatureSERIALIZE, + FeatureCLDEMOTE, + FeatureWAITPKG, + FeaturePTWRITE, + FeatureAVXVNNI, + FeatureTSXLDTRK, + FeatureENQCMD, + FeatureSHSTK, + FeatureVP2INTERSECT, + FeatureMOVDIRI, + FeatureMOVDIR64B, + FeatureUINTR]; + list<SubtargetFeature> SPRTuning = ICXTuning; + list<SubtargetFeature> SPRFeatures = + !listconcat(ICXFeatures, SPRAdditionalFeatures); + + // Alderlake + list<SubtargetFeature> ADLAdditionalFeatures = [FeatureAVXVNNI, + FeatureCLDEMOTE, + FeatureHRESET, + FeaturePTWRITE, + FeatureSERIALIZE, + FeatureWAITPKG]; + list<SubtargetFeature> ADLTuning = SKLTuning; + list<SubtargetFeature> ADLFeatures = + !listconcat(SKLFeatures, ADLAdditionalFeatures); + // Atom - list<SubtargetFeature> AtomFeatures = [FeatureX87, - FeatureCMPXCHG8B, - FeatureCMOV, - FeatureMMX, - FeatureSSSE3, - FeatureFXSR, - FeatureNOPL, - Feature64Bit, - FeatureCMPXCHG16B, - FeatureMOVBE, - FeatureLAHFSAHF]; - list<SubtargetFeature> AtomTuning = [ProcIntelAtom, - FeatureSlowUAMem16, - FeatureLEAForSP, - FeatureSlowDivide32, - FeatureSlowDivide64, - FeatureSlowTwoMemOps, - FeatureLEAUsesAG, - FeaturePadShortFunctions, - FeatureInsertVZEROUPPER]; + list<SubtargetFeature> AtomFeatures = [FeatureX87, + FeatureCMPXCHG8B, + FeatureCMOV, + FeatureMMX, + FeatureSSSE3, + FeatureFXSR, + FeatureNOPL, + Feature64Bit, + FeatureCMPXCHG16B, + FeatureMOVBE, + FeatureLAHFSAHF]; + list<SubtargetFeature> AtomTuning = [ProcIntelAtom, + FeatureSlowUAMem16, + FeatureLEAForSP, + FeatureSlowDivide32, + FeatureSlowDivide64, + FeatureSlowTwoMemOps, + FeatureLEAUsesAG, + FeaturePadShortFunctions, + FeatureInsertVZEROUPPER]; // Silvermont list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42, @@ -823,17 +823,17 @@ def ProcessorFeatures { FeaturePCLMUL, FeaturePRFCHW, FeatureRDRAND]; - list<SubtargetFeature> SLMTuning = [ProcIntelSLM, - FeatureSlowTwoMemOps, - FeatureSlowLEA, - FeatureSlowIncDec, - FeatureSlowDivide64, - FeatureSlowPMULLD, - FeatureFast7ByteNOP, - FeaturePOPCNTFalseDeps, - FeatureInsertVZEROUPPER]; + list<SubtargetFeature> SLMTuning = [ProcIntelSLM, + FeatureSlowTwoMemOps, + FeatureSlowLEA, + FeatureSlowIncDec, + FeatureSlowDivide64, + FeatureSlowPMULLD, + FeatureFast7ByteNOP, + FeaturePOPCNTFalseDeps, + FeatureInsertVZEROUPPER]; list<SubtargetFeature> SLMFeatures = - !listconcat(AtomFeatures, SLMAdditionalFeatures); + !listconcat(AtomFeatures, SLMAdditionalFeatures); // Goldmont list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES, @@ -845,33 +845,33 @@ def ProcessorFeatures { FeatureXSAVES, FeatureCLFLUSHOPT, FeatureFSGSBase]; - list<SubtargetFeature> GLMTuning = [FeatureUseGLMDivSqrtCosts, - FeatureSlowTwoMemOps, - FeatureSlowLEA, - FeatureSlowIncDec, - FeaturePOPCNTFalseDeps, - FeatureInsertVZEROUPPER]; + list<SubtargetFeature> GLMTuning = [FeatureUseGLMDivSqrtCosts, + FeatureSlowTwoMemOps, + FeatureSlowLEA, + FeatureSlowIncDec, + FeaturePOPCNTFalseDeps, + FeatureInsertVZEROUPPER]; list<SubtargetFeature> GLMFeatures = - !listconcat(SLMFeatures, GLMAdditionalFeatures); + !listconcat(SLMFeatures, GLMAdditionalFeatures); // Goldmont Plus list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE, FeatureRDPID, FeatureSGX]; - list<SubtargetFeature> GLPTuning = [FeatureUseGLMDivSqrtCosts, - FeatureSlowTwoMemOps, - FeatureSlowLEA, - FeatureSlowIncDec, - FeatureInsertVZEROUPPER]; + list<SubtargetFeature> GLPTuning = [FeatureUseGLMDivSqrtCosts, + FeatureSlowTwoMemOps, + FeatureSlowLEA, + FeatureSlowIncDec, + FeatureInsertVZEROUPPER]; list<SubtargetFeature> GLPFeatures = - !listconcat(GLMFeatures, GLPAdditionalFeatures); + !listconcat(GLMFeatures, GLPAdditionalFeatures); // Tremont list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLWB, FeatureGFNI]; - list<SubtargetFeature> TRMTuning = GLPTuning; + list<SubtargetFeature> TRMTuning = GLPTuning; list<SubtargetFeature> TRMFeatures = - !listconcat(GLPFeatures, TRMAdditionalFeatures); + !listconcat(GLPFeatures, TRMAdditionalFeatures); // Knights Landing list<SubtargetFeature> KNLFeatures = [FeatureX87, @@ -903,56 +903,56 @@ def ProcessorFeatures { FeatureBMI, FeatureBMI2, FeatureFMA, - FeaturePRFCHW]; - list<SubtargetFeature> KNLTuning = [FeatureSlowDivide64, - FeatureSlow3OpsLEA, - FeatureSlowIncDec, - FeatureSlowTwoMemOps, - FeaturePreferMaskRegisters, - FeatureHasFastGather, - FeatureSlowPMADDWD]; + FeaturePRFCHW]; + list<SubtargetFeature> KNLTuning = [FeatureSlowDivide64, + FeatureSlow3OpsLEA, + FeatureSlowIncDec, + FeatureSlowTwoMemOps, + FeaturePreferMaskRegisters, + FeatureHasFastGather, + FeatureSlowPMADDWD]; // TODO Add AVX5124FMAPS/AVX5124VNNIW features list<SubtargetFeature> KNMFeatures = !listconcat(KNLFeatures, [FeatureVPOPCNTDQ]); // Barcelona - list<SubtargetFeature> BarcelonaFeatures = [FeatureX87, - FeatureCMPXCHG8B, - FeatureSSE4A, - Feature3DNowA, - FeatureFXSR, - FeatureNOPL, - FeatureCMPXCHG16B, - FeaturePRFCHW, - FeatureLZCNT, - FeaturePOPCNT, - FeatureLAHFSAHF, - FeatureCMOV, - Feature64Bit]; - list<SubtargetFeature> BarcelonaTuning = [FeatureFastScalarShiftMasks, - FeatureSlowSHLD, - FeatureInsertVZEROUPPER]; + list<SubtargetFeature> BarcelonaFeatures = [FeatureX87, + FeatureCMPXCHG8B, + FeatureSSE4A, + Feature3DNowA, + FeatureFXSR, + FeatureNOPL, + FeatureCMPXCHG16B, + FeaturePRFCHW, + FeatureLZCNT, + FeaturePOPCNT, + FeatureLAHFSAHF, + FeatureCMOV, + Feature64Bit]; + list<SubtargetFeature> BarcelonaTuning = [FeatureFastScalarShiftMasks, + FeatureSlowSHLD, + FeatureInsertVZEROUPPER]; // Bobcat - list<SubtargetFeature> BtVer1Features = [FeatureX87, - FeatureCMPXCHG8B, - FeatureCMOV, - FeatureMMX, - FeatureSSSE3, - FeatureSSE4A, - FeatureFXSR, - FeatureNOPL, - Feature64Bit, - FeatureCMPXCHG16B, - FeaturePRFCHW, - FeatureLZCNT, - FeaturePOPCNT, - FeatureLAHFSAHF]; - list<SubtargetFeature> BtVer1Tuning = [FeatureFast15ByteNOP, - FeatureFastScalarShiftMasks, - FeatureFastVectorShiftMasks, - FeatureSlowSHLD, - FeatureInsertVZEROUPPER]; + list<SubtargetFeature> BtVer1Features = [FeatureX87, + FeatureCMPXCHG8B, + FeatureCMOV, + FeatureMMX, + FeatureSSSE3, + FeatureSSE4A, + FeatureFXSR, + FeatureNOPL, + Feature64Bit, + FeatureCMPXCHG16B, + FeaturePRFCHW, + FeatureLZCNT, + FeaturePOPCNT, + FeatureLAHFSAHF]; + list<SubtargetFeature> BtVer1Tuning = [FeatureFast15ByteNOP, + FeatureFastScalarShiftMasks, + FeatureFastVectorShiftMasks, + FeatureSlowSHLD, + FeatureInsertVZEROUPPER]; // Jaguar list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX, @@ -963,39 +963,39 @@ def ProcessorFeatures { FeatureMOVBE, FeatureXSAVE, FeatureXSAVEOPT]; - list<SubtargetFeature> BtVer2Tuning = [FeatureFastLZCNT, - FeatureFastBEXTR, - FeatureFastHorizontalOps, - FeatureFast15ByteNOP, - FeatureFastScalarShiftMasks, - FeatureFastVectorShiftMasks, - FeatureSlowSHLD]; + list<SubtargetFeature> BtVer2Tuning = [FeatureFastLZCNT, + FeatureFastBEXTR, + FeatureFastHorizontalOps, + FeatureFast15ByteNOP, + FeatureFastScalarShiftMasks, + FeatureFastVectorShiftMasks, + FeatureSlowSHLD]; list<SubtargetFeature> BtVer2Features = - !listconcat(BtVer1Features, BtVer2AdditionalFeatures); + !listconcat(BtVer1Features, BtVer2AdditionalFeatures); // Bulldozer - list<SubtargetFeature> BdVer1Features = [FeatureX87, - FeatureCMPXCHG8B, - FeatureCMOV, - FeatureXOP, - Feature64Bit, - FeatureCMPXCHG16B, - FeatureAES, - FeaturePRFCHW, - FeaturePCLMUL, - FeatureMMX, - FeatureFXSR, - FeatureNOPL, - FeatureLZCNT, - FeaturePOPCNT, - FeatureXSAVE, - FeatureLWP, - FeatureLAHFSAHF]; - list<SubtargetFeature> BdVer1Tuning = [FeatureSlowSHLD, - FeatureFast11ByteNOP, - FeatureFastScalarShiftMasks, - FeatureBranchFusion, - FeatureInsertVZEROUPPER]; + list<SubtargetFeature> BdVer1Features = [FeatureX87, + FeatureCMPXCHG8B, + FeatureCMOV, + FeatureXOP, + Feature64Bit, + FeatureCMPXCHG16B, + FeatureAES, + FeaturePRFCHW, + FeaturePCLMUL, + FeatureMMX, + FeatureFXSR, + FeatureNOPL, + FeatureLZCNT, + FeaturePOPCNT, + FeatureXSAVE, + FeatureLWP, + FeatureLAHFSAHF]; + list<SubtargetFeature> BdVer1Tuning = [FeatureSlowSHLD, + FeatureFast11ByteNOP, + FeatureFastScalarShiftMasks, + FeatureBranchFusion, + FeatureInsertVZEROUPPER]; // PileDriver list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C, @@ -1003,16 +1003,16 @@ def ProcessorFeatures { FeatureTBM, FeatureFMA, FeatureFastBEXTR]; - list<SubtargetFeature> BdVer2Tuning = BdVer1Tuning; - list<SubtargetFeature> BdVer2Features = - !listconcat(BdVer1Features, BdVer2AdditionalFeatures); + list<SubtargetFeature> BdVer2Tuning = BdVer1Tuning; + list<SubtargetFeature> BdVer2Features = + !listconcat(BdVer1Features, BdVer2AdditionalFeatures); // Steamroller list<SubtargetFeature> BdVer3AdditionalFeatures = [FeatureXSAVEOPT, FeatureFSGSBase]; - list<SubtargetFeature> BdVer3Tuning = BdVer2Tuning; - list<SubtargetFeature> BdVer3Features = - !listconcat(BdVer2Features, BdVer3AdditionalFeatures); + list<SubtargetFeature> BdVer3Tuning = BdVer2Tuning; + list<SubtargetFeature> BdVer3Features = + !listconcat(BdVer2Features, BdVer3AdditionalFeatures); // Excavator list<SubtargetFeature> BdVer4AdditionalFeatures = [FeatureAVX2, @@ -1020,9 +1020,9 @@ def ProcessorFeatures { FeatureMOVBE, FeatureRDRAND, FeatureMWAITX]; - list<SubtargetFeature> BdVer4Tuning = BdVer3Tuning; - list<SubtargetFeature> BdVer4Features = - !listconcat(BdVer3Features, BdVer4AdditionalFeatures); + list<SubtargetFeature> BdVer4Tuning = BdVer3Tuning; + list<SubtargetFeature> BdVer4Features = + !listconcat(BdVer3Features, BdVer4AdditionalFeatures); // AMD Zen Processors common ISAs @@ -1058,80 +1058,80 @@ def ProcessorFeatures { FeatureXSAVEC, FeatureXSAVEOPT, FeatureXSAVES]; - list<SubtargetFeature> ZNTuning = [FeatureFastLZCNT, - FeatureFastBEXTR, - FeatureFast15ByteNOP, - FeatureBranchFusion, - FeatureFastScalarShiftMasks, - FeatureSlowSHLD, - FeatureInsertVZEROUPPER]; + list<SubtargetFeature> ZNTuning = [FeatureFastLZCNT, + FeatureFastBEXTR, + FeatureFast15ByteNOP, + FeatureBranchFusion, + FeatureFastScalarShiftMasks, + FeatureSlowSHLD, + FeatureInsertVZEROUPPER]; list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB, FeatureRDPID, FeatureWBNOINVD]; - list<SubtargetFeature> ZN2Tuning = ZNTuning; + list<SubtargetFeature> ZN2Tuning = ZNTuning; list<SubtargetFeature> ZN2Features = !listconcat(ZNFeatures, ZN2AdditionalFeatures); - list<SubtargetFeature> ZN3AdditionalFeatures = [FeatureFSRM, - FeatureINVPCID, - FeaturePKU, - FeatureVAES, - FeatureVPCLMULQDQ]; - list<SubtargetFeature> ZN3Tuning = ZNTuning; - list<SubtargetFeature> ZN3Features = - !listconcat(ZN2Features, ZN3AdditionalFeatures); + list<SubtargetFeature> ZN3AdditionalFeatures = [FeatureFSRM, + FeatureINVPCID, + FeaturePKU, + FeatureVAES, + FeatureVPCLMULQDQ]; + list<SubtargetFeature> ZN3Tuning = ZNTuning; + list<SubtargetFeature> ZN3Features = + !listconcat(ZN2Features, ZN3AdditionalFeatures); } //===----------------------------------------------------------------------===// // X86 processors supported. //===----------------------------------------------------------------------===// -class Proc<string Name, list<SubtargetFeature> Features, - list<SubtargetFeature> TuneFeatures> - : ProcessorModel<Name, GenericModel, Features, TuneFeatures>; - -class ProcModel<string Name, SchedMachineModel Model, - list<SubtargetFeature> Features, - list<SubtargetFeature> TuneFeatures> - : ProcessorModel<Name, Model, Features, TuneFeatures>; +class Proc<string Name, list<SubtargetFeature> Features, + list<SubtargetFeature> TuneFeatures> + : ProcessorModel<Name, GenericModel, Features, TuneFeatures>; +class ProcModel<string Name, SchedMachineModel Model, + list<SubtargetFeature> Features, + list<SubtargetFeature> TuneFeatures> + : ProcessorModel<Name, Model, Features, TuneFeatures>; + // NOTE: CMPXCHG8B is here for legacy compatibility so that it is only disabled // if i386/i486 is specifically requested. -// NOTE: 64Bit is here as "generic" is the default llc CPU. The X86Subtarget -// constructor checks that any CPU used in 64-bit mode has Feature64Bit enabled. -// It has no effect on code generation. -def : ProcModel<"generic", SandyBridgeModel, - [FeatureX87, FeatureCMPXCHG8B, Feature64Bit], - [FeatureSlow3OpsLEA, - FeatureSlowDivide64, - FeatureSlowIncDec, - FeatureMacroFusion, - FeatureInsertVZEROUPPER]>; - -def : Proc<"i386", [FeatureX87], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; -def : Proc<"i486", [FeatureX87], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; -def : Proc<"i586", [FeatureX87, FeatureCMPXCHG8B], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; -def : Proc<"pentium", [FeatureX87, FeatureCMPXCHG8B], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; -def : Proc<"pentium-mmx", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; - -def : Proc<"i686", [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; -def : Proc<"pentiumpro", [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, - FeatureNOPL], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; - -def : Proc<"pentium2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureCMOV, - FeatureFXSR, FeatureNOPL], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; - +// NOTE: 64Bit is here as "generic" is the default llc CPU. The X86Subtarget +// constructor checks that any CPU used in 64-bit mode has Feature64Bit enabled. +// It has no effect on code generation. +def : ProcModel<"generic", SandyBridgeModel, + [FeatureX87, FeatureCMPXCHG8B, Feature64Bit], + [FeatureSlow3OpsLEA, + FeatureSlowDivide64, + FeatureSlowIncDec, + FeatureMacroFusion, + FeatureInsertVZEROUPPER]>; + +def : Proc<"i386", [FeatureX87], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; +def : Proc<"i486", [FeatureX87], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; +def : Proc<"i586", [FeatureX87, FeatureCMPXCHG8B], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; +def : Proc<"pentium", [FeatureX87, FeatureCMPXCHG8B], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; +def : Proc<"pentium-mmx", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; + +def : Proc<"i686", [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; +def : Proc<"pentiumpro", [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, + FeatureNOPL], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; + +def : Proc<"pentium2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureCMOV, + FeatureFXSR, FeatureNOPL], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; + foreach P = ["pentium3", "pentium3m"] in { - def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, - FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; + def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, + FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; } // Enable the PostRAScheduler for SSE2 and SSE3 class cpus. @@ -1144,34 +1144,34 @@ foreach P = ["pentium3", "pentium3m"] in { // measure to avoid performance surprises, in case clang's default cpu // changes slightly. -def : ProcModel<"pentium-m", GenericPostRAModel, - [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2, - FeatureFXSR, FeatureNOPL, FeatureCMOV], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; +def : ProcModel<"pentium-m", GenericPostRAModel, + [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2, + FeatureFXSR, FeatureNOPL, FeatureCMOV], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; foreach P = ["pentium4", "pentium4m"] in { - def : ProcModel<P, GenericPostRAModel, - [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2, - FeatureFXSR, FeatureNOPL, FeatureCMOV], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; + def : ProcModel<P, GenericPostRAModel, + [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2, + FeatureFXSR, FeatureNOPL, FeatureCMOV], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; } // Intel Quark. -def : Proc<"lakemont", [FeatureCMPXCHG8B], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; +def : Proc<"lakemont", [FeatureCMPXCHG8B], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; // Intel Core Duo. -def : ProcModel<"yonah", SandyBridgeModel, - [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3, - FeatureFXSR, FeatureNOPL, FeatureCMOV], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; +def : ProcModel<"yonah", SandyBridgeModel, + [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3, + FeatureFXSR, FeatureNOPL, FeatureCMOV], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; // NetBurst. -def : ProcModel<"prescott", GenericPostRAModel, - [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3, - FeatureFXSR, FeatureNOPL, FeatureCMOV], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; -def : ProcModel<"nocona", GenericPostRAModel, [ +def : ProcModel<"prescott", GenericPostRAModel, + [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3, + FeatureFXSR, FeatureNOPL, FeatureCMOV], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; +def : ProcModel<"nocona", GenericPostRAModel, [ FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, @@ -1181,14 +1181,14 @@ def : ProcModel<"nocona", GenericPostRAModel, [ FeatureNOPL, Feature64Bit, FeatureCMPXCHG16B, -], -[ - FeatureSlowUAMem16, +], +[ + FeatureSlowUAMem16, FeatureInsertVZEROUPPER ]>; // Intel Core 2 Solo/Duo. -def : ProcModel<"core2", SandyBridgeModel, [ +def : ProcModel<"core2", SandyBridgeModel, [ FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, @@ -1198,14 +1198,14 @@ def : ProcModel<"core2", SandyBridgeModel, [ FeatureNOPL, Feature64Bit, FeatureCMPXCHG16B, - FeatureLAHFSAHF -], -[ + FeatureLAHFSAHF +], +[ FeatureMacroFusion, - FeatureSlowUAMem16, + FeatureSlowUAMem16, FeatureInsertVZEROUPPER ]>; -def : ProcModel<"penryn", SandyBridgeModel, [ +def : ProcModel<"penryn", SandyBridgeModel, [ FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, @@ -1215,171 +1215,171 @@ def : ProcModel<"penryn", SandyBridgeModel, [ FeatureNOPL, Feature64Bit, FeatureCMPXCHG16B, - FeatureLAHFSAHF -], -[ + FeatureLAHFSAHF +], +[ FeatureMacroFusion, - FeatureSlowUAMem16, + FeatureSlowUAMem16, FeatureInsertVZEROUPPER ]>; // Atom CPUs. foreach P = ["bonnell", "atom"] in { - def : ProcModel<P, AtomModel, ProcessorFeatures.AtomFeatures, - ProcessorFeatures.AtomTuning>; + def : ProcModel<P, AtomModel, ProcessorFeatures.AtomFeatures, + ProcessorFeatures.AtomTuning>; } foreach P = ["silvermont", "slm"] in { - def : ProcModel<P, SLMModel, ProcessorFeatures.SLMFeatures, - ProcessorFeatures.SLMTuning>; + def : ProcModel<P, SLMModel, ProcessorFeatures.SLMFeatures, + ProcessorFeatures.SLMTuning>; } -def : ProcModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures, - ProcessorFeatures.GLMTuning>; -def : ProcModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures, - ProcessorFeatures.GLPTuning>; -def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures, - ProcessorFeatures.TRMTuning>; +def : ProcModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures, + ProcessorFeatures.GLMTuning>; +def : ProcModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures, + ProcessorFeatures.GLPTuning>; +def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures, + ProcessorFeatures.TRMTuning>; // "Arrandale" along with corei3 and corei5 foreach P = ["nehalem", "corei7"] in { - def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures, - ProcessorFeatures.NHMTuning>; + def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures, + ProcessorFeatures.NHMTuning>; } // Westmere is the corei3/i5/i7 path from nehalem to sandybridge -def : ProcModel<"westmere", SandyBridgeModel, ProcessorFeatures.WSMFeatures, - ProcessorFeatures.WSMTuning>; +def : ProcModel<"westmere", SandyBridgeModel, ProcessorFeatures.WSMFeatures, + ProcessorFeatures.WSMTuning>; foreach P = ["sandybridge", "corei7-avx"] in { - def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.SNBFeatures, - ProcessorFeatures.SNBTuning>; + def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.SNBFeatures, + ProcessorFeatures.SNBTuning>; } foreach P = ["ivybridge", "core-avx-i"] in { - def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.IVBFeatures, - ProcessorFeatures.IVBTuning>; + def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.IVBFeatures, + ProcessorFeatures.IVBTuning>; } foreach P = ["haswell", "core-avx2"] in { - def : ProcModel<P, HaswellModel, ProcessorFeatures.HSWFeatures, - ProcessorFeatures.HSWTuning>; + def : ProcModel<P, HaswellModel, ProcessorFeatures.HSWFeatures, + ProcessorFeatures.HSWTuning>; } -def : ProcModel<"broadwell", BroadwellModel, ProcessorFeatures.BDWFeatures, - ProcessorFeatures.BDWTuning>; +def : ProcModel<"broadwell", BroadwellModel, ProcessorFeatures.BDWFeatures, + ProcessorFeatures.BDWTuning>; -def : ProcModel<"skylake", SkylakeClientModel, ProcessorFeatures.SKLFeatures, - ProcessorFeatures.SKLTuning>; +def : ProcModel<"skylake", SkylakeClientModel, ProcessorFeatures.SKLFeatures, + ProcessorFeatures.SKLTuning>; // FIXME: define KNL scheduler model -def : ProcModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures, - ProcessorFeatures.KNLTuning>; -def : ProcModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures, - ProcessorFeatures.KNLTuning>; +def : ProcModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures, + ProcessorFeatures.KNLTuning>; +def : ProcModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures, + ProcessorFeatures.KNLTuning>; foreach P = ["skylake-avx512", "skx"] in { - def : ProcModel<P, SkylakeServerModel, ProcessorFeatures.SKXFeatures, - ProcessorFeatures.SKXTuning>; + def : ProcModel<P, SkylakeServerModel, ProcessorFeatures.SKXFeatures, + ProcessorFeatures.SKXTuning>; } -def : ProcModel<"cascadelake", SkylakeServerModel, - ProcessorFeatures.CLXFeatures, ProcessorFeatures.CLXTuning>; -def : ProcModel<"cooperlake", SkylakeServerModel, - ProcessorFeatures.CPXFeatures, ProcessorFeatures.CPXTuning>; -def : ProcModel<"cannonlake", SkylakeServerModel, - ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>; -def : ProcModel<"icelake-client", SkylakeServerModel, - ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>; -def : ProcModel<"icelake-server", SkylakeServerModel, - ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>; -def : ProcModel<"tigerlake", SkylakeServerModel, - ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>; -def : ProcModel<"sapphirerapids", SkylakeServerModel, - ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>; -def : ProcModel<"alderlake", SkylakeClientModel, - ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>; +def : ProcModel<"cascadelake", SkylakeServerModel, + ProcessorFeatures.CLXFeatures, ProcessorFeatures.CLXTuning>; +def : ProcModel<"cooperlake", SkylakeServerModel, + ProcessorFeatures.CPXFeatures, ProcessorFeatures.CPXTuning>; +def : ProcModel<"cannonlake", SkylakeServerModel, + ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>; +def : ProcModel<"icelake-client", SkylakeServerModel, + ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>; +def : ProcModel<"icelake-server", SkylakeServerModel, + ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>; +def : ProcModel<"tigerlake", SkylakeServerModel, + ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>; +def : ProcModel<"sapphirerapids", SkylakeServerModel, + ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>; +def : ProcModel<"alderlake", SkylakeClientModel, + ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>; // AMD CPUs. -def : Proc<"k6", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; -def : Proc<"k6-2", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; -def : Proc<"k6-3", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; +def : Proc<"k6", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; +def : Proc<"k6-2", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; +def : Proc<"k6-3", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; foreach P = ["athlon", "athlon-tbird"] in { - def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, Feature3DNowA, - FeatureNOPL], - [FeatureSlowSHLD, FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; + def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, Feature3DNowA, + FeatureNOPL], + [FeatureSlowSHLD, FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; } foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in { - def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, - FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL], - [FeatureSlowSHLD, FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; + def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, + FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL], + [FeatureSlowSHLD, FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; } foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in { - def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE2, Feature3DNowA, - FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureCMOV], - [FeatureFastScalarShiftMasks, FeatureSlowSHLD, FeatureSlowUAMem16, - FeatureInsertVZEROUPPER]>; + def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE2, Feature3DNowA, + FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureCMOV], + [FeatureFastScalarShiftMasks, FeatureSlowSHLD, FeatureSlowUAMem16, + FeatureInsertVZEROUPPER]>; } foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in { - def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE3, Feature3DNowA, - FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureCMOV, - Feature64Bit], - [FeatureFastScalarShiftMasks, FeatureSlowSHLD, FeatureSlowUAMem16, - FeatureInsertVZEROUPPER]>; + def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE3, Feature3DNowA, + FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureCMOV, + Feature64Bit], + [FeatureFastScalarShiftMasks, FeatureSlowSHLD, FeatureSlowUAMem16, + FeatureInsertVZEROUPPER]>; } foreach P = ["amdfam10", "barcelona"] in { - def : Proc<P, ProcessorFeatures.BarcelonaFeatures, - ProcessorFeatures.BarcelonaTuning>; + def : Proc<P, ProcessorFeatures.BarcelonaFeatures, + ProcessorFeatures.BarcelonaTuning>; } // Bobcat -def : Proc<"btver1", ProcessorFeatures.BtVer1Features, - ProcessorFeatures.BtVer1Tuning>; +def : Proc<"btver1", ProcessorFeatures.BtVer1Features, + ProcessorFeatures.BtVer1Tuning>; // Jaguar -def : ProcModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features, - ProcessorFeatures.BtVer2Tuning>; +def : ProcModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features, + ProcessorFeatures.BtVer2Tuning>; // Bulldozer -def : ProcModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features, - ProcessorFeatures.BdVer1Tuning>; +def : ProcModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features, + ProcessorFeatures.BdVer1Tuning>; // Piledriver -def : ProcModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features, - ProcessorFeatures.BdVer2Tuning>; +def : ProcModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features, + ProcessorFeatures.BdVer2Tuning>; // Steamroller -def : Proc<"bdver3", ProcessorFeatures.BdVer3Features, - ProcessorFeatures.BdVer3Tuning>; +def : Proc<"bdver3", ProcessorFeatures.BdVer3Features, + ProcessorFeatures.BdVer3Tuning>; // Excavator -def : Proc<"bdver4", ProcessorFeatures.BdVer4Features, - ProcessorFeatures.BdVer4Tuning>; - -def : ProcModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures, - ProcessorFeatures.ZNTuning>; -def : ProcModel<"znver2", Znver2Model, ProcessorFeatures.ZN2Features, - ProcessorFeatures.ZN2Tuning>; -def : ProcModel<"znver3", Znver2Model, ProcessorFeatures.ZN3Features, - ProcessorFeatures.ZN3Tuning>; - -def : Proc<"geode", [FeatureX87, FeatureCMPXCHG8B, Feature3DNowA], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; - -def : Proc<"winchip-c6", [FeatureX87, FeatureMMX], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; -def : Proc<"winchip2", [FeatureX87, Feature3DNow], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; -def : Proc<"c3", [FeatureX87, Feature3DNow], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; -def : Proc<"c3-2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, - FeatureSSE1, FeatureFXSR, FeatureCMOV], - [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; +def : Proc<"bdver4", ProcessorFeatures.BdVer4Features, + ProcessorFeatures.BdVer4Tuning>; + +def : ProcModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures, + ProcessorFeatures.ZNTuning>; +def : ProcModel<"znver2", Znver2Model, ProcessorFeatures.ZN2Features, + ProcessorFeatures.ZN2Tuning>; +def : ProcModel<"znver3", Znver2Model, ProcessorFeatures.ZN3Features, + ProcessorFeatures.ZN3Tuning>; + +def : Proc<"geode", [FeatureX87, FeatureCMPXCHG8B, Feature3DNowA], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; + +def : Proc<"winchip-c6", [FeatureX87, FeatureMMX], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; +def : Proc<"winchip2", [FeatureX87, Feature3DNow], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; +def : Proc<"c3", [FeatureX87, Feature3DNow], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; +def : Proc<"c3-2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, + FeatureSSE1, FeatureFXSR, FeatureCMOV], + [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; // We also provide a generic 64-bit specific x86 processor model which tries to // be good for modern chips without enabling instruction set encodings past the @@ -1391,8 +1391,8 @@ def : Proc<"c3-2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, // covers a huge swath of x86 processors. If there are specific scheduling // knobs which need to be tuned differently for AMD chips, we might consider // forming a common base for them. -def : ProcModel<"x86-64", SandyBridgeModel, ProcessorFeatures.X86_64V1Features, -[ +def : ProcModel<"x86-64", SandyBridgeModel, ProcessorFeatures.X86_64V1Features, +[ FeatureSlow3OpsLEA, FeatureSlowDivide64, FeatureSlowIncDec, @@ -1400,16 +1400,16 @@ def : ProcModel<"x86-64", SandyBridgeModel, ProcessorFeatures.X86_64V1Features, FeatureInsertVZEROUPPER ]>; -// x86-64 micro-architecture levels. -def : ProcModel<"x86-64-v2", SandyBridgeModel, ProcessorFeatures.X86_64V2Features, - ProcessorFeatures.SNBTuning>; -// Close to Haswell. -def : ProcModel<"x86-64-v3", HaswellModel, ProcessorFeatures.X86_64V3Features, - ProcessorFeatures.HSWTuning>; -// Close to the AVX-512 level implemented by Xeon Scalable Processors. -def : ProcModel<"x86-64-v4", HaswellModel, ProcessorFeatures.X86_64V4Features, - ProcessorFeatures.SKXTuning>; - +// x86-64 micro-architecture levels. +def : ProcModel<"x86-64-v2", SandyBridgeModel, ProcessorFeatures.X86_64V2Features, + ProcessorFeatures.SNBTuning>; +// Close to Haswell. +def : ProcModel<"x86-64-v3", HaswellModel, ProcessorFeatures.X86_64V3Features, + ProcessorFeatures.HSWTuning>; +// Close to the AVX-512 level implemented by Xeon Scalable Processors. +def : ProcModel<"x86-64-v4", HaswellModel, ProcessorFeatures.X86_64V4Features, + ProcessorFeatures.SKXTuning>; + //===----------------------------------------------------------------------===// // Calling Conventions //===----------------------------------------------------------------------===// |