Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 1 of 2.

1 files changed, 42 insertions, 42 deletions

diff --git a/contrib/libs/llvm12/lib/Target/PowerPC/PPCSubtarget.cpp b/contrib/libs/llvm12/lib/Target/PowerPC/PPCSubtarget.cpp
index d31195f67e..1ec28066dc 100644
--- a/contrib/libs/llvm12/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/contrib/libs/llvm12/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -11,13 +11,13 @@
 //===----------------------------------------------------------------------===//
 
 #include "PPCSubtarget.h"
-#include "GISel/PPCCallLowering.h"
-#include "GISel/PPCLegalizerInfo.h"
-#include "GISel/PPCRegisterBankInfo.h"
+#include "GISel/PPCCallLowering.h" 
+#include "GISel/PPCLegalizerInfo.h" 
+#include "GISel/PPCRegisterBankInfo.h" 
 #include "PPC.h"
 #include "PPCRegisterInfo.h"
 #include "PPCTargetMachine.h"
-#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
+#include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineScheduler.h"
 #include "llvm/IR/Attributes.h"
@@ -53,20 +53,20 @@ PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
 
 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS, const PPCTargetMachine &TM)
-    : PPCGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT),
+    : PPCGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT), 
       IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
               TargetTriple.getArch() == Triple::ppc64le),
       TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
-      InstrInfo(*this), TLInfo(TM, *this) {
-  CallLoweringInfo.reset(new PPCCallLowering(*getTargetLowering()));
-  Legalizer.reset(new PPCLegalizerInfo(*this));
-  auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo());
-  RegBankInfo.reset(RBI);
-
-  InstSelector.reset(createPPCInstructionSelector(
-      *static_cast<const PPCTargetMachine *>(&TM), *this, *RBI));
-}
-
+      InstrInfo(*this), TLInfo(TM, *this) { 
+  CallLoweringInfo.reset(new PPCCallLowering(*getTargetLowering())); 
+  Legalizer.reset(new PPCLegalizerInfo(*this)); 
+  auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo()); 
+  RegBankInfo.reset(RBI); 
+
+  InstSelector.reset(createPPCInstructionSelector( 
+      *static_cast<const PPCTargetMachine *>(&TM), *this, *RBI)); 
+} 
+ 
 void PPCSubtarget::initializeEnvironment() {
   StackAlignment = Align(16);
   CPUDirective = PPC::DIR_NONE;
@@ -77,7 +77,7 @@ void PPCSubtarget::initializeEnvironment() {
   HasHardFloat = false;
   HasAltivec = false;
   HasSPE = false;
-  HasEFPU2 = false;
+  HasEFPU2 = false; 
   HasFPU = false;
   HasVSX = false;
   NeedsTwoConstNR = false;
@@ -86,7 +86,7 @@ void PPCSubtarget::initializeEnvironment() {
   HasP8Crypto = false;
   HasP9Vector = false;
   HasP9Altivec = false;
-  HasMMA = false;
+  HasMMA = false; 
   HasP10Vector = false;
   HasPrefixInstrs = false;
   HasPCRelativeMemops = false;
@@ -121,7 +121,7 @@ void PPCSubtarget::initializeEnvironment() {
   HasHTM = false;
   HasFloat128 = false;
   HasFusion = false;
-  HasStoreFusion = false;
+  HasStoreFusion = false; 
   HasAddiLoadFusion = false;
   HasAddisLoadFusion = false;
   IsISA3_0 = false;
@@ -131,10 +131,10 @@ void PPCSubtarget::initializeEnvironment() {
   VectorsUseTwoUnits = false;
   UsePPCPreRASchedStrategy = false;
   UsePPCPostRASchedStrategy = false;
-  PairedVectorMemops = false;
+  PairedVectorMemops = false; 
   PredictableSelectIsExpensive = false;
-  HasModernAIXAs = false;
-  IsAIX = false;
+  HasModernAIXAs = false; 
+  IsAIX = false; 
 
   HasPOPCNTD = POPCNTD_Unavailable;
 }
@@ -156,7 +156,7 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   InstrItins = getInstrItineraryForCPU(CPUName);
 
   // Parse features string.
-  ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
+  ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS); 
 
   // If the user requested use of 64-bit regs, but the cpu selected doesn't
   // support it, ignore.
@@ -170,7 +170,7 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
 
   if (HasSPE && IsPPC64)
     report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
-  if (HasSPE && (HasAltivec || HasVSX || HasFPU))
+  if (HasSPE && (HasAltivec || HasVSX || HasFPU)) 
     report_fatal_error(
         "SPE and traditional floating point cannot both be enabled.\n", false);
 
@@ -182,8 +182,8 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
 
   // Determine endianness.
   // FIXME: Part of the TargetMachine.
-  IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le ||
-                    TargetTriple.getArch() == Triple::ppcle);
+  IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le || 
+                    TargetTriple.getArch() == Triple::ppcle); 
 }
 
 bool PPCSubtarget::enableMachineScheduler() const { return true; }
@@ -244,20 +244,20 @@ bool PPCSubtarget::isUsingPCRelativeCalls() const {
   return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&
          CodeModel::Medium == getTargetMachine().getCodeModel();
 }
-
-// GlobalISEL
-const CallLowering *PPCSubtarget::getCallLowering() const {
-  return CallLoweringInfo.get();
-}
-
-const RegisterBankInfo *PPCSubtarget::getRegBankInfo() const {
-  return RegBankInfo.get();
-}
-
-const LegalizerInfo *PPCSubtarget::getLegalizerInfo() const {
-  return Legalizer.get();
-}
-
-InstructionSelector *PPCSubtarget::getInstructionSelector() const {
-  return InstSelector.get();
-}
+ 
+// GlobalISEL 
+const CallLowering *PPCSubtarget::getCallLowering() const { 
+  return CallLoweringInfo.get(); 
+} 
+ 
+const RegisterBankInfo *PPCSubtarget::getRegBankInfo() const { 
+  return RegBankInfo.get(); 
+} 
+ 
+const LegalizerInfo *PPCSubtarget::getLegalizerInfo() const { 
+  return Legalizer.get(); 
+} 
+ 
+InstructionSelector *PPCSubtarget::getInstructionSelector() const { 
+  return InstSelector.get(); 
+}