Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 1 of 2.

1 files changed, 77 insertions, 77 deletions

diff --git a/contrib/libs/llvm12/lib/Target/PowerPC/PPCISelLowering.h b/contrib/libs/llvm12/lib/Target/PowerPC/PPCISelLowering.h
index 836c52bdff..2a0b6d3eb0 100644
--- a/contrib/libs/llvm12/lib/Target/PowerPC/PPCISelLowering.h
+++ b/contrib/libs/llvm12/lib/Target/PowerPC/PPCISelLowering.h
@@ -89,12 +89,12 @@ namespace llvm {
     FRE,
     FRSQRTE,
 
-    /// Test instruction for software square root.
-    FTSQRT,
-
-    /// Square root instruction.
-    FSQRT,
-
+    /// Test instruction for software square root. 
+    FTSQRT, 
+ 
+    /// Square root instruction. 
+    FSQRT, 
+ 
     /// VPERM - The PPC VPERM Instruction.
     ///
     VPERM,
@@ -152,7 +152,7 @@ namespace llvm {
     /// probed.
     PROBED_ALLOCA,
 
-    /// The result of the mflr at function entry, used for PIC code.
+    /// The result of the mflr at function entry, used for PIC code. 
     GlobalBaseReg,
 
     /// These nodes represent PPC shifts.
@@ -270,11 +270,11 @@ namespace llvm {
     /// is VCMPGTSH.
     VCMP,
 
-    /// RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the
-    /// altivec VCMP*_rec instructions.  For lack of better number, we use the
+    /// RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the 
+    /// altivec VCMP*_rec instructions.  For lack of better number, we use the 
     /// opcode number encoding for the OPC field to identify the compare.  For
     /// example, 838 is VCMPGTSH.
-    VCMP_rec,
+    VCMP_rec, 
 
     /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
     /// corresponds to the COND_BRANCH pseudo instruction.  CRRC is the
@@ -386,10 +386,10 @@ namespace llvm {
     /// sym\@got\@dtprel\@l.
     ADDI_DTPREL_L,
 
-    /// G8RC = PADDI_DTPREL %x3, Symbol - For the pc-rel based local-dynamic TLS
-    /// model, produces a PADDI8 instruction that adds X3 to sym\@dtprel.
-    PADDI_DTPREL,
-
+    /// G8RC = PADDI_DTPREL %x3, Symbol - For the pc-rel based local-dynamic TLS 
+    /// model, produces a PADDI8 instruction that adds X3 to sym\@dtprel. 
+    PADDI_DTPREL, 
+ 
     /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
     /// during instruction selection to optimize a BUILD_VECTOR into
     /// operations on splats.  This is necessary to avoid losing these
@@ -445,46 +445,46 @@ namespace llvm {
     /// PLD.
     MAT_PCREL_ADDR,
 
-    /// TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for
-    /// TLS global address when using dynamic access models. This can be done
-    /// through an add like PADDI.
-    TLS_DYNAMIC_MAT_PCREL_ADDR,
-
-    /// TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address
-    /// when using local exec access models, and when prefixed instructions are
-    /// available. This is used with ADD_TLS to produce an add like PADDI.
-    TLS_LOCAL_EXEC_MAT_ADDR,
-
-    /// ACC_BUILD = Build an accumulator register from 4 VSX registers.
-    ACC_BUILD,
-
-    /// PAIR_BUILD = Build a vector pair register from 2 VSX registers.
-    PAIR_BUILD,
-
-    /// EXTRACT_VSX_REG = Extract one of the underlying vsx registers of
-    /// an accumulator or pair register. This node is needed because
-    /// EXTRACT_SUBVECTOR expects the input and output vectors to have the same
-    /// element type.
-    EXTRACT_VSX_REG,
-
-    /// XXMFACC = This corresponds to the xxmfacc instruction.
-    XXMFACC,
-
-    // Constrained conversion from floating point to int
-    STRICT_FCTIDZ = ISD::FIRST_TARGET_STRICTFP_OPCODE,
-    STRICT_FCTIWZ,
-    STRICT_FCTIDUZ,
-    STRICT_FCTIWUZ,
-
-    /// Constrained integer-to-floating-point conversion instructions.
-    STRICT_FCFID,
-    STRICT_FCFIDU,
-    STRICT_FCFIDS,
-    STRICT_FCFIDUS,
-
-    /// Constrained floating point add in round-to-zero mode.
-    STRICT_FADDRTZ,
-
+    /// TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for 
+    /// TLS global address when using dynamic access models. This can be done 
+    /// through an add like PADDI. 
+    TLS_DYNAMIC_MAT_PCREL_ADDR, 
+ 
+    /// TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address 
+    /// when using local exec access models, and when prefixed instructions are 
+    /// available. This is used with ADD_TLS to produce an add like PADDI. 
+    TLS_LOCAL_EXEC_MAT_ADDR, 
+ 
+    /// ACC_BUILD = Build an accumulator register from 4 VSX registers. 
+    ACC_BUILD, 
+ 
+    /// PAIR_BUILD = Build a vector pair register from 2 VSX registers. 
+    PAIR_BUILD, 
+ 
+    /// EXTRACT_VSX_REG = Extract one of the underlying vsx registers of 
+    /// an accumulator or pair register. This node is needed because 
+    /// EXTRACT_SUBVECTOR expects the input and output vectors to have the same 
+    /// element type. 
+    EXTRACT_VSX_REG, 
+ 
+    /// XXMFACC = This corresponds to the xxmfacc instruction. 
+    XXMFACC, 
+ 
+    // Constrained conversion from floating point to int 
+    STRICT_FCTIDZ = ISD::FIRST_TARGET_STRICTFP_OPCODE, 
+    STRICT_FCTIWZ, 
+    STRICT_FCTIDUZ, 
+    STRICT_FCTIWUZ, 
+ 
+    /// Constrained integer-to-floating-point conversion instructions. 
+    STRICT_FCFID, 
+    STRICT_FCFIDU, 
+    STRICT_FCFIDS, 
+    STRICT_FCFIDUS, 
+ 
+    /// Constrained floating point add in round-to-zero mode. 
+    STRICT_FADDRTZ, 
+ 
     /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
     /// byte-swapping store instruction.  It byte-swaps the low "Type" bits of
     /// the GPRC input, then stores it through Ptr.  Type can be either i16 or
@@ -526,12 +526,12 @@ namespace llvm {
     /// an xxswapd.
     LXVD2X,
 
-    /// LXVRZX - Load VSX Vector Rightmost and Zero Extend
-    /// This node represents v1i128 BUILD_VECTOR of a zero extending load
-    /// instruction from <byte, halfword, word, or doubleword> to i128.
-    /// Allows utilization of the Load VSX Vector Rightmost Instructions.
-    LXVRZX,
-
+    /// LXVRZX - Load VSX Vector Rightmost and Zero Extend 
+    /// This node represents v1i128 BUILD_VECTOR of a zero extending load 
+    /// instruction from <byte, halfword, word, or doubleword> to i128. 
+    /// Allows utilization of the Load VSX Vector Rightmost Instructions. 
+    LXVRZX, 
+ 
     /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
     /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on
     /// the vector type to load vector in big-endian element order.
@@ -771,8 +771,8 @@ namespace llvm {
     bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
                              SelectionDAG &DAG,
                              MaybeAlign EncodingAlignment) const;
-    bool SelectAddressRegImm34(SDValue N, SDValue &Disp, SDValue &Base,
-                               SelectionDAG &DAG) const;
+    bool SelectAddressRegImm34(SDValue N, SDValue &Disp, SDValue &Base, 
+                               SelectionDAG &DAG) const; 
 
     /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
     /// represented as an indexed [r+r] operation.
@@ -928,9 +928,9 @@ namespace llvm {
       return true;
     }
 
-    bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
-                                SDValue C) const override;
-
+    bool decomposeMulByConstant(LLVMContext &Context, EVT VT, 
+                                SDValue C) const override; 
+ 
     bool isDesirableToTransformToIntegerOp(unsigned Opc,
                                            EVT VT) const override {
       // Only handle float load/store pair because float(fpr) load/store
@@ -987,9 +987,9 @@ namespace llvm {
     shouldExpandBuildVectorWithShuffles(EVT VT,
                                         unsigned DefinedValues) const override;
 
-    // Keep the zero-extensions for arguments to libcalls.
-    bool shouldKeepZExtForFP16Conv() const override { return true; }
-
+    // Keep the zero-extensions for arguments to libcalls. 
+    bool shouldKeepZExtForFP16Conv() const override { return true; } 
+ 
     /// createFastISel - This method returns a target-specific FastISel object,
     /// or null if the target does not support "fast" instruction selection.
     FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
@@ -1128,7 +1128,7 @@ namespace llvm {
     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; 
     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
@@ -1147,7 +1147,7 @@ namespace llvm {
     SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const; 
     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
@@ -1158,7 +1158,7 @@ namespace llvm {
     SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 
     SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
 
     SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
@@ -1275,10 +1275,10 @@ namespace llvm {
                             bool Reciprocal) const override;
     SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
                              int &RefinementSteps) const override;
-    SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
-                             const DenormalMode &Mode) const override;
-    SDValue getSqrtResultForDenormInput(SDValue Operand,
-                                        SelectionDAG &DAG) const override;
+    SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, 
+                             const DenormalMode &Mode) const override; 
+    SDValue getSqrtResultForDenormInput(SDValue Operand, 
+                                        SelectionDAG &DAG) const override; 
     unsigned combineRepeatedFPDivisors() const override;
 
     SDValue
@@ -1317,8 +1317,8 @@ namespace llvm {
 
   bool isIntS16Immediate(SDNode *N, int16_t &Imm);
   bool isIntS16Immediate(SDValue Op, int16_t &Imm);
-  bool isIntS34Immediate(SDNode *N, int64_t &Imm);
-  bool isIntS34Immediate(SDValue Op, int64_t &Imm);
+  bool isIntS34Immediate(SDNode *N, int64_t &Imm); 
+  bool isIntS34Immediate(SDValue Op, int64_t &Imm); 
 
   bool convertToNonDenormSingle(APInt &ArgAPInt);
   bool convertToNonDenormSingle(APFloat &ArgAPFloat);