Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 1 of 2.

1 files changed, 108 insertions, 108 deletions

diff --git a/contrib/libs/llvm12/lib/Target/AArch64/AArch64ISelLowering.h b/contrib/libs/llvm12/lib/Target/AArch64/AArch64ISelLowering.h
index 9550197159..535aa519f7 100644
--- a/contrib/libs/llvm12/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/contrib/libs/llvm12/lib/Target/AArch64/AArch64ISelLowering.h
@@ -72,51 +72,51 @@ enum NodeType : unsigned {
   ADC,
   SBC, // adc, sbc instructions
 
-  // Predicated instructions where inactive lanes produce undefined results.
+  // Predicated instructions where inactive lanes produce undefined results. 
   ADD_PRED,
   FADD_PRED,
-  FDIV_PRED,
-  FMA_PRED,
-  FMAXNM_PRED,
-  FMINNM_PRED,
-  FMUL_PRED,
-  FSUB_PRED,
-  MUL_PRED,
+  FDIV_PRED, 
+  FMA_PRED, 
+  FMAXNM_PRED, 
+  FMINNM_PRED, 
+  FMUL_PRED, 
+  FSUB_PRED, 
+  MUL_PRED, 
   SDIV_PRED,
-  SHL_PRED,
-  SMAX_PRED,
-  SMIN_PRED,
-  SRA_PRED,
-  SRL_PRED,
-  SUB_PRED,
+  SHL_PRED, 
+  SMAX_PRED, 
+  SMIN_PRED, 
+  SRA_PRED, 
+  SRL_PRED, 
+  SUB_PRED, 
   UDIV_PRED,
-  UMAX_PRED,
-  UMIN_PRED,
-
-  // Predicated instructions with the result of inactive lanes provided by the
-  // last operand.
-  FABS_MERGE_PASSTHRU,
-  FCEIL_MERGE_PASSTHRU,
-  FFLOOR_MERGE_PASSTHRU,
-  FNEARBYINT_MERGE_PASSTHRU,
-  FNEG_MERGE_PASSTHRU,
-  FRECPX_MERGE_PASSTHRU,
-  FRINT_MERGE_PASSTHRU,
-  FROUND_MERGE_PASSTHRU,
-  FROUNDEVEN_MERGE_PASSTHRU,
-  FSQRT_MERGE_PASSTHRU,
-  FTRUNC_MERGE_PASSTHRU,
-  FP_ROUND_MERGE_PASSTHRU,
-  FP_EXTEND_MERGE_PASSTHRU,
-  UINT_TO_FP_MERGE_PASSTHRU,
-  SINT_TO_FP_MERGE_PASSTHRU,
-  FCVTZU_MERGE_PASSTHRU,
-  FCVTZS_MERGE_PASSTHRU,
-  SIGN_EXTEND_INREG_MERGE_PASSTHRU,
-  ZERO_EXTEND_INREG_MERGE_PASSTHRU,
-  ABS_MERGE_PASSTHRU,
-  NEG_MERGE_PASSTHRU,
-
+  UMAX_PRED, 
+  UMIN_PRED, 
+
+  // Predicated instructions with the result of inactive lanes provided by the 
+  // last operand. 
+  FABS_MERGE_PASSTHRU, 
+  FCEIL_MERGE_PASSTHRU, 
+  FFLOOR_MERGE_PASSTHRU, 
+  FNEARBYINT_MERGE_PASSTHRU, 
+  FNEG_MERGE_PASSTHRU, 
+  FRECPX_MERGE_PASSTHRU, 
+  FRINT_MERGE_PASSTHRU, 
+  FROUND_MERGE_PASSTHRU, 
+  FROUNDEVEN_MERGE_PASSTHRU, 
+  FSQRT_MERGE_PASSTHRU, 
+  FTRUNC_MERGE_PASSTHRU, 
+  FP_ROUND_MERGE_PASSTHRU, 
+  FP_EXTEND_MERGE_PASSTHRU, 
+  UINT_TO_FP_MERGE_PASSTHRU, 
+  SINT_TO_FP_MERGE_PASSTHRU, 
+  FCVTZU_MERGE_PASSTHRU, 
+  FCVTZS_MERGE_PASSTHRU, 
+  SIGN_EXTEND_INREG_MERGE_PASSTHRU, 
+  ZERO_EXTEND_INREG_MERGE_PASSTHRU, 
+  ABS_MERGE_PASSTHRU, 
+  NEG_MERGE_PASSTHRU, 
+ 
   SETCC_MERGE_ZERO,
 
   // Arithmetic instructions which write flags.
@@ -219,18 +219,18 @@ enum NodeType : unsigned {
   SADDV,
   UADDV,
 
-  // Vector halving addition
-  SHADD,
-  UHADD,
-
+  // Vector halving addition 
+  SHADD, 
+  UHADD, 
+ 
   // Vector rounding halving addition
   SRHADD,
   URHADD,
 
-  // Absolute difference
-  UABD,
-  SABD,
-
+  // Absolute difference 
+  UABD, 
+  SABD, 
+ 
   // Vector across-lanes min/max
   // Only the lower result lane is defined.
   SMINV,
@@ -238,8 +238,8 @@ enum NodeType : unsigned {
   SMAXV,
   UMAXV,
 
-  SADDV_PRED,
-  UADDV_PRED,
+  SADDV_PRED, 
+  UADDV_PRED, 
   SMAXV_PRED,
   UMAXV_PRED,
   SMINV_PRED,
@@ -307,14 +307,14 @@ enum NodeType : unsigned {
   PTEST,
   PTRUE,
 
-  BITREVERSE_MERGE_PASSTHRU,
-  BSWAP_MERGE_PASSTHRU,
-  CTLZ_MERGE_PASSTHRU,
-  CTPOP_MERGE_PASSTHRU,
+  BITREVERSE_MERGE_PASSTHRU, 
+  BSWAP_MERGE_PASSTHRU, 
+  CTLZ_MERGE_PASSTHRU, 
+  CTPOP_MERGE_PASSTHRU, 
   DUP_MERGE_PASSTHRU,
   INDEX_VECTOR,
 
-  // Cast between vectors of the same element type but differ in length.
+  // Cast between vectors of the same element type but differ in length. 
   REINTERPRET_CAST,
 
   LD1_MERGE_ZERO,
@@ -424,11 +424,11 @@ enum NodeType : unsigned {
 
   LDP,
   STP,
-  STNP,
-
-  // Pseudo for a OBJC call that gets emitted together with a special `mov
-  // x29, x29` marker instruction.
-  CALL_RVMARKER
+  STNP, 
+ 
+  // Pseudo for a OBJC call that gets emitted together with a special `mov 
+  // x29, x29` marker instruction. 
+  CALL_RVMARKER 
 };
 
 } // end namespace AArch64ISD
@@ -438,14 +438,14 @@ namespace {
 // Any instruction that defines a 32-bit result zeros out the high half of the
 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
 // be copying from a truncate. But any other 32-bit operation will zero-extend
-// up to 64 bits. AssertSext/AssertZext aren't saying anything about the upper
-// 32 bits, they're probably just qualifying a CopyFromReg.
+// up to 64 bits. AssertSext/AssertZext aren't saying anything about the upper 
+// 32 bits, they're probably just qualifying a CopyFromReg. 
 // FIXME: X86 also checks for CMOV here. Do we need something similar?
 static inline bool isDef32(const SDNode &N) {
   unsigned Opc = N.getOpcode();
   return Opc != ISD::TRUNCATE && Opc != TargetOpcode::EXTRACT_SUBREG &&
-         Opc != ISD::CopyFromReg && Opc != ISD::AssertSext &&
-         Opc != ISD::AssertZext;
+         Opc != ISD::CopyFromReg && Opc != ISD::AssertSext && 
+         Opc != ISD::AssertZext; 
 }
 
 } // end anonymous namespace
@@ -784,7 +784,7 @@ public:
   /// illegal as the original, thus leading to an infinite legalisation loop.
   /// NOTE: Once BUILD_VECTOR is legal or can be custom lowered for all legal
   /// vector types this override can be removed.
-  bool mergeStoresAfterLegalization(EVT VT) const override;
+  bool mergeStoresAfterLegalization(EVT VT) const override; 
 
 private:
   /// Keep a pointer to the AArch64Subtarget around so that we can
@@ -815,11 +815,11 @@ private:
                           SDValue ThisVal) const;
 
   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
-  SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
-
-  SDValue LowerMGATHER(SDValue Op, SelectionDAG &DAG) const;
-  SDValue LowerMSCATTER(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const; 
 
+  SDValue LowerMGATHER(SDValue Op, SelectionDAG &DAG) const; 
+  SDValue LowerMSCATTER(SDValue Op, SelectionDAG &DAG) const; 
+ 
   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 
   bool isEligibleForTailCallOptimization(
@@ -903,28 +903,28 @@ private:
   SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerDUPQLane(SDValue Op, SelectionDAG &DAG) const;
-  SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, unsigned NewOp,
-                              bool OverrideNEON = false) const;
-  SDValue LowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, unsigned NewOp, 
+                              bool OverrideNEON = false) const; 
+  SDValue LowerToScalableOp(SDValue Op, SelectionDAG &DAG) const; 
   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
-  SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const;
-  SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const; 
+  SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 
   SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
-  SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const; 
   SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
-  SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 
   SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
-  SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const; 
   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVSCALE(SDValue Op, SelectionDAG &DAG) const;
@@ -939,17 +939,17 @@ private:
   SDValue LowerSVEStructLoad(unsigned Intrinsic, ArrayRef<SDValue> LoadOps,
                              EVT VT, SelectionDAG &DAG, const SDLoc &DL) const;
 
-  SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue Op,
-                                               SelectionDAG &DAG) const;
-  SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op,
-                                               SelectionDAG &DAG) const;
+  SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue Op, 
+                                               SelectionDAG &DAG) const; 
+  SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op, 
+                                               SelectionDAG &DAG) const; 
   SDValue LowerFixedLengthVectorLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
-  SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const;
-  SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG) const;
-  SDValue LowerReductionToSVE(unsigned Opcode, SDValue ScalarOp,
-                              SelectionDAG &DAG) const;
-  SDValue LowerFixedLengthVectorSelectToSVE(SDValue Op, SelectionDAG &DAG) const;
-  SDValue LowerFixedLengthVectorSetccToSVE(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const; 
+  SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG) const; 
+  SDValue LowerReductionToSVE(unsigned Opcode, SDValue ScalarOp, 
+                              SelectionDAG &DAG) const; 
+  SDValue LowerFixedLengthVectorSelectToSVE(SDValue Op, SelectionDAG &DAG) const; 
+  SDValue LowerFixedLengthVectorSetccToSVE(SDValue Op, SelectionDAG &DAG) const; 
   SDValue LowerFixedLengthVectorStoreToSVE(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFixedLengthVectorTruncateToSVE(SDValue Op,
                                               SelectionDAG &DAG) const;
@@ -961,10 +961,10 @@ private:
                           bool Reciprocal) const override;
   SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
                            int &ExtraSteps) const override;
-  SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
-                           const DenormalMode &Mode) const override;
-  SDValue getSqrtResultForDenormInput(SDValue Operand,
-                                      SelectionDAG &DAG) const override;
+  SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, 
+                           const DenormalMode &Mode) const override; 
+  SDValue getSqrtResultForDenormInput(SDValue Operand, 
+                                      SelectionDAG &DAG) const override; 
   unsigned combineRepeatedFPDivisors() const override;
 
   ConstraintType getConstraintType(StringRef Constraint) const override;
@@ -996,7 +996,7 @@ private:
     return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
   }
 
-  bool shouldRemoveExtendFromGSIndex(EVT VT) const override;
+  bool shouldRemoveExtendFromGSIndex(EVT VT) const override; 
   bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
   bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
   bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
@@ -1023,21 +1023,21 @@ private:
   bool shouldLocalize(const MachineInstr &MI,
                       const TargetTransformInfo *TTI) const override;
 
-  // Normally SVE is only used for byte size vectors that do not fit within a
-  // NEON vector. This changes when OverrideNEON is true, allowing SVE to be
-  // used for 64bit and 128bit vectors as well.
-  bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON = false) const;
-
-  // With the exception of data-predicate transitions, no instructions are
-  // required to cast between legal scalable vector types. However:
-  //  1. Packed and unpacked types have different bit lengths, meaning BITCAST
-  //     is not universally useable.
-  //  2. Most unpacked integer types are not legal and thus integer extends
-  //     cannot be used to convert between unpacked and packed types.
-  // These can make "bitcasting" a multiphase process. REINTERPRET_CAST is used
-  // to transition between unpacked and packed types of the same element type,
-  // with BITCAST used otherwise.
-  SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const;
+  // Normally SVE is only used for byte size vectors that do not fit within a 
+  // NEON vector. This changes when OverrideNEON is true, allowing SVE to be 
+  // used for 64bit and 128bit vectors as well. 
+  bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON = false) const; 
+ 
+  // With the exception of data-predicate transitions, no instructions are 
+  // required to cast between legal scalable vector types. However: 
+  //  1. Packed and unpacked types have different bit lengths, meaning BITCAST 
+  //     is not universally useable. 
+  //  2. Most unpacked integer types are not legal and thus integer extends 
+  //     cannot be used to convert between unpacked and packed types. 
+  // These can make "bitcasting" a multiphase process. REINTERPRET_CAST is used 
+  // to transition between unpacked and packed types of the same element type, 
+  // with BITCAST used otherwise. 
+  SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const; 
 };
 
 namespace AArch64 {