aboutsummaryrefslogtreecommitdiffstats
path: root/contrib/libs/llvm12/lib/CodeGen/RegAllocBasic.cpp
diff options
context:
space:
mode:
authorshadchin <shadchin@yandex-team.ru>2022-02-10 16:44:39 +0300
committerDaniil Cherednik <dcherednik@yandex-team.ru>2022-02-10 16:44:39 +0300
commite9656aae26e0358d5378e5b63dcac5c8dbe0e4d0 (patch)
tree64175d5cadab313b3e7039ebaa06c5bc3295e274 /contrib/libs/llvm12/lib/CodeGen/RegAllocBasic.cpp
parent2598ef1d0aee359b4b6d5fdd1758916d5907d04f (diff)
downloadydb-e9656aae26e0358d5378e5b63dcac5c8dbe0e4d0.tar.gz
Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 2 of 2.
Diffstat (limited to 'contrib/libs/llvm12/lib/CodeGen/RegAllocBasic.cpp')
-rw-r--r--contrib/libs/llvm12/lib/CodeGen/RegAllocBasic.cpp58
1 files changed, 29 insertions, 29 deletions
diff --git a/contrib/libs/llvm12/lib/CodeGen/RegAllocBasic.cpp b/contrib/libs/llvm12/lib/CodeGen/RegAllocBasic.cpp
index acff080e8d..8f2cb48c5d 100644
--- a/contrib/libs/llvm12/lib/CodeGen/RegAllocBasic.cpp
+++ b/contrib/libs/llvm12/lib/CodeGen/RegAllocBasic.cpp
@@ -46,7 +46,7 @@ static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
namespace {
struct CompSpillWeight {
bool operator()(LiveInterval *A, LiveInterval *B) const {
- return A->weight() < B->weight();
+ return A->weight() < B->weight();
}
};
}
@@ -72,8 +72,8 @@ class RABasic : public MachineFunctionPass,
// selectOrSplit().
BitVector UsableRegs;
- bool LRE_CanEraseVirtReg(Register) override;
- void LRE_WillShrinkVirtReg(Register) override;
+ bool LRE_CanEraseVirtReg(Register) override;
+ void LRE_WillShrinkVirtReg(Register) override;
public:
RABasic();
@@ -100,8 +100,8 @@ public:
return LI;
}
- MCRegister selectOrSplit(LiveInterval &VirtReg,
- SmallVectorImpl<Register> &SplitVRegs) override;
+ MCRegister selectOrSplit(LiveInterval &VirtReg,
+ SmallVectorImpl<Register> &SplitVRegs) override;
/// Perform register allocation.
bool runOnMachineFunction(MachineFunction &mf) override;
@@ -111,15 +111,15 @@ public:
MachineFunctionProperties::Property::NoPHIs);
}
- MachineFunctionProperties getClearedProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::IsSSA);
- }
-
+ MachineFunctionProperties getClearedProperties() const override {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::IsSSA);
+ }
+
// Helper for spilling all live virtual registers currently unified under preg
// that interfere with the most recently queried lvr. Return true if spilling
// was successful, and append any new spilled/split intervals to splitLVRs.
- bool spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg,
+ bool spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg,
SmallVectorImpl<Register> &SplitVRegs);
static char ID;
@@ -146,7 +146,7 @@ INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
INITIALIZE_PASS_END(RABasic, "regallocbasic", "Basic Register Allocator", false,
false)
-bool RABasic::LRE_CanEraseVirtReg(Register VirtReg) {
+bool RABasic::LRE_CanEraseVirtReg(Register VirtReg) {
LiveInterval &LI = LIS->getInterval(VirtReg);
if (VRM->hasPhys(VirtReg)) {
Matrix->unassign(LI);
@@ -161,7 +161,7 @@ bool RABasic::LRE_CanEraseVirtReg(Register VirtReg) {
return false;
}
-void RABasic::LRE_WillShrinkVirtReg(Register VirtReg) {
+void RABasic::LRE_WillShrinkVirtReg(Register VirtReg) {
if (!VRM->hasPhys(VirtReg))
return;
@@ -206,7 +206,7 @@ void RABasic::releaseMemory() {
// Spill or split all live virtual registers currently unified under PhysReg
// that interfere with VirtReg. The newly spilled or split live intervals are
// returned by appending them to SplitVRegs.
-bool RABasic::spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg,
+bool RABasic::spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg,
SmallVectorImpl<Register> &SplitVRegs) {
// Record each interference and determine if all are spillable before mutating
// either the union or live intervals.
@@ -218,7 +218,7 @@ bool RABasic::spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg,
Q.collectInterferingVRegs();
for (unsigned i = Q.interferingVRegs().size(); i; --i) {
LiveInterval *Intf = Q.interferingVRegs()[i - 1];
- if (!Intf->isSpillable() || Intf->weight() > VirtReg.weight())
+ if (!Intf->isSpillable() || Intf->weight() > VirtReg.weight())
return false;
Intfs.push_back(Intf);
}
@@ -232,7 +232,7 @@ bool RABasic::spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg,
LiveInterval &Spill = *Intfs[i];
// Skip duplicates.
- if (!VRM->hasPhys(Spill.reg()))
+ if (!VRM->hasPhys(Spill.reg()))
continue;
// Deallocate the interfering vreg by removing it from the union.
@@ -258,16 +258,16 @@ bool RABasic::spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg,
// |vregs| * |machineregs|. And since the number of interference tests is
// minimal, there is no value in caching them outside the scope of
// selectOrSplit().
-MCRegister RABasic::selectOrSplit(LiveInterval &VirtReg,
- SmallVectorImpl<Register> &SplitVRegs) {
+MCRegister RABasic::selectOrSplit(LiveInterval &VirtReg,
+ SmallVectorImpl<Register> &SplitVRegs) {
// Populate a list of physical register spill candidates.
- SmallVector<MCRegister, 8> PhysRegSpillCands;
+ SmallVector<MCRegister, 8> PhysRegSpillCands;
// Check for an available register in this class.
- auto Order =
- AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix);
- for (MCRegister PhysReg : Order) {
- assert(PhysReg.isValid());
+ auto Order =
+ AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix);
+ for (MCRegister PhysReg : Order) {
+ assert(PhysReg.isValid());
// Check for interference in PhysReg
switch (Matrix->checkInterference(VirtReg, PhysReg)) {
case LiveRegMatrix::IK_Free:
@@ -286,9 +286,9 @@ MCRegister RABasic::selectOrSplit(LiveInterval &VirtReg,
}
// Try to spill another interfering reg with less spill weight.
- for (auto PhysRegI = PhysRegSpillCands.begin(),
- PhysRegE = PhysRegSpillCands.end();
- PhysRegI != PhysRegE; ++PhysRegI) {
+ for (auto PhysRegI = PhysRegSpillCands.begin(),
+ PhysRegE = PhysRegSpillCands.end();
+ PhysRegI != PhysRegE; ++PhysRegI) {
if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs))
continue;
@@ -318,9 +318,9 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
RegAllocBase::init(getAnalysis<VirtRegMap>(),
getAnalysis<LiveIntervals>(),
getAnalysis<LiveRegMatrix>());
- VirtRegAuxInfo VRAI(*MF, *LIS, *VRM, getAnalysis<MachineLoopInfo>(),
- getAnalysis<MachineBlockFrequencyInfo>());
- VRAI.calculateSpillWeightsAndHints();
+ VirtRegAuxInfo VRAI(*MF, *LIS, *VRM, getAnalysis<MachineLoopInfo>(),
+ getAnalysis<MachineBlockFrequencyInfo>());
+ VRAI.calculateSpillWeightsAndHints();
SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));