Restoring authorship annotation for <orivej@yandex-team.ru>. Commit 2 of 2.

1 files changed, 48 insertions, 48 deletions

diff --git a/contrib/libs/llvm12/lib/CodeGen/AllocationOrder.h b/contrib/libs/llvm12/lib/CodeGen/AllocationOrder.h
index bd175390a9..0701e68101 100644
--- a/contrib/libs/llvm12/lib/CodeGen/AllocationOrder.h
+++ b/contrib/libs/llvm12/lib/CodeGen/AllocationOrder.h
@@ -1,35 +1,35 @@
-//===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===// 
-// 
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 
-// See https://llvm.org/LICENSE.txt for license information. 
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 
-// 
-//===----------------------------------------------------------------------===// 
-// 
-// This file implements an allocation order for virtual registers. 
-// 
-// The preferred allocation order for a virtual register depends on allocation 
-// hints and target hooks. The AllocationOrder class encapsulates all of that. 
-// 
-//===----------------------------------------------------------------------===// 
- 
-#ifndef LLVM_LIB_CODEGEN_ALLOCATIONORDER_H 
-#define LLVM_LIB_CODEGEN_ALLOCATIONORDER_H 
- 
-#include "llvm/ADT/ArrayRef.h" 
+//===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements an allocation order for virtual registers.
+//
+// The preferred allocation order for a virtual register depends on allocation
+// hints and target hooks. The AllocationOrder class encapsulates all of that.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_CODEGEN_ALLOCATIONORDER_H
+#define LLVM_LIB_CODEGEN_ALLOCATIONORDER_H
+
+#include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/SmallVector.h" 
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/Register.h"
- 
-namespace llvm { 
- 
-class RegisterClassInfo; 
-class VirtRegMap; 
-class LiveRegMatrix; 
- 
-class LLVM_LIBRARY_VISIBILITY AllocationOrder { 
+
+namespace llvm {
+
+class RegisterClassInfo;
+class VirtRegMap;
+class LiveRegMatrix;
+
+class LLVM_LIBRARY_VISIBILITY AllocationOrder {
   const SmallVector<MCPhysReg, 16> Hints;
-  ArrayRef<MCPhysReg> Order; 
+  ArrayRef<MCPhysReg> Order;
   // How far into the Order we can iterate. This is 0 if the AllocationOrder is
   // constructed with HardHints = true, Order.size() otherwise. While
   // technically a size_t, it will participate in comparisons with the
@@ -38,13 +38,13 @@ class LLVM_LIBRARY_VISIBILITY AllocationOrder {
   // relatively small.
   // IterationLimit defines an invalid iterator position.
   const int IterationLimit;
- 
-public: 
+
+public:
   /// Forward iterator for an AllocationOrder.
   class Iterator final {
     const AllocationOrder &AO;
     int Pos = 0;
- 
+
   public:
     Iterator(const AllocationOrder &AO, int Pos) : AO(AO), Pos(Pos) {}
 
@@ -77,25 +77,25 @@ public:
     bool operator!=(const Iterator &Other) const { return !(*this == Other); }
   };
 
-  /// Create a new AllocationOrder for VirtReg. 
-  /// @param VirtReg      Virtual register to allocate for. 
-  /// @param VRM          Virtual register map for function. 
-  /// @param RegClassInfo Information about reserved and allocatable registers. 
+  /// Create a new AllocationOrder for VirtReg.
+  /// @param VirtReg      Virtual register to allocate for.
+  /// @param VRM          Virtual register map for function.
+  /// @param RegClassInfo Information about reserved and allocatable registers.
   static AllocationOrder create(unsigned VirtReg, const VirtRegMap &VRM,
                                 const RegisterClassInfo &RegClassInfo,
                                 const LiveRegMatrix *Matrix);
- 
+
   /// Create an AllocationOrder given the Hits, Order, and HardHits values.
   /// Use the create method above - the ctor is for unittests.
   AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order,
                   bool HardHints)
       : Hints(std::move(Hints)), Order(Order),
         IterationLimit(HardHints ? 0 : static_cast<int>(Order.size())) {}
- 
+
   Iterator begin() const {
     return Iterator(*this, -(static_cast<int>(Hints.size())));
-  } 
- 
+  }
+
   Iterator end() const { return Iterator(*this, IterationLimit); }
 
   Iterator getOrderLimitEnd(unsigned OrderLimit) const {
@@ -105,11 +105,11 @@ public:
     Iterator Ret(*this,
                  std::min(static_cast<int>(OrderLimit) - 1, IterationLimit));
     return ++Ret;
-  } 
- 
+  }
+
   /// Get the allocation order without reordered hints.
   ArrayRef<MCPhysReg> getOrder() const { return Order; }
- 
+
   /// Return true if Reg is a preferred physical register.
   bool isHint(Register Reg) const {
     assert(!Reg.isPhysical() ||
@@ -117,8 +117,8 @@ public:
                static_cast<uint32_t>(std::numeric_limits<MCPhysReg>::max()));
     return Reg.isPhysical() && is_contained(Hints, Reg.id());
   }
-}; 
- 
-} // end namespace llvm 
- 
-#endif 
+};
+
+} // end namespace llvm
+
+#endif