Restoring authorship annotation for <heretic@yandex-team.ru>. Commit 2 of 2.

5 files changed, 4263 insertions, 4263 deletions

diff --git a/contrib/libs/llvm12/include/.yandex_meta/licenses.list.txt b/contrib/libs/llvm12/include/.yandex_meta/licenses.list.txt
index bea93831ea3..98869bcd43c 100644
--- a/contrib/libs/llvm12/include/.yandex_meta/licenses.list.txt
+++ b/contrib/libs/llvm12/include/.yandex_meta/licenses.list.txt
@@ -1,464 +1,464 @@
-====================Apache-2.0 WITH LLVM-exception==================== 
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 
- * See https://llvm.org/LICENSE.txt for license information. 
- 
- 
-====================Apache-2.0 WITH LLVM-exception==================== 
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 
- 
- 
-====================Apache-2.0 WITH LLVM-exception==================== 
-/* Part of the LLVM Project, under the Apache License v2.0 with LLVM          */ 
-/* Exceptions.                                                                */ 
-/* See https://llvm.org/LICENSE.txt for license information.                  */ 
- 
- 
-====================Apache-2.0 WITH LLVM-exception==================== 
-/* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception                    */ 
- 
- 
-====================Apache-2.0 WITH LLVM-exception==================== 
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 
-// See https://llvm.org/LICENSE.txt for license information. 
- 
- 
-====================Apache-2.0 WITH LLVM-exception==================== 
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 
- 
- 
-====================Apache-2.0 WITH LLVM-exception==================== 
-/// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 
-/// See https://llvm.org/LICENSE.txt for license information. 
- 
- 
-====================Apache-2.0 WITH LLVM-exception==================== 
-/// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 
- 
- 
-====================Apache-2.0 WITH LLVM-exception==================== 
-|* Part of the LLVM Project, under the Apache License v2.0 with LLVM          *| 
-|* Exceptions.                                                                *| 
-|* See https://llvm.org/LICENSE.txt for license information.                  *| 
- 
- 
-====================Apache-2.0 WITH LLVM-exception==================== 
-|* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 
-|* See https://llvm.org/LICENSE.txt for license information. 
- 
- 
-====================Apache-2.0 WITH LLVM-exception==================== 
-|* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 
- 
- 
-====================Apache-2.0 WITH LLVM-exception==================== 
-|* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception                    *| 
- 
- 
-====================BSD-2-Clause==================== 
-   BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) 
- 
- 
-====================BSD-2-Clause==================== 
-   Redistribution and use in source and binary forms, with or without 
-   modification, are permitted provided that the following conditions are 
-   met: 
- 
-       * Redistributions of source code must retain the above copyright 
-   notice, this list of conditions and the following disclaimer. 
-       * Redistributions in binary form must reproduce the above 
-   copyright notice, this list of conditions and the following disclaimer 
-   in the documentation and/or other materials provided with the 
-   distribution. 
- 
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 
-   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 
-   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 
-   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
- 
- 
-====================COPYRIGHT==================== 
-   Copyright (C) 2012-2016, Yann Collet. 
- 
- 
-====================COPYRIGHT==================== 
-  static bool isChar6(char C) { return isAlnum(C) || C == '.' || C == '_'; } 
-  static unsigned EncodeChar6(char C) { 
-    if (C >= 'a' && C <= 'z') return C-'a'; 
- 
- 
-====================COPYRIGHT==================== 
- * Copyright 2001-2004 Unicode, Inc. 
- 
- 
-====================COPYRIGHT==================== 
- * This software was written by Alexander Peslyak in 2001.  No copyright is 
- * claimed, and the software is hereby placed in the public domain. 
- * In case this attempt to disclaim copyright and place the software in the 
- * public domain is deemed null and void, then the software is 
- * Copyright (c) 2001 Alexander Peslyak and it is hereby released to the 
- * general public under the following terms: 
- 
- 
-====================COPYRIGHT==================== 
-//   if (c)                   if (c) 
-//     X1 = ...                 X1 = ... 
-//   else                     else 
- 
- 
-====================COPYRIGHT==================== 
-Copyright (c) 2004 eXtensible Systems, Inc. 
- 
-====================File: LICENSE.TXT==================== 
-============================================================================== 
-The LLVM Project is under the Apache License v2.0 with LLVM Exceptions: 
-============================================================================== 
- 
-                                 Apache License 
-                           Version 2.0, January 2004 
-                        http://www.apache.org/licenses/ 
- 
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-      direction or management of such entity, whether by contract or 
-      otherwise, or (ii) ownership of fifty percent (50%) or more of the 
-      outstanding shares, or (iii) beneficial ownership of such entity. 
- 
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-All rights reserved. 
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- 
- 
-====================File: include/llvm/Support/LICENSE.TXT==================== 
-LLVM System Interface Library 
-------------------------------------------------------------------------------- 
-The LLVM System Interface Library is licensed under the Illinois Open Source 
-License and has the following additional copyright: 
- 
-Copyright (C) 2004 eXtensible Systems, Inc. 
- 
- 
-====================NCSA==================== 
-// This file is distributed under the University of Illinois Open Source 
-// License. See LICENSE.TXT for details. 
- 
- 
-====================NCSA==================== 
-The LLVM System Interface Library is licensed under the Illinois Open Source 
- 
- 
-====================NCSA==================== 
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-License and has the following additional copyright: 
- 
- 
-====================Public-Domain==================== 
- * Homepage: 
- * http://openwall.info/wiki/people/solar/software/public-domain-source-code/md5 
- * 
- * Author: 
- * Alexander Peslyak, better known as Solar Designer <solar at openwall.com> 
- * 
- * This software was written by Alexander Peslyak in 2001.  No copyright is 
- * claimed, and the software is hereby placed in the public domain. 
- * In case this attempt to disclaim copyright and place the software in the 
- * public domain is deemed null and void, then the software is 
- * Copyright (c) 2001 Alexander Peslyak and it is hereby released to the 
- * general public under the following terms: 
- * 
- * Redistribution and use in source and binary forms, with or without 
- * modification, are permitted. 
- * 
- * There's ABSOLUTELY NO WARRANTY, express or implied. 
- 
- 
-====================Public-Domain==================== 
-// This code is taken from public domain 
- 
- 
-====================Unicode-Mappings==================== 
- * Disclaimer 
- * 
- * This source code is provided as is by Unicode, Inc. No claims are 
- * made as to fitness for any particular purpose. No warranties of any 
- * kind are expressed or implied. The recipient agrees to determine 
- * applicability of information provided. If this file has been 
- * purchased on magnetic or optical media from Unicode, Inc., the 
- * sole remedy for any claim will be exchange of defective media 
- * within 90 days of receipt. 
- * 
- * Limitations on Rights to Redistribute This Code 
- * 
- * Unicode, Inc. hereby grants the right to freely use the information 
- * supplied in this file in the creation of products supporting the 
- * Unicode Standard, and to make copies of this file in any form 
- * for internal or external distribution as long as this notice 
- * remains attached. 
+====================Apache-2.0 WITH LLVM-exception====================
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+
+
+====================Apache-2.0 WITH LLVM-exception====================
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+
+====================Apache-2.0 WITH LLVM-exception====================
+/* Part of the LLVM Project, under the Apache License v2.0 with LLVM          */
+/* Exceptions.                                                                */
+/* See https://llvm.org/LICENSE.txt for license information.                  */
+
+
+====================Apache-2.0 WITH LLVM-exception====================
+/* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception                    */
+
+
+====================Apache-2.0 WITH LLVM-exception====================
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+
+
+====================Apache-2.0 WITH LLVM-exception====================
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+
+====================Apache-2.0 WITH LLVM-exception====================
+/// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+/// See https://llvm.org/LICENSE.txt for license information.
+
+
+====================Apache-2.0 WITH LLVM-exception====================
+/// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+
+====================Apache-2.0 WITH LLVM-exception====================
+|* Part of the LLVM Project, under the Apache License v2.0 with LLVM          *|
+|* Exceptions.                                                                *|
+|* See https://llvm.org/LICENSE.txt for license information.                  *|
+
+
+====================Apache-2.0 WITH LLVM-exception====================
+|* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+|* See https://llvm.org/LICENSE.txt for license information.
+
+
+====================Apache-2.0 WITH LLVM-exception====================
+|* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+
+====================Apache-2.0 WITH LLVM-exception====================
+|* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception                    *|
+
+
+====================BSD-2-Clause====================
+   BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php)
+
+
+====================BSD-2-Clause====================
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are
+   met:
+
+       * Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+       * Redistributions in binary form must reproduce the above
+   copyright notice, this list of conditions and the following disclaimer
+   in the documentation and/or other materials provided with the
+   distribution.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+====================COPYRIGHT====================
+   Copyright (C) 2012-2016, Yann Collet.
+
+
+====================COPYRIGHT====================
+  static bool isChar6(char C) { return isAlnum(C) || C == '.' || C == '_'; }
+  static unsigned EncodeChar6(char C) {
+    if (C >= 'a' && C <= 'z') return C-'a';
+
+
+====================COPYRIGHT====================
+ * Copyright 2001-2004 Unicode, Inc.
+
+
+====================COPYRIGHT====================
+ * This software was written by Alexander Peslyak in 2001.  No copyright is
+ * claimed, and the software is hereby placed in the public domain.
+ * In case this attempt to disclaim copyright and place the software in the
+ * public domain is deemed null and void, then the software is
+ * Copyright (c) 2001 Alexander Peslyak and it is hereby released to the
+ * general public under the following terms:
+
+
+====================COPYRIGHT====================
+//   if (c)                   if (c)
+//     X1 = ...                 X1 = ...
+//   else                     else
+
+
+====================COPYRIGHT====================
+Copyright (c) 2004 eXtensible Systems, Inc.
+
+====================File: LICENSE.TXT====================
+==============================================================================
+The LLVM Project is under the Apache License v2.0 with LLVM Exceptions:
+==============================================================================
+
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+    TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+    1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
+      control with that entity. For the purposes of this definition,
+      "control" means (i) the power, direct or indirect, to cause the
+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+
+      "Object" form shall mean any form resulting from mechanical
+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+
+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
+      editorial revisions, annotations, elaborations, or other modifications
+      represent, as a whole, an original work of authorship. For the purposes
+      of this License, Derivative Works shall not include works that remain
+      separable from, or merely link (or bind by name) to the interfaces of,
+      the Work and Derivative Works thereof.
+
+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
+      to that Work or Derivative Works thereof, that is intentionally
+      submitted to Licensor for inclusion in the Work by the copyright owner
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+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+
+
+---- LLVM Exceptions to the Apache 2.0 License ----
+
+As an exception, if, as a result of your compiling your source code, portions
+of this Software are embedded into an Object form of such source code, you
+may redistribute such embedded portions in such Object form without complying
+with the conditions of Sections 4(a), 4(b) and 4(d) of the License.
+
+In addition, if you combine or link compiled forms of this Software with
+software that is licensed under the GPLv2 ("Combined Software") and if a
+court of competent jurisdiction determines that the patent provision (Section
+3), the indemnity provision (Section 9) or other Section of the License
+conflicts with the conditions of the GPLv2, you may retroactively and
+prospectively choose to deem waived or otherwise exclude such Section(s) of
+the License, but only in their entirety and only with respect to the Combined
+Software.
+
+==============================================================================
+Software from third parties included in the LLVM Project:
+==============================================================================
+The LLVM Project contains third party software which is under different license
+terms. All such code will be identified clearly using at least one of two
+mechanisms:
+1) It will be in a separate directory tree with its own `LICENSE.txt` or
+   `LICENSE` file at the top containing the specific license and restrictions
+   which apply to that software, or
+2) It will contain specific license and restriction terms at the top of every
+   file.
+
+==============================================================================
+Legacy LLVM License (https://llvm.org/docs/DeveloperPolicy.html#legacy):
+==============================================================================
+University of Illinois/NCSA
+Open Source License
+
+Copyright (c) 2003-2019 University of Illinois at Urbana-Champaign.
+All rights reserved.
+
+Developed by:
+
+    LLVM Team
+
+    University of Illinois at Urbana-Champaign
+
+    http://llvm.org
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal with
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimers.
+
+    * Redistributions in binary form must reproduce the above copyright notice,
+      this list of conditions and the following disclaimers in the
+      documentation and/or other materials provided with the distribution.
+
+    * Neither the names of the LLVM Team, University of Illinois at
+      Urbana-Champaign, nor the names of its contributors may be used to
+      endorse or promote products derived from this Software without specific
+      prior written permission.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+SOFTWARE.
+
+
+
+====================File: include/llvm/Support/LICENSE.TXT====================
+LLVM System Interface Library
+-------------------------------------------------------------------------------
+The LLVM System Interface Library is licensed under the Illinois Open Source
+License and has the following additional copyright:
+
+Copyright (C) 2004 eXtensible Systems, Inc.
+
+
+====================NCSA====================
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+
+
+====================NCSA====================
+The LLVM System Interface Library is licensed under the Illinois Open Source
+
+
+====================NCSA====================
+The LLVM System Interface Library is licensed under the Illinois Open Source
+License and has the following additional copyright:
+
+
+====================Public-Domain====================
+ * Homepage:
+ * http://openwall.info/wiki/people/solar/software/public-domain-source-code/md5
+ *
+ * Author:
+ * Alexander Peslyak, better known as Solar Designer <solar at openwall.com>
+ *
+ * This software was written by Alexander Peslyak in 2001.  No copyright is
+ * claimed, and the software is hereby placed in the public domain.
+ * In case this attempt to disclaim copyright and place the software in the
+ * public domain is deemed null and void, then the software is
+ * Copyright (c) 2001 Alexander Peslyak and it is hereby released to the
+ * general public under the following terms:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted.
+ *
+ * There's ABSOLUTELY NO WARRANTY, express or implied.
+
+
+====================Public-Domain====================
+// This code is taken from public domain
+
+
+====================Unicode-Mappings====================
+ * Disclaimer
+ *
+ * This source code is provided as is by Unicode, Inc. No claims are
+ * made as to fitness for any particular purpose. No warranties of any
+ * kind are expressed or implied. The recipient agrees to determine
+ * applicability of information provided. If this file has been
+ * purchased on magnetic or optical media from Unicode, Inc., the
+ * sole remedy for any claim will be exchange of defective media
+ * within 90 days of receipt.
+ *
+ * Limitations on Rights to Redistribute This Code
+ *
+ * Unicode, Inc. hereby grants the right to freely use the information
+ * supplied in this file in the creation of products supporting the
+ * Unicode Standard, and to make copies of this file in any form
+ * for internal or external distribution as long as this notice
+ * remains attached.
diff --git a/contrib/libs/llvm12/include/llvm/Config/config.h b/contrib/libs/llvm12/include/llvm/Config/config.h
index 009de507fe4..96f0524966e 100644
--- a/contrib/libs/llvm12/include/llvm/Config/config.h
+++ b/contrib/libs/llvm12/include/llvm/Config/config.h
@@ -1,15 +1,15 @@
 #pragma once
 
 #if defined(__ANDROID__)
-#   include "config-android.h" 
-#elif defined(__APPLE__) 
-#   include "config-osx.h" 
-#elif defined(_MSC_VER) 
-#   include "config-win.h" 
-#else 
-#   include "config-linux.h" 
+#   include "config-android.h"
+#elif defined(__APPLE__)
+#   include "config-osx.h"
+#elif defined(_MSC_VER)
+#   include "config-win.h"
+#else
+#   include "config-linux.h"
 #endif
 
 #if defined(_musl_)
-#   include "config-musl.h" 
+#   include "config-musl.h"
 #endif
diff --git a/contrib/libs/llvm12/include/llvm/Config/llvm-config.h b/contrib/libs/llvm12/include/llvm/Config/llvm-config.h
index c8ea05ad0d4..0ab964dcd1c 100644
--- a/contrib/libs/llvm12/include/llvm/Config/llvm-config.h
+++ b/contrib/libs/llvm12/include/llvm/Config/llvm-config.h
@@ -1,9 +1,9 @@
 #pragma once
 
 #if defined(__APPLE__)
-#   include "llvm-config-osx.h" 
-#elif defined(_MSC_VER) 
-#   include "llvm-config-win.h" 
-#else 
-#   include "llvm-config-linux.h" 
+#   include "llvm-config-osx.h"
+#elif defined(_MSC_VER)
+#   include "llvm-config-win.h"
+#else
+#   include "llvm-config-linux.h"
 #endif
diff --git a/contrib/libs/llvm12/include/llvm/Support/VirtualFileSystem.h b/contrib/libs/llvm12/include/llvm/Support/VirtualFileSystem.h
index e997d38422d..4729450b67f 100644
--- a/contrib/libs/llvm12/include/llvm/Support/VirtualFileSystem.h
+++ b/contrib/libs/llvm12/include/llvm/Support/VirtualFileSystem.h
@@ -26,7 +26,7 @@
 #include "llvm/ADT/Optional.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
-#include "llvm/ADT/StringMap.h" 
+#include "llvm/ADT/StringMap.h"
 #include "llvm/Support/Chrono.h"
 #include "llvm/Support/ErrorOr.h"
 #include "llvm/Support/FileSystem.h"
@@ -372,37 +372,37 @@ public:
   const_reverse_iterator overlays_rend() const { return FSList.end(); }
 };
 
-class CaseInsensitiveFileSystem : public FileSystem { 
-  IntrusiveRefCntPtr<FileSystem> Base; 
- 
-  /// Try to find Path by means of case-insensitive lookup. Stores the result in 
-  /// FoundPath on success, or returns an error code otherwise. 
-  std::error_code findCaseInsensitivePath(StringRef Path, 
-                                          SmallVectorImpl<char> &FoundPath); 
- 
-  /// Attempt to exclude the possibility that File exists in Dir based on 
-  /// previous information. 
-  bool exclude(StringRef Dir, StringRef File); 
- 
-  /// Map from directory to map from lowercase to real-case filename. 
-  llvm::StringMap<llvm::StringMap<std::string>> Maps; 
- 
-public: 
-  CaseInsensitiveFileSystem(IntrusiveRefCntPtr<FileSystem> Base) : Base(Base) {} 
- 
-  llvm::ErrorOr<Status> status(const Twine &Path) override; 
-  llvm::ErrorOr<std::unique_ptr<File>> 
-  openFileForRead(const Twine &Path) override; 
-  directory_iterator dir_begin(const Twine &Dir, std::error_code &EC) override; 
-  llvm::ErrorOr<std::string> getCurrentWorkingDirectory() const override { 
-    return Base->getCurrentWorkingDirectory(); 
-  } 
-  std::error_code setCurrentWorkingDirectory(const Twine &Path) override { 
-    Maps.clear(); 
-    return Base->setCurrentWorkingDirectory(Path); 
-  } 
-}; 
- 
+class CaseInsensitiveFileSystem : public FileSystem {
+  IntrusiveRefCntPtr<FileSystem> Base;
+
+  /// Try to find Path by means of case-insensitive lookup. Stores the result in
+  /// FoundPath on success, or returns an error code otherwise.
+  std::error_code findCaseInsensitivePath(StringRef Path,
+                                          SmallVectorImpl<char> &FoundPath);
+
+  /// Attempt to exclude the possibility that File exists in Dir based on
+  /// previous information.
+  bool exclude(StringRef Dir, StringRef File);
+
+  /// Map from directory to map from lowercase to real-case filename.
+  llvm::StringMap<llvm::StringMap<std::string>> Maps;
+
+public:
+  CaseInsensitiveFileSystem(IntrusiveRefCntPtr<FileSystem> Base) : Base(Base) {}
+
+  llvm::ErrorOr<Status> status(const Twine &Path) override;
+  llvm::ErrorOr<std::unique_ptr<File>>
+  openFileForRead(const Twine &Path) override;
+  directory_iterator dir_begin(const Twine &Dir, std::error_code &EC) override;
+  llvm::ErrorOr<std::string> getCurrentWorkingDirectory() const override {
+    return Base->getCurrentWorkingDirectory();
+  }
+  std::error_code setCurrentWorkingDirectory(const Twine &Path) override {
+    Maps.clear();
+    return Base->setCurrentWorkingDirectory(Path);
+  }
+};
+
 /// By default, this delegates all calls to the underlying file system. This
 /// is useful when derived file systems want to override some calls and still
 /// proxy other calls.
diff --git a/contrib/libs/llvm12/include/ya.make b/contrib/libs/llvm12/include/ya.make
index b3a3fe3f47c..649c0e4a89b 100644
--- a/contrib/libs/llvm12/include/ya.make
+++ b/contrib/libs/llvm12/include/ya.make
@@ -4,21 +4,21 @@ LIBRARY()
 
 PROVIDES(llvm)
 
-OWNER( 
-    orivej 
-    g:cpp-contrib 
-) 
-
-LICENSE( 
-    Apache-2.0 WITH LLVM-exception AND 
-    BSD-2-Clause AND 
-    NCSA AND 
-    Public-Domain AND 
-    Unicode-Mappings 
-) 
- 
-LICENSE_TEXTS(.yandex_meta/licenses.list.txt) 
- 
+OWNER(
+    orivej
+    g:cpp-contrib
+)
+
+LICENSE(
+    Apache-2.0 WITH LLVM-exception AND
+    BSD-2-Clause AND
+    NCSA AND
+    Public-Domain AND
+    Unicode-Mappings
+)
+
+LICENSE_TEXTS(.yandex_meta/licenses.list.txt)
+
 PEERDIR(
     contrib/libs/llvm12
 )
@@ -26,10 +26,10 @@ PEERDIR(
 NO_UTIL()
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen --gen-directive-decl -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/Frontend/OpenACC -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/Frontend/OpenACC/ACC.td --write-if-changed -o 
-        llvm/Frontend/OpenACC/ACC.h.inc -d llvm/Frontend/OpenACC/ACC.h.inc.d 
+    contrib/libs/llvm12/utils/TableGen --gen-directive-decl -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/Frontend/OpenACC -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/Frontend/OpenACC/ACC.td --write-if-changed -o
+        llvm/Frontend/OpenACC/ACC.h.inc -d llvm/Frontend/OpenACC/ACC.h.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
     IN llvm/Frontend/Directive/DirectiveBase.td llvm/Frontend/OpenACC/ACC.td
     OUTPUT_INCLUDES llvm/ADT/BitmaskEnum.h
@@ -37,10 +37,10 @@ RUN_PROGRAM(
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen --gen-directive-decl -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/Frontend/OpenMP -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/Frontend/OpenMP/OMP.td --write-if-changed -o 
-        llvm/Frontend/OpenMP/OMP.h.inc -d llvm/Frontend/OpenMP/OMP.h.inc.d 
+    contrib/libs/llvm12/utils/TableGen --gen-directive-decl -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/Frontend/OpenMP -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/Frontend/OpenMP/OMP.td --write-if-changed -o
+        llvm/Frontend/OpenMP/OMP.h.inc -d llvm/Frontend/OpenMP/OMP.h.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
     IN llvm/Frontend/Directive/DirectiveBase.td llvm/Frontend/OpenMP/OMP.td
     OUTPUT_INCLUDES llvm/ADT/BitmaskEnum.h
@@ -48,3922 +48,3922 @@ RUN_PROGRAM(
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-attrs -I ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Attributes.td --write-if-changed -o 
-        llvm/IR/Attributes.inc -d llvm/IR/Attributes.inc.d 
+    contrib/libs/llvm12/utils/TableGen -gen-attrs -I ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Attributes.td --write-if-changed -o
+        llvm/IR/Attributes.inc -d llvm/IR/Attributes.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
     IN llvm/IR/Attributes.td
     OUT_NOAUTO llvm/IR/Attributes.inc llvm/IR/Attributes.inc.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicEnums.inc -d llvm/IR/IntrinsicEnums.inc.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicEnums.inc -d llvm/IR/IntrinsicEnums.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicEnums.inc llvm/IR/IntrinsicEnums.inc.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-impl -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicImpl.inc -d llvm/IR/IntrinsicImpl.inc.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-impl -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicImpl.inc -d llvm/IR/IntrinsicImpl.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicImpl.inc llvm/IR/IntrinsicImpl.inc.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=aarch64 -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicsAArch64.h -d llvm/IR/IntrinsicsAArch64.h.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=aarch64 -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicsAArch64.h -d llvm/IR/IntrinsicsAArch64.h.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicsAArch64.h llvm/IR/IntrinsicsAArch64.h.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=amdgcn -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicsAMDGPU.h -d llvm/IR/IntrinsicsAMDGPU.h.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=amdgcn -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicsAMDGPU.h -d llvm/IR/IntrinsicsAMDGPU.h.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicsAMDGPU.h llvm/IR/IntrinsicsAMDGPU.h.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=arm -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicsARM.h -d llvm/IR/IntrinsicsARM.h.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=arm -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicsARM.h -d llvm/IR/IntrinsicsARM.h.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicsARM.h llvm/IR/IntrinsicsARM.h.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=bpf -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicsBPF.h -d llvm/IR/IntrinsicsBPF.h.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=bpf -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicsBPF.h -d llvm/IR/IntrinsicsBPF.h.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicsBPF.h llvm/IR/IntrinsicsBPF.h.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=hexagon -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicsHexagon.h -d llvm/IR/IntrinsicsHexagon.h.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=hexagon -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicsHexagon.h -d llvm/IR/IntrinsicsHexagon.h.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicsHexagon.h llvm/IR/IntrinsicsHexagon.h.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=mips -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicsMips.h -d llvm/IR/IntrinsicsMips.h.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=mips -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicsMips.h -d llvm/IR/IntrinsicsMips.h.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicsMips.h llvm/IR/IntrinsicsMips.h.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=nvvm -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicsNVPTX.h -d llvm/IR/IntrinsicsNVPTX.h.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=nvvm -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicsNVPTX.h -d llvm/IR/IntrinsicsNVPTX.h.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicsNVPTX.h llvm/IR/IntrinsicsNVPTX.h.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=ppc -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicsPowerPC.h -d llvm/IR/IntrinsicsPowerPC.h.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=ppc -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicsPowerPC.h -d llvm/IR/IntrinsicsPowerPC.h.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicsPowerPC.h llvm/IR/IntrinsicsPowerPC.h.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=r600 -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicsR600.h -d llvm/IR/IntrinsicsR600.h.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=r600 -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicsR600.h -d llvm/IR/IntrinsicsR600.h.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicsR600.h llvm/IR/IntrinsicsR600.h.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=riscv -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicsRISCV.h -d llvm/IR/IntrinsicsRISCV.h.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=riscv -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicsRISCV.h -d llvm/IR/IntrinsicsRISCV.h.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicsRISCV.h llvm/IR/IntrinsicsRISCV.h.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=s390 -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicsS390.h -d llvm/IR/IntrinsicsS390.h.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=s390 -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicsS390.h -d llvm/IR/IntrinsicsS390.h.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicsS390.h llvm/IR/IntrinsicsS390.h.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=ve -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicsVE.h -d llvm/IR/IntrinsicsVE.h.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=ve -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicsVE.h -d llvm/IR/IntrinsicsVE.h.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicsVE.h llvm/IR/IntrinsicsVE.h.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=wasm -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicsWebAssembly.h -d llvm/IR/IntrinsicsWebAssembly.h.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=wasm -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicsWebAssembly.h -d llvm/IR/IntrinsicsWebAssembly.h.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicsWebAssembly.h llvm/IR/IntrinsicsWebAssembly.h.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=x86 -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicsX86.h -d llvm/IR/IntrinsicsX86.h.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=x86 -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicsX86.h -d llvm/IR/IntrinsicsX86.h.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicsX86.h llvm/IR/IntrinsicsX86.h.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=xcore -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o 
-        llvm/IR/IntrinsicsXCore.h -d llvm/IR/IntrinsicsXCore.h.d 
+    contrib/libs/llvm12/utils/TableGen -gen-intrinsic-enums -intrinsic-prefix=xcore -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/include/llvm/IR -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/IR/Intrinsics.td --write-if-changed -o
+        llvm/IR/IntrinsicsXCore.h -d llvm/IR/IntrinsicsXCore.h.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td 
-        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td 
-        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td 
-        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td 
-        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td 
-        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td 
-        llvm/IR/IntrinsicsXCore.td 
+    IN llvm/CodeGen/SDNodeProperties.td llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td
+        llvm/IR/IntrinsicsAArch64.td llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td
+        llvm/IR/IntrinsicsBPF.td llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td
+        llvm/IR/IntrinsicsMips.td llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td
+        llvm/IR/IntrinsicsRISCV.td llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td
+        llvm/IR/IntrinsicsVEVL.gen.td llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td
+        llvm/IR/IntrinsicsXCore.td
     OUT_NOAUTO llvm/IR/IntrinsicsXCore.h llvm/IR/IntrinsicsXCore.h.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen --gen-directive-impl -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenACC -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/Frontend/OpenACC/ACC.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenACC/ACC.cpp -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenACC/ACC.cpp.d 
+    contrib/libs/llvm12/utils/TableGen --gen-directive-impl -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenACC -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/Frontend/OpenACC/ACC.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenACC/ACC.cpp -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenACC/ACC.cpp.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
     IN llvm/Frontend/Directive/DirectiveBase.td llvm/Frontend/OpenACC/ACC.td
-    OUTPUT_INCLUDES llvm/ADT/StringRef.h llvm/ADT/StringSwitch.h llvm/Frontend/OpenACC/ACC.h.inc 
-        llvm/Support/ErrorHandling.h 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenACC/ACC.cpp 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenACC/ACC.cpp.d 
+    OUTPUT_INCLUDES llvm/ADT/StringRef.h llvm/ADT/StringSwitch.h llvm/Frontend/OpenACC/ACC.h.inc
+        llvm/Support/ErrorHandling.h
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenACC/ACC.cpp
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenACC/ACC.cpp.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen --gen-directive-impl -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenMP -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/Frontend/OpenMP/OMP.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenMP/OMP.cpp -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenMP/OMP.cpp.d 
+    contrib/libs/llvm12/utils/TableGen --gen-directive-impl -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenMP -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include llvm/Frontend/OpenMP/OMP.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenMP/OMP.cpp -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenMP/OMP.cpp.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
     IN llvm/Frontend/Directive/DirectiveBase.td llvm/Frontend/OpenMP/OMP.td
-    OUTPUT_INCLUDES llvm/ADT/StringRef.h llvm/ADT/StringSwitch.h llvm/Frontend/OpenMP/OMP.h.inc 
-        llvm/Support/ErrorHandling.h 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenMP/OMP.cpp 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenMP/OMP.cpp.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-matcher -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmMatcher.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmMatcher.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUTPUT_INCLUDES llvm/ADT/StringRef.h llvm/ADT/StringSwitch.h llvm/Frontend/OpenMP/OMP.h.inc
+        llvm/Support/ErrorHandling.h
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenMP/OMP.cpp
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Frontend/OpenMP/OMP.cpp.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-asm-matcher -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmMatcher.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmMatcher.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmMatcher.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmMatcher.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -asmwriternum=1 -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter1.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter1.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter1.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter1.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-callingconv -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenCallingConv.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenCallingConv.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenCallingConv.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenCallingConv.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDAGISel.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDAGISel.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDAGISel.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDAGISel.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-disassembler -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDisassemblerTables.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDisassemblerTables.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/Support/DataTypes.h llvm/Support/Debug.h 
-        llvm/Support/LEB128.h llvm/Support/raw_ostream.h 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDisassemblerTables.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDisassemblerTables.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-exegesis -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenExegesis.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenExegesis.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenExegesis.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenExegesis.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-fast-isel -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenFastISel.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenFastISel.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenFastISel.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenFastISel.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-global-isel -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenGlobalISel.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenGlobalISel.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenGlobalISel.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenGlobalISel.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenInstrInfo.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenInstrInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenInstrInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenInstrInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmMatcher.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmMatcher.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -asmwriternum=1 -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter1.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter1.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter1.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenAsmWriter1.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-callingconv -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenCallingConv.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenCallingConv.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenCallingConv.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenCallingConv.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDAGISel.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDAGISel.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDAGISel.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDAGISel.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-disassembler -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDisassemblerTables.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDisassemblerTables.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/Support/DataTypes.h llvm/Support/Debug.h
+        llvm/Support/LEB128.h llvm/Support/raw_ostream.h
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDisassemblerTables.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenDisassemblerTables.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-exegesis -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenExegesis.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenExegesis.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenExegesis.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenExegesis.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-fast-isel -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenFastISel.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenFastISel.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenFastISel.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenFastISel.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-global-isel -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenGlobalISel.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenGlobalISel.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenGlobalISel.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenGlobalISel.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenInstrInfo.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenInstrInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenInstrInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenInstrInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES _llvm_sstream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-pseudo-lowering -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-global-isel-combiner -combiners=AArch64PostLegalizerCombinerHelper 
-        -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-pseudo-lowering -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-global-isel-combiner -combiners=AArch64PostLegalizerCombinerHelper
+        -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/ADT/SparseBitVector.h
-    OUT_NOAUTO 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-global-isel-combiner -combiners=AArch64PostLegalizerLoweringHelper 
-        -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-global-isel-combiner -combiners=AArch64PostLegalizerLoweringHelper
+        -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/ADT/SparseBitVector.h
-    OUT_NOAUTO 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-global-isel-combiner -combiners=AArch64PreLegalizerCombinerHelper 
-        -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-global-isel-combiner -combiners=AArch64PreLegalizerCombinerHelper
+        -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/ADT/SparseBitVector.h
-    OUT_NOAUTO 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-bank -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterBank.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterBank.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterBank.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterBank.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-info -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterInfo.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-register-bank -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterBank.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterBank.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterBank.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterBank.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-register-info -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterInfo.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSubtargetInfo.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSubtargetInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenRegisterInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSubtargetInfo.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSubtargetInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSubtargetInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSubtargetInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-searchable-tables -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSystemOperands.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSystemOperands.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td 
-        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td 
-        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td 
-        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td 
-        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td 
-        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td 
-        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSystemOperands.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSystemOperands.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-matcher -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmMatcher.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmMatcher.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSubtargetInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSubtargetInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-searchable-tables -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/AArch64 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSystemOperands.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSystemOperands.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/AArch64/AArch64.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64CallingConvention.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Combine.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrAtomics.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrFormats.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrGISel.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64InstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64PfmCounters.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SVEInstrInfo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA53.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA55.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedA64FX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedCyclone.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM3.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM4.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedExynosM5.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkor.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryo.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedKryoDetails.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredExynos.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedTSV110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64Schedule.td
+        contrib/libs/llvm12/lib/Target/AArch64/AArch64SystemOperands.td
+        contrib/libs/llvm12/lib/Target/AArch64/SVEInstrFormats.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/Combine.td
+        llvm/Target/GlobalISel/RegisterBank.td llvm/Target/GlobalISel/SelectionDAGCompat.td
+        llvm/Target/GlobalISel/Target.td llvm/Target/Target.td llvm/Target/TargetCallingConv.td
+        llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td llvm/Target/TargetPfmCounters.td
+        llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSystemOperands.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/AArch64/AArch64GenSystemOperands.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-asm-matcher -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmMatcher.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmMatcher.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmMatcher.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmMatcher.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmWriter.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmWriter.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmWriter.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmWriter.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-callingconv -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenCallingConv.inc 
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenCallingConv.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenCallingConv.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenCallingConv.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments 
-        contrib/libs/llvm12/lib/Target/ARM/ARM.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDAGISel.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDAGISel.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDAGISel.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDAGISel.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-disassembler -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td 
-        --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDisassemblerTables.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDisassemblerTables.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/Support/DataTypes.h llvm/Support/Debug.h 
-        llvm/Support/LEB128.h llvm/Support/raw_ostream.h 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDisassemblerTables.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDisassemblerTables.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-fast-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenFastISel.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenFastISel.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenFastISel.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenFastISel.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-global-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenGlobalISel.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenGlobalISel.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenGlobalISel.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenGlobalISel.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenInstrInfo.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenInstrInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenInstrInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenInstrInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCCodeEmitter.inc 
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCCodeEmitter.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmMatcher.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmMatcher.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmWriter.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmWriter.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmWriter.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenAsmWriter.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-callingconv -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenCallingConv.inc
+        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenCallingConv.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenCallingConv.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenCallingConv.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments
+        contrib/libs/llvm12/lib/Target/ARM/ARM.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDAGISel.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDAGISel.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDAGISel.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDAGISel.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-disassembler -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
+        --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDisassemblerTables.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDisassemblerTables.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/Support/DataTypes.h llvm/Support/Debug.h
+        llvm/Support/LEB128.h llvm/Support/raw_ostream.h
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDisassemblerTables.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenDisassemblerTables.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-fast-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenFastISel.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenFastISel.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenFastISel.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenFastISel.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-global-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenGlobalISel.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenGlobalISel.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenGlobalISel.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenGlobalISel.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenInstrInfo.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenInstrInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenInstrInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenInstrInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCCodeEmitter.inc
+        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCCodeEmitter.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES _llvm_sstream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCCodeEmitter.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCCodeEmitter.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-pseudo-lowering -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/ARM/ARM.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCPseudoLowering.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCPseudoLowering.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCPseudoLowering.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCPseudoLowering.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-bank -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/ARM/ARM.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterBank.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterBank.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterBank.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterBank.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-info -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/ARM/ARM.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterInfo.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCCodeEmitter.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCCodeEmitter.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-pseudo-lowering -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/ARM/ARM.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCPseudoLowering.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCPseudoLowering.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCPseudoLowering.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenMCPseudoLowering.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-register-bank -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/ARM/ARM.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterBank.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterBank.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterBank.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterBank.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-register-info -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/ARM/ARM.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterInfo.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSubtargetInfo.inc 
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSubtargetInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenRegisterInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/ARM/ARM.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSubtargetInfo.inc
+        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSubtargetInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSubtargetInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSubtargetInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-searchable-tables -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/ARM/ARM.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSystemRegister.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSystemRegister.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td 
-        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSystemRegister.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSystemRegister.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-matcher -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmMatcher.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmMatcher.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSubtargetInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSubtargetInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-searchable-tables -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/ARM -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/ARM/ARM.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSystemRegister.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSystemRegister.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/ARM/ARM.td contrib/libs/llvm12/lib/Target/ARM/ARMCallingConv.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrCDE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrFormats.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrInfo.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrMVE.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrNEON.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMInstrThumb2.td contrib/libs/llvm12/lib/Target/ARM/ARMInstrVFP.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMPredicates.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSchedule.td contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA57WriteRes.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA8.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleA9.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM4.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleM7.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleR52.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleSwift.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMScheduleV6.td
+        contrib/libs/llvm12/lib/Target/ARM/ARMSystemRegister.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/TableGen/SearchableTable.td llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSystemRegister.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/ARM/ARMGenSystemRegister.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-asm-matcher -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmMatcher.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmMatcher.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmMatcher.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmMatcher.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmWriter.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmWriter.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmWriter.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmWriter.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-callingconv -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenCallingConv.inc 
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenCallingConv.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenCallingConv.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenCallingConv.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments 
-        contrib/libs/llvm12/lib/Target/BPF/BPF.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDAGISel.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDAGISel.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDAGISel.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDAGISel.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-disassembler -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td 
-        --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDisassemblerTables.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDisassemblerTables.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/Support/DataTypes.h llvm/Support/Debug.h 
-        llvm/Support/LEB128.h llvm/Support/raw_ostream.h 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDisassemblerTables.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDisassemblerTables.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenInstrInfo.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenInstrInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenInstrInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenInstrInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenMCCodeEmitter.inc 
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenMCCodeEmitter.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmMatcher.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmMatcher.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmWriter.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmWriter.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmWriter.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenAsmWriter.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-callingconv -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenCallingConv.inc
+        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenCallingConv.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenCallingConv.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenCallingConv.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments
+        contrib/libs/llvm12/lib/Target/BPF/BPF.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDAGISel.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDAGISel.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDAGISel.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDAGISel.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-disassembler -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td
+        --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDisassemblerTables.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDisassemblerTables.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/Support/DataTypes.h llvm/Support/Debug.h
+        llvm/Support/LEB128.h llvm/Support/raw_ostream.h
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDisassemblerTables.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenDisassemblerTables.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenInstrInfo.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenInstrInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenInstrInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenInstrInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenMCCodeEmitter.inc
+        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenMCCodeEmitter.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES _llvm_sstream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenMCCodeEmitter.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenMCCodeEmitter.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-info -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/BPF/BPF.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenRegisterInfo.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenRegisterInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenMCCodeEmitter.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenMCCodeEmitter.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-register-info -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/BPF/BPF.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenRegisterInfo.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenRegisterInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenRegisterInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenRegisterInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenSubtargetInfo.inc 
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenSubtargetInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenRegisterInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenRegisterInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/BPF
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/BPF/BPF.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenSubtargetInfo.inc
+        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenSubtargetInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/BPF/BPF.td contrib/libs/llvm12/lib/Target/BPF/BPFCallingConv.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrFormats.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFInstrInfo.td
+        contrib/libs/llvm12/lib/Target/BPF/BPFRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenSubtargetInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenSubtargetInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenAsmWriter.inc 
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenAsmWriter.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXIntrinsics.td 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenAsmWriter.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenAsmWriter.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenDAGISel.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenDAGISel.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXIntrinsics.td 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenDAGISel.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenDAGISel.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenInstrInfo.inc 
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenInstrInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXIntrinsics.td 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenInstrInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenInstrInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-info -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXIntrinsics.td 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenSubtargetInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/BPF/BPFGenSubtargetInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenAsmWriter.inc
+        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenAsmWriter.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrFormats.td
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrInfo.td
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXIntrinsics.td
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenAsmWriter.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenAsmWriter.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenDAGISel.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenDAGISel.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrFormats.td
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrInfo.td
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXIntrinsics.td
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenDAGISel.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenDAGISel.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenInstrInfo.inc
+        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenInstrInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrFormats.td
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrInfo.td
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXIntrinsics.td
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenInstrInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenInstrInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-register-info -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrFormats.td
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrInfo.td
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXIntrinsics.td
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td 
-        --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXIntrinsics.td 
-        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td
+        --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/NVPTX/NVPTX.td contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrFormats.td
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXInstrInfo.td
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXIntrinsics.td
+        contrib/libs/llvm12/lib/Target/NVPTX/NVPTXRegisterInfo.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-matcher -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmMatcher.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmMatcher.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-asm-matcher -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmMatcher.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmMatcher.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmMatcher.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmMatcher.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmWriter.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmWriter.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmWriter.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmWriter.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-callingconv -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenCallingConv.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenCallingConv.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenCallingConv.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenCallingConv.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDAGISel.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDAGISel.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDAGISel.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDAGISel.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-disassembler -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDisassemblerTables.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDisassemblerTables.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/Support/DataTypes.h llvm/Support/Debug.h 
-        llvm/Support/LEB128.h llvm/Support/raw_ostream.h 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDisassemblerTables.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDisassemblerTables.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-exegesis -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/PowerPC/PPC.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenExegesis.inc 
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenExegesis.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenExegesis.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenExegesis.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-fast-isel -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenFastISel.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenFastISel.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenFastISel.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenFastISel.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-global-isel -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenGlobalISel.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenGlobalISel.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenGlobalISel.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenGlobalISel.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenInstrInfo.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenInstrInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenInstrInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenInstrInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/PowerPC/PPC.td 
-        --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmMatcher.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmMatcher.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmWriter.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmWriter.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmWriter.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenAsmWriter.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-callingconv -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenCallingConv.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenCallingConv.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenCallingConv.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenCallingConv.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDAGISel.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDAGISel.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDAGISel.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDAGISel.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-disassembler -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDisassemblerTables.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDisassemblerTables.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUTPUT_INCLUDES assert.h llvm/MC/MCInst.h llvm/Support/DataTypes.h llvm/Support/Debug.h
+        llvm/Support/LEB128.h llvm/Support/raw_ostream.h
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDisassemblerTables.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenDisassemblerTables.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-exegesis -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/PowerPC/PPC.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenExegesis.inc
+        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenExegesis.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenExegesis.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenExegesis.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-fast-isel -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenFastISel.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenFastISel.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenFastISel.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenFastISel.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-global-isel -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenGlobalISel.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenGlobalISel.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenGlobalISel.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenGlobalISel.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenInstrInfo.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenInstrInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenInstrInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenInstrInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-emitter -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/PowerPC/PPC.td
+        --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES _llvm_sstream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-bank -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterBank.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterBank.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterBank.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterBank.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-info -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterInfo.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-register-bank -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterBank.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterBank.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterBank.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterBank.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-register-info -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterInfo.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenSubtargetInfo.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenSubtargetInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td 
-        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenRegisterInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenSubtargetInfo.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenSubtargetInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+        contrib/libs/llvm12/lib/Target/PowerPC/P9InstrResources.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPC.td contrib/libs/llvm12/lib/Target/PowerPC/PPCCallingConv.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstr64Bit.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrAltivec.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrFormats.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrHTM.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrPrefix.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrSPE.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCInstrVSX.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCPfmCounters.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCRegisterInfo.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCSchedule440.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleA2.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE500mc.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleE5500.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG3.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG4Plus.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleG5.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP7.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP8.td
+        contrib/libs/llvm12/lib/Target/PowerPC/PPCScheduleP9.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenSubtargetInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenSubtargetInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-matcher -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmMatcher.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmMatcher.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenSubtargetInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/PowerPC/PPCGenSubtargetInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-asm-matcher -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmMatcher.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmMatcher.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
+        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
+        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/Support/Debug.h llvm/Support/Format.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmMatcher.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmMatcher.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -asmwriternum=1 -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/X86/X86.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter1.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter1.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter1.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter1.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-callingconv -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenCallingConv.inc 
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenCallingConv.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenCallingConv.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenCallingConv.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments 
-        contrib/libs/llvm12/lib/Target/X86/X86.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDAGISel.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDAGISel.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDAGISel.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDAGISel.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-disassembler -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td 
-        --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDisassemblerTables.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDisassemblerTables.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDisassemblerTables.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDisassemblerTables.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-x86-EVEX2VEX-tables -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/X86/X86.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenEVEX2VEXTables.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenEVEX2VEXTables.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenEVEX2VEXTables.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenEVEX2VEXTables.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-exegesis -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenExegesis.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenExegesis.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenExegesis.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenExegesis.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-fast-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenFastISel.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenFastISel.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenFastISel.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenFastISel.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-global-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenGlobalISel.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenGlobalISel.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenGlobalISel.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenGlobalISel.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenInstrInfo.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenInstrInfo.inc.d 
-        --long-string-literals=0 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenInstrInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenInstrInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-bank -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/X86/X86.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterBank.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterBank.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterBank.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterBank.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-register-info -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target 
-        contrib/libs/llvm12/lib/Target/X86/X86.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterInfo.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmMatcher.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmMatcher.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
+        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
+        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-asm-writer -asmwriternum=1 -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/X86/X86.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter1.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter1.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
+        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
+        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter1.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenAsmWriter1.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-callingconv -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenCallingConv.inc
+        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenCallingConv.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
+        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
+        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenCallingConv.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenCallingConv.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-dag-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target -omit-comments
+        contrib/libs/llvm12/lib/Target/X86/X86.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDAGISel.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDAGISel.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
+        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
+        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDAGISel.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDAGISel.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-disassembler -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
+        --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDisassemblerTables.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDisassemblerTables.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
+        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
+        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDisassemblerTables.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenDisassemblerTables.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-x86-EVEX2VEX-tables -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/X86/X86.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenEVEX2VEXTables.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenEVEX2VEXTables.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
+        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
+        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenEVEX2VEXTables.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenEVEX2VEXTables.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-exegesis -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenExegesis.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenExegesis.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
+        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
+        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenExegesis.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenExegesis.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-fast-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenFastISel.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenFastISel.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
+        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
+        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenFastISel.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenFastISel.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-global-isel -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenGlobalISel.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenGlobalISel.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
+        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
+        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenGlobalISel.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenGlobalISel.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-instr-info -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenInstrInfo.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenInstrInfo.inc.d
+        --long-string-literals=0
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
+        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
+        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenInstrInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenInstrInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-register-bank -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/X86/X86.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterBank.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterBank.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
+        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
+        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterBank.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterBank.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-register-info -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target
+        contrib/libs/llvm12/lib/Target/X86/X86.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterInfo.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
+        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
+        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/CodeGen/TargetRegisterInfo.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterInfo.inc.d 
-)
-
-RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86 
-        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenSubtargetInfo.inc 
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenSubtargetInfo.inc.d 
-    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td 
-        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td 
-        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td 
-        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td 
-        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td 
-        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td 
-        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td 
-        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td 
-        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td 
-        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td 
-        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td 
-        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td 
-        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td 
-        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td 
-        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td 
-        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenRegisterInfo.inc.d
+)
+
+RUN_PROGRAM(
+    contrib/libs/llvm12/utils/TableGen -gen-subtarget -I ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target/X86
+        -Iinclude -I${ARCADIA_ROOT}/contrib/libs/llvm12/include -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/Target contrib/libs/llvm12/lib/Target/X86/X86.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenSubtargetInfo.inc
+        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenSubtargetInfo.inc.d
+    CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
+    IN contrib/libs/llvm12/lib/Target/X86/X86.td contrib/libs/llvm12/lib/Target/X86/X86CallingConv.td
+        contrib/libs/llvm12/lib/Target/X86/X86Instr3DNow.td contrib/libs/llvm12/lib/Target/X86/X86InstrAMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrAVX512.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrArithmetic.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCMovSetCC.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrControl.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrExtension.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFMA.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFPStack.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFormats.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrFragmentsSIMD.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrInfo.td contrib/libs/llvm12/lib/Target/X86/X86InstrKL.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrMMX.td contrib/libs/llvm12/lib/Target/X86/X86InstrMPX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSGX.td contrib/libs/llvm12/lib/Target/X86/X86InstrSNP.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSSE.td contrib/libs/llvm12/lib/Target/X86/X86InstrSVM.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrShiftRotate.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrSystem.td contrib/libs/llvm12/lib/Target/X86/X86InstrTDX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrTSX.td contrib/libs/llvm12/lib/Target/X86/X86InstrVMX.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrVecCompiler.td
+        contrib/libs/llvm12/lib/Target/X86/X86InstrXOP.td contrib/libs/llvm12/lib/Target/X86/X86PfmCounters.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterBanks.td
+        contrib/libs/llvm12/lib/Target/X86/X86RegisterInfo.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedBroadwell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedHaswell.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedPredicates.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSandyBridge.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeClient.td
+        contrib/libs/llvm12/lib/Target/X86/X86SchedSkylakeServer.td
+        contrib/libs/llvm12/lib/Target/X86/X86Schedule.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleAtom.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBdVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleBtVer2.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleSLM.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver1.td
+        contrib/libs/llvm12/lib/Target/X86/X86ScheduleZnver2.td llvm/CodeGen/SDNodeProperties.td
+        llvm/CodeGen/ValueTypes.td llvm/IR/Intrinsics.td llvm/IR/IntrinsicsAArch64.td
+        llvm/IR/IntrinsicsAMDGPU.td llvm/IR/IntrinsicsARM.td llvm/IR/IntrinsicsBPF.td
+        llvm/IR/IntrinsicsHexagon.td llvm/IR/IntrinsicsHexagonDep.td llvm/IR/IntrinsicsMips.td
+        llvm/IR/IntrinsicsNVVM.td llvm/IR/IntrinsicsPowerPC.td llvm/IR/IntrinsicsRISCV.td
+        llvm/IR/IntrinsicsSystemZ.td llvm/IR/IntrinsicsVE.td llvm/IR/IntrinsicsVEVL.gen.td
+        llvm/IR/IntrinsicsWebAssembly.td llvm/IR/IntrinsicsX86.td llvm/IR/IntrinsicsXCore.td
+        llvm/Target/GenericOpcodes.td llvm/Target/GlobalISel/RegisterBank.td
+        llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/Target/GlobalISel/Target.td llvm/Target/Target.td
+        llvm/Target/TargetCallingConv.td llvm/Target/TargetInstrPredicate.td llvm/Target/TargetItinerary.td
+        llvm/Target/TargetPfmCounters.td llvm/Target/TargetSchedule.td llvm/Target/TargetSelectionDAG.td
     OUTPUT_INCLUDES llvm/CodeGen/TargetSchedule.h llvm/Support/Debug.h llvm/Support/raw_ostream.h
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenSubtargetInfo.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenSubtargetInfo.inc.d 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenSubtargetInfo.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/Target/X86/X86GenSubtargetInfo.inc.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include 
-        contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.inc.d 
+    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include
+        contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
     IN contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.inc.d 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-dlltool/Options.inc.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-lib -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.inc 
-        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.inc.d 
+    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-lib -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.inc
+        -d ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
     IN contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.inc.d 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/lib/ToolDrivers/llvm-lib/Options.inc.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/dsymutil -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/dsymutil/Options.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/dsymutil/Options.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/dsymutil/Options.inc.d 
+    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/dsymutil -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/dsymutil/Options.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/dsymutil/Options.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/dsymutil/Options.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
     IN contrib/libs/llvm12/tools/dsymutil/Options.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/dsymutil/Options.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/dsymutil/Options.inc.d 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/dsymutil/Options.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/dsymutil/Options.inc.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-cvtres -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-cvtres/Opts.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-cvtres/Opts.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-cvtres/Opts.inc.d 
+    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-cvtres -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-cvtres/Opts.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-cvtres/Opts.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-cvtres/Opts.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
     IN contrib/libs/llvm12/tools/llvm-cvtres/Opts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-cvtres/Opts.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-cvtres/Opts.inc.d 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-cvtres/Opts.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-cvtres/Opts.inc.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-lipo -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.inc.d 
+    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-lipo -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
     IN contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.inc.d 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-lipo/LipoOpts.inc.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-ml -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-ml/Opts.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-ml/Opts.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-ml/Opts.inc.d 
+    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-ml -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-ml/Opts.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-ml/Opts.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-ml/Opts.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
     IN contrib/libs/llvm12/tools/llvm-ml/Opts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-ml/Opts.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-ml/Opts.inc.d 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-ml/Opts.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-ml/Opts.inc.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-mt -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-mt/Opts.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-mt/Opts.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-mt/Opts.inc.d 
+    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-mt -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-mt/Opts.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-mt/Opts.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-mt/Opts.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
     IN contrib/libs/llvm12/tools/llvm-mt/Opts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-mt/Opts.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-mt/Opts.inc.d 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-mt/Opts.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-mt/Opts.inc.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include 
-        contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.inc.d 
+    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include
+        contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
     IN contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.inc.d 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/BitcodeStripOpts.inc.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include 
-        contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.td --write-if-changed -o 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.inc.d 
+    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include
+        contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.td --write-if-changed -o
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
     IN contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.inc.d 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/InstallNameToolOpts.inc.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.inc.d 
+    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/tools/llvm-objcopy/CommonOpts.td 
-        contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.td llvm/Option/OptParser.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.inc.d 
+    IN contrib/libs/llvm12/tools/llvm-objcopy/CommonOpts.td
+        contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.td llvm/Option/OptParser.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/ObjcopyOpts.inc.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.inc.d 
+    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
-    IN contrib/libs/llvm12/tools/llvm-objcopy/CommonOpts.td 
-        contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.td llvm/Option/OptParser.td 
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.inc.d 
+    IN contrib/libs/llvm12/tools/llvm-objcopy/CommonOpts.td
+        contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.td llvm/Option/OptParser.td
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-objcopy/StripOpts.inc.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-rc -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-rc/Opts.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-rc/Opts.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-rc/Opts.inc.d 
+    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-rc -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-rc/Opts.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-rc/Opts.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-rc/Opts.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
     IN contrib/libs/llvm12/tools/llvm-rc/Opts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-rc/Opts.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-rc/Opts.inc.d 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-rc/Opts.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-rc/Opts.inc.d
 )
 
 RUN_PROGRAM(
-    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I 
-        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-symbolizer -Iinclude 
-        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-symbolizer/Opts.td 
-        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-symbolizer/Opts.inc -d 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-symbolizer/Opts.inc.d 
+    contrib/libs/llvm12/utils/TableGen -gen-opt-parser-defs -I
+        ${ARCADIA_ROOT}/contrib/libs/llvm12/tools/llvm-symbolizer -Iinclude
+        -I${ARCADIA_ROOT}/contrib/libs/llvm12/include contrib/libs/llvm12/tools/llvm-symbolizer/Opts.td
+        --write-if-changed -o ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-symbolizer/Opts.inc -d
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-symbolizer/Opts.inc.d
     CWD ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12
     IN contrib/libs/llvm12/tools/llvm-symbolizer/Opts.td llvm/Option/OptParser.td
-    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-symbolizer/Opts.inc 
-        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-symbolizer/Opts.inc.d 
+    OUT_NOAUTO ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-symbolizer/Opts.inc
+        ${ARCADIA_BUILD_ROOT}/contrib/libs/llvm12/tools/llvm-symbolizer/Opts.inc.d
 )
 
 END()