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author | shadchin <shadchin@yandex-team.ru> | 2022-02-10 16:44:30 +0300 |
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committer | Daniil Cherednik <dcherednik@yandex-team.ru> | 2022-02-10 16:44:30 +0300 |
commit | 2598ef1d0aee359b4b6d5fdd1758916d5907d04f (patch) | |
tree | 012bb94d777798f1f56ac1cec429509766d05181 /contrib/libs/llvm12/include/llvm/Target/TargetInstrPredicate.td | |
parent | 6751af0b0c1b952fede40b19b71da8025b5d8bcf (diff) | |
download | ydb-2598ef1d0aee359b4b6d5fdd1758916d5907d04f.tar.gz |
Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 1 of 2.
Diffstat (limited to 'contrib/libs/llvm12/include/llvm/Target/TargetInstrPredicate.td')
-rw-r--r-- | contrib/libs/llvm12/include/llvm/Target/TargetInstrPredicate.td | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/contrib/libs/llvm12/include/llvm/Target/TargetInstrPredicate.td b/contrib/libs/llvm12/include/llvm/Target/TargetInstrPredicate.td index 9f2cde9d92..04022cf45b 100644 --- a/contrib/libs/llvm12/include/llvm/Target/TargetInstrPredicate.td +++ b/contrib/libs/llvm12/include/llvm/Target/TargetInstrPredicate.td @@ -11,7 +11,7 @@ // MCInstPredicate definitions are used by target scheduling models to describe // constraints on instructions. // -// Here is an example of an MCInstPredicate definition in TableGen: +// Here is an example of an MCInstPredicate definition in TableGen: // // def MCInstPredicateExample : CheckAll<[ // CheckOpcode<[BLR]>, @@ -126,11 +126,11 @@ class CheckRegOperand<int Index, Register R> : CheckOperandBase<Index> { // Check if register operand at index `Index` is the invalid register. class CheckInvalidRegOperand<int Index> : CheckOperandBase<Index>; -// Return true if machine operand at position `Index` is a valid -// register operand. -class CheckValidRegOperand<int Index> : - CheckNot<CheckInvalidRegOperand<Index>>; - +// Return true if machine operand at position `Index` is a valid +// register operand. +class CheckValidRegOperand<int Index> : + CheckNot<CheckInvalidRegOperand<Index>>; + // Check that the operand at position `Index` is immediate `Imm`. // If field `FunctionMapper` is a non-empty string, then function // `FunctionMapper` is applied to the operand value, and the return value is then @@ -259,20 +259,20 @@ class CheckFunctionPredicate<string MCInstFn, string MachineInstrFn> : MCInstPre string MachineInstrFnName = MachineInstrFn; } -// Similar to CheckFunctionPredicate. However it assumes that MachineInstrFn is -// a method in TargetInstrInfo, and MCInstrFn takes an extra pointer to -// MCInstrInfo. -// -// It Expands to: -// - TIIPointer->MachineInstrFn(MI) -// - MCInstrFn(MI, MCII); -class CheckFunctionPredicateWithTII<string MCInstFn, string MachineInstrFn, string -TIIPointer = "TII"> : MCInstPredicate { - string MCInstFnName = MCInstFn; - string TIIPtrName = TIIPointer; - string MachineInstrFnName = MachineInstrFn; -} - +// Similar to CheckFunctionPredicate. However it assumes that MachineInstrFn is +// a method in TargetInstrInfo, and MCInstrFn takes an extra pointer to +// MCInstrInfo. +// +// It Expands to: +// - TIIPointer->MachineInstrFn(MI) +// - MCInstrFn(MI, MCII); +class CheckFunctionPredicateWithTII<string MCInstFn, string MachineInstrFn, string +TIIPointer = "TII"> : MCInstPredicate { + string MCInstFnName = MCInstFn; + string TIIPtrName = TIIPointer; + string MachineInstrFnName = MachineInstrFn; +} + // Used to classify machine instructions based on a machine instruction // predicate. // @@ -319,8 +319,8 @@ class DepBreakingClass<list<Instruction> opcodes, MCInstPredicate pred, // - A list of subtarget hooks (Delegates) that are called from this function. // class STIPredicateDecl<string name, MCInstPredicate default = FalsePred, - bit overrides = true, bit expandForMC = true, - bit updatesOpcodeMask = false, + bit overrides = true, bit expandForMC = true, + bit updatesOpcodeMask = false, list<STIPredicateDecl> delegates = []> { string Name = name; @@ -355,7 +355,7 @@ class STIPredicate<STIPredicateDecl declaration, // Convenience classes and definitions used by processor scheduling models to // describe dependency breaking instructions and move elimination candidates. -let UpdatesOpcodeMask = true in { +let UpdatesOpcodeMask = true in { def IsZeroIdiomDecl : STIPredicateDecl<"isZeroIdiom">; |