Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 1 of 2.

1 files changed, 211 insertions, 211 deletions

diff --git a/contrib/libs/llvm12/include/llvm/Target/Target.td b/contrib/libs/llvm12/include/llvm/Target/Target.td
index 1c97d70a47..0261df6fb2 100644
--- a/contrib/libs/llvm12/include/llvm/Target/Target.td
+++ b/contrib/libs/llvm12/include/llvm/Target/Target.td
@@ -110,9 +110,9 @@ class SubRegIndex<int size, int offset = 0> {
 // ComposedSubRegIndex - A sub-register that is the result of composing A and B.
 // Offset is set to the sum of A and B's Offsets. Size is set to B's Size.
 class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
-  : SubRegIndex<B.Size, !cond(!eq(A.Offset, -1): -1,
-                              !eq(B.Offset, -1): -1,
-                              true:              !add(A.Offset, B.Offset))> {
+  : SubRegIndex<B.Size, !cond(!eq(A.Offset, -1): -1, 
+                              !eq(B.Offset, -1): -1, 
+                              true:              !add(A.Offset, B.Offset))> { 
   // See SubRegIndex.
   let ComposedOf = [A, B];
 }
@@ -175,12 +175,12 @@ class Register<string n, list<string> altNames = []> {
   // completely determined by the value of its sub-registers.  For example, the
   // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
   // covered by its sub-register AX.
-  bit CoveredBySubRegs = false;
+  bit CoveredBySubRegs = false; 
 
   // HWEncoding - The target specific hardware encoding for this register.
   bits<16> HWEncoding = 0;
 
-  bit isArtificial = false;
+  bit isArtificial = false; 
 }
 
 // RegisterWithSubRegs - This can be used to define instances of Register which
@@ -252,7 +252,7 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
   // isAllocatable - Specify that the register class can be used for virtual
   // registers and register allocation.  Some register classes are only used to
   // model instruction operand constraints, and should have isAllocatable = 0.
-  bit isAllocatable = true;
+  bit isAllocatable = true; 
 
   // AltOrders - List of alternative allocation orders. The default order is
   // MemberList itself, and that is good enough for most targets since the
@@ -278,7 +278,7 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
 
   // Generate register pressure set for this register class and any class
   // synthesized from it. Set to 0 to inhibit unneeded pressure sets.
-  bit GeneratePressureSet = true;
+  bit GeneratePressureSet = true; 
 
   // Weight override for register pressure calculation. This is the value
   // TargetRegisterClass::getRegClassWeight() will return. The weight is in
@@ -452,7 +452,7 @@ class InstructionEncoding {
   // DecodeInstB() is not able to determine if all possible values of ?? are
   // valid or not. If DecodeInstB() returns Fail the decoder will attempt to
   // decode the bitpattern as InstA too.
-  bit hasCompleteDecoder = true;
+  bit hasCompleteDecoder = true; 
 }
 
 // Allows specifying an InstructionEncoding by HwMode. If an Instruction specifies
@@ -506,59 +506,59 @@ class Instruction : InstructionEncoding {
 
   // Indicates if this is a pre-isel opcode that should be
   // legalized/regbankselected/selected.
-  bit isPreISelOpcode = false;
+  bit isPreISelOpcode = false; 
 
   // These bits capture information about the high-level semantics of the
   // instruction.
-  bit isReturn     = false;     // Is this instruction a return instruction?
-  bit isBranch     = false;     // Is this instruction a branch instruction?
-  bit isEHScopeReturn = false;  // Does this instruction end an EH scope?
-  bit isIndirectBranch = false; // Is this instruction an indirect branch?
-  bit isCompare    = false;     // Is this instruction a comparison instruction?
-  bit isMoveImm    = false;     // Is this instruction a move immediate instruction?
-  bit isMoveReg    = false;     // Is this instruction a move register instruction?
-  bit isBitcast    = false;     // Is this instruction a bitcast instruction?
-  bit isSelect     = false;     // Is this instruction a select instruction?
-  bit isBarrier    = false;     // Can control flow fall through this instruction?
-  bit isCall       = false;     // Is this instruction a call instruction?
-  bit isAdd        = false;     // Is this instruction an add instruction?
-  bit isTrap       = false;     // Is this instruction a trap instruction?
-  bit canFoldAsLoad = false;    // Can this be folded as a simple memory operand?
-  bit mayLoad      = ?;         // Is it possible for this inst to read memory?
-  bit mayStore     = ?;         // Is it possible for this inst to write memory?
-  bit mayRaiseFPException = false; // Can this raise a floating-point exception?
-  bit isConvertibleToThreeAddress = false;  // Can this 2-addr instruction promote?
-  bit isCommutable = false;     // Is this 3 operand instruction commutable?
-  bit isTerminator = false;     // Is this part of the terminator for a basic block?
-  bit isReMaterializable = false; // Is this instruction re-materializable?
-  bit isPredicable = false;     // 1 means this instruction is predicable
-                                // even if it does not have any operand
-                                // tablegen can identify as a predicate
-  bit isUnpredicable = false;   // 1 means this instruction is not predicable
-                                // even if it _does_ have a predicate operand
-  bit hasDelaySlot = false;     // Does this instruction have an delay slot?
-  bit usesCustomInserter = false; // Pseudo instr needing special help.
-  bit hasPostISelHook = false;  // To be *adjusted* after isel by target hook.
-  bit hasCtrlDep   = false;     // Does this instruction r/w ctrl-flow chains?
-  bit isNotDuplicable = false;  // Is it unsafe to duplicate this instruction?
-  bit isConvergent = false;     // Is this instruction convergent?
-  bit isAuthenticated = false;  // Does this instruction authenticate a pointer?
-  bit isAsCheapAsAMove = false; // As cheap (or cheaper) than a move instruction.
-  bit hasExtraSrcRegAllocReq = false; // Sources have special regalloc requirement?
-  bit hasExtraDefRegAllocReq = false; // Defs have special regalloc requirement?
-  bit isRegSequence = false;    // Is this instruction a kind of reg sequence?
-                                // If so, make sure to override
-                                // TargetInstrInfo::getRegSequenceLikeInputs.
-  bit isPseudo     = false;     // Is this instruction a pseudo-instruction?
-                                // If so, won't have encoding information for
-                                // the [MC]CodeEmitter stuff.
-  bit isExtractSubreg = false;  // Is this instruction a kind of extract subreg?
-                                // If so, make sure to override
-                                // TargetInstrInfo::getExtractSubregLikeInputs.
-  bit isInsertSubreg = false;   // Is this instruction a kind of insert subreg?
-                                // If so, make sure to override
-                                // TargetInstrInfo::getInsertSubregLikeInputs.
-  bit variadicOpsAreDefs = false; // Are variadic operands definitions?
+  bit isReturn     = false;     // Is this instruction a return instruction? 
+  bit isBranch     = false;     // Is this instruction a branch instruction? 
+  bit isEHScopeReturn = false;  // Does this instruction end an EH scope? 
+  bit isIndirectBranch = false; // Is this instruction an indirect branch? 
+  bit isCompare    = false;     // Is this instruction a comparison instruction? 
+  bit isMoveImm    = false;     // Is this instruction a move immediate instruction? 
+  bit isMoveReg    = false;     // Is this instruction a move register instruction? 
+  bit isBitcast    = false;     // Is this instruction a bitcast instruction? 
+  bit isSelect     = false;     // Is this instruction a select instruction? 
+  bit isBarrier    = false;     // Can control flow fall through this instruction? 
+  bit isCall       = false;     // Is this instruction a call instruction? 
+  bit isAdd        = false;     // Is this instruction an add instruction? 
+  bit isTrap       = false;     // Is this instruction a trap instruction? 
+  bit canFoldAsLoad = false;    // Can this be folded as a simple memory operand? 
+  bit mayLoad      = ?;         // Is it possible for this inst to read memory? 
+  bit mayStore     = ?;         // Is it possible for this inst to write memory? 
+  bit mayRaiseFPException = false; // Can this raise a floating-point exception? 
+  bit isConvertibleToThreeAddress = false;  // Can this 2-addr instruction promote? 
+  bit isCommutable = false;     // Is this 3 operand instruction commutable? 
+  bit isTerminator = false;     // Is this part of the terminator for a basic block? 
+  bit isReMaterializable = false; // Is this instruction re-materializable? 
+  bit isPredicable = false;     // 1 means this instruction is predicable 
+                                // even if it does not have any operand 
+                                // tablegen can identify as a predicate 
+  bit isUnpredicable = false;   // 1 means this instruction is not predicable 
+                                // even if it _does_ have a predicate operand 
+  bit hasDelaySlot = false;     // Does this instruction have an delay slot? 
+  bit usesCustomInserter = false; // Pseudo instr needing special help. 
+  bit hasPostISelHook = false;  // To be *adjusted* after isel by target hook. 
+  bit hasCtrlDep   = false;     // Does this instruction r/w ctrl-flow chains? 
+  bit isNotDuplicable = false;  // Is it unsafe to duplicate this instruction? 
+  bit isConvergent = false;     // Is this instruction convergent? 
+  bit isAuthenticated = false;  // Does this instruction authenticate a pointer? 
+  bit isAsCheapAsAMove = false; // As cheap (or cheaper) than a move instruction. 
+  bit hasExtraSrcRegAllocReq = false; // Sources have special regalloc requirement? 
+  bit hasExtraDefRegAllocReq = false; // Defs have special regalloc requirement? 
+  bit isRegSequence = false;    // Is this instruction a kind of reg sequence? 
+                                // If so, make sure to override 
+                                // TargetInstrInfo::getRegSequenceLikeInputs. 
+  bit isPseudo     = false;     // Is this instruction a pseudo-instruction? 
+                                // If so, won't have encoding information for 
+                                // the [MC]CodeEmitter stuff. 
+  bit isExtractSubreg = false;  // Is this instruction a kind of extract subreg? 
+                                // If so, make sure to override 
+                                // TargetInstrInfo::getExtractSubregLikeInputs. 
+  bit isInsertSubreg = false;   // Is this instruction a kind of insert subreg? 
+                                // If so, make sure to override 
+                                // TargetInstrInfo::getInsertSubregLikeInputs. 
+  bit variadicOpsAreDefs = false; // Are variadic operands definitions? 
 
   // Does the instruction have side effects that are not captured by any
   // operands of the instruction or other flags?
@@ -581,15 +581,15 @@ class Instruction : InstructionEncoding {
   //   CodeEmitter unchanged, but duplicates a canonical instruction
   //   definition's encoding and should be ignored when constructing the
   //   assembler match tables.
-  bit isCodeGenOnly = false;
+  bit isCodeGenOnly = false; 
 
   // Is this instruction a pseudo instruction for use by the assembler parser.
-  bit isAsmParserOnly = false;
+  bit isAsmParserOnly = false; 
 
   // This instruction is not expected to be queried for scheduling latencies
   // and therefore needs no scheduling information even for a complete
   // scheduling model.
-  bit hasNoSchedulingInfo = false;
+  bit hasNoSchedulingInfo = false; 
 
   InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
 
@@ -630,13 +630,13 @@ class Instruction : InstructionEncoding {
   /// UseNamedOperandTable - If set, the operand indices of this instruction
   /// can be queried via the getNamedOperandIdx() function which is generated
   /// by TableGen.
-  bit UseNamedOperandTable = false;
+  bit UseNamedOperandTable = false; 
 
   /// Should FastISel ignore this instruction. For certain ISAs, they have
   /// instructions which map to the same ISD Opcode, value type operands and
   /// instruction selection predicates. FastISel cannot handle such cases, but
   /// SelectionDAG can.
-  bit FastISelShouldIgnore = false;
+  bit FastISelShouldIgnore = false; 
 }
 
 /// Defines an additional encoding that disassembles to the given instruction
@@ -651,7 +651,7 @@ class AdditionalEncoding<Instruction I> : InstructionEncoding {
 /// pseudo.
 class PseudoInstExpansion<dag Result> {
   dag ResultInst = Result;     // The instruction to generate.
-  bit isPseudo = true;
+  bit isPseudo = true; 
 }
 
 /// Predicates - These are extra conditionals which are turned into instruction
@@ -662,7 +662,7 @@ class Predicate<string cond> {
   /// AssemblerMatcherPredicate - If this feature can be used by the assembler
   /// matcher, this is true.  Targets should set this by inheriting their
   /// feature from the AssemblerPredicate class in addition to Predicate.
-  bit AssemblerMatcherPredicate = false;
+  bit AssemblerMatcherPredicate = false; 
 
   /// AssemblerCondDag - Set of subtarget features being tested used
   /// as alternative condition string used for assembler matcher. Must be used
@@ -688,7 +688,7 @@ class Predicate<string cond> {
   /// every function change. Most predicates can leave this at '0'.
   ///
   /// Ignored by SelectionDAG, it always recomputes the predicate on every use.
-  bit RecomputePerFunction = false;
+  bit RecomputePerFunction = false; 
 }
 
 /// NoHonorSignDependentRounding - This predicate is true if support for
@@ -788,7 +788,7 @@ class AsmOperandClass {
   /// marked as IsOptional.
   ///
   /// Optional arguments must be at the end of the operand list.
-  bit IsOptional = false;
+  bit IsOptional = false; 
 
   /// The name of the method on the target specific asm parser that returns the
   /// default operand for this optional operand. This method is only used if
@@ -809,7 +809,7 @@ class Operand<ValueType ty> : DAGOperand {
   ValueType Type = ty;
   string PrintMethod = "printOperand";
   string EncoderMethod = "";
-  bit hasCompleteDecoder = true;
+  bit hasCompleteDecoder = true; 
   string OperandType = "OPERAND_UNKNOWN";
   dag MIOperandInfo = (ops);
 
@@ -877,8 +877,8 @@ def f64imm : Operand<f64>;
 // have the same LLT).
 class TypedOperand<string Ty> : Operand<untyped> {
   let OperandType = Ty;
-  bit IsPointer = false;
-  bit IsImmediate = false;
+  bit IsPointer = false; 
+  bit IsImmediate = false; 
 }
 
 def type0 : TypedOperand<"OPERAND_GENERIC_0">;
@@ -888,7 +888,7 @@ def type3 : TypedOperand<"OPERAND_GENERIC_3">;
 def type4 : TypedOperand<"OPERAND_GENERIC_4">;
 def type5 : TypedOperand<"OPERAND_GENERIC_5">;
 
-let IsPointer = true in {
+let IsPointer = true in { 
   def ptype0 : TypedOperand<"OPERAND_GENERIC_0">;
   def ptype1 : TypedOperand<"OPERAND_GENERIC_1">;
   def ptype2 : TypedOperand<"OPERAND_GENERIC_2">;
@@ -900,7 +900,7 @@ let IsPointer = true in {
 // untyped_imm is for operands where isImm() will be true. It currently has no
 // special behaviour and is only used for clarity.
 def untyped_imm_0 : TypedOperand<"OPERAND_GENERIC_IMM_0"> {
-  let IsImmediate = true;
+  let IsImmediate = true; 
 }
 
 /// zero_reg definition - Special node to stand for the zero register.
@@ -952,7 +952,7 @@ class InstrInfo {
   // For instance, while both Sparc and PowerPC are big-endian platforms, the
   // Sparc manual specifies its instructions in the format [31..0] (big), while
   // PowerPC specifies them using the format [0..31] (little).
-  bit isLittleEndianEncoding = false;
+  bit isLittleEndianEncoding = false; 
 
   // The instruction properties mayLoad, mayStore, and hasSideEffects are unset
   // by default, and TableGen will infer their value from the instruction
@@ -963,7 +963,7 @@ class InstrInfo {
   // is set, it will guess a safe value instead.
   //
   // This option is a temporary migration help. It will go away.
-  bit guessInstructionProperties = true;
+  bit guessInstructionProperties = true; 
 
   // TableGen's instruction encoder generator has support for matching operands
   // to bit-field variables both by name and by position. While matching by
@@ -975,7 +975,7 @@ class InstrInfo {
   // This option is temporary; it will go away once the TableGen decoder
   // generator has better support for complex operands and targets have
   // migrated away from using positionally encoded operands.
-  bit decodePositionallyEncodedOperands = false;
+  bit decodePositionallyEncodedOperands = false; 
 
   // When set, this indicates that there will be no overlap between those
   // operands that are matched by ordering (positional operands) and those
@@ -984,7 +984,7 @@ class InstrInfo {
   // This option is temporary; it will go away once the TableGen decoder
   // generator has better support for complex operands and targets have
   // migrated away from using positionally encoded operands.
-  bit noNamedPositionallyEncodedOperands = false;
+  bit noNamedPositionallyEncodedOperands = false; 
 }
 
 // Standard Pseudo Instructions.
@@ -994,31 +994,31 @@ class InstrInfo {
 // targets that set guessInstructionProperties=0. Any local definition of
 // mayLoad/mayStore takes precedence over these default values.
 class StandardPseudoInstruction : Instruction {
-  let mayLoad = false;
-  let mayStore = false;
-  let isCodeGenOnly = true;
-  let isPseudo = true;
-  let hasNoSchedulingInfo = true;
+  let mayLoad = false; 
+  let mayStore = false; 
+  let isCodeGenOnly = true; 
+  let isPseudo = true; 
+  let hasNoSchedulingInfo = true; 
   let Namespace = "TargetOpcode";
 }
 def PHI : StandardPseudoInstruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins variable_ops);
   let AsmString = "PHINODE";
-  let hasSideEffects = false;
+  let hasSideEffects = false; 
 }
 def INLINEASM : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "";
-  let hasSideEffects = false;  // Note side effect is encoded in an operand.
+  let hasSideEffects = false;  // Note side effect is encoded in an operand. 
 }
 def INLINEASM_BR : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "";
   // Unlike INLINEASM, this is always treated as having side-effects.
-  let hasSideEffects = true;
+  let hasSideEffects = true; 
   // Despite potentially branching, this instruction is intentionally _not_
   // marked as a terminator or a branch.
 }
@@ -1026,177 +1026,177 @@ def CFI_INSTRUCTION : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins i32imm:$id);
   let AsmString = "";
-  let hasCtrlDep = true;
-  let hasSideEffects = false;
-  let isNotDuplicable = true;
+  let hasCtrlDep = true; 
+  let hasSideEffects = false; 
+  let isNotDuplicable = true; 
 }
 def EH_LABEL : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins i32imm:$id);
   let AsmString = "";
-  let hasCtrlDep = true;
-  let hasSideEffects = false;
-  let isNotDuplicable = true;
+  let hasCtrlDep = true; 
+  let hasSideEffects = false; 
+  let isNotDuplicable = true; 
 }
 def GC_LABEL : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins i32imm:$id);
   let AsmString = "";
-  let hasCtrlDep = true;
-  let hasSideEffects = false;
-  let isNotDuplicable = true;
+  let hasCtrlDep = true; 
+  let hasSideEffects = false; 
+  let isNotDuplicable = true; 
 }
 def ANNOTATION_LABEL : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins i32imm:$id);
   let AsmString = "";
-  let hasCtrlDep = true;
-  let hasSideEffects = false;
-  let isNotDuplicable = true;
+  let hasCtrlDep = true; 
+  let hasSideEffects = false; 
+  let isNotDuplicable = true; 
 }
 def KILL : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "";
-  let hasSideEffects = false;
+  let hasSideEffects = false; 
 }
 def EXTRACT_SUBREG : StandardPseudoInstruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
   let AsmString = "";
-  let hasSideEffects = false;
+  let hasSideEffects = false; 
 }
 def INSERT_SUBREG : StandardPseudoInstruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
   let AsmString = "";
-  let hasSideEffects = false;
+  let hasSideEffects = false; 
   let Constraints = "$supersrc = $dst";
 }
 def IMPLICIT_DEF : StandardPseudoInstruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins);
   let AsmString = "";
-  let hasSideEffects = false;
-  let isReMaterializable = true;
-  let isAsCheapAsAMove = true;
+  let hasSideEffects = false; 
+  let isReMaterializable = true; 
+  let isAsCheapAsAMove = true; 
 }
 def SUBREG_TO_REG : StandardPseudoInstruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
   let AsmString = "";
-  let hasSideEffects = false;
+  let hasSideEffects = false; 
 }
 def COPY_TO_REGCLASS : StandardPseudoInstruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins unknown:$src, i32imm:$regclass);
   let AsmString = "";
-  let hasSideEffects = false;
-  let isAsCheapAsAMove = true;
+  let hasSideEffects = false; 
+  let isAsCheapAsAMove = true; 
 }
 def DBG_VALUE : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "DBG_VALUE";
-  let hasSideEffects = false;
-}
-def DBG_INSTR_REF : StandardPseudoInstruction {
-  let OutOperandList = (outs);
-  let InOperandList = (ins variable_ops);
-  let AsmString = "DBG_INSTR_REF";
-  let hasSideEffects = false;
-}
+  let hasSideEffects = false; 
+}
+def DBG_INSTR_REF : StandardPseudoInstruction { 
+  let OutOperandList = (outs); 
+  let InOperandList = (ins variable_ops); 
+  let AsmString = "DBG_INSTR_REF"; 
+  let hasSideEffects = false; 
+} 
 def DBG_LABEL : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins unknown:$label);
   let AsmString = "DBG_LABEL";
-  let hasSideEffects = false;
+  let hasSideEffects = false; 
 }
 def REG_SEQUENCE : StandardPseudoInstruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins unknown:$supersrc, variable_ops);
   let AsmString = "";
-  let hasSideEffects = false;
-  let isAsCheapAsAMove = true;
+  let hasSideEffects = false; 
+  let isAsCheapAsAMove = true; 
 }
 def COPY : StandardPseudoInstruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins unknown:$src);
   let AsmString = "";
-  let hasSideEffects = false;
-  let isAsCheapAsAMove = true;
-  let hasNoSchedulingInfo = false;
+  let hasSideEffects = false; 
+  let isAsCheapAsAMove = true; 
+  let hasNoSchedulingInfo = false; 
 }
 def BUNDLE : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "BUNDLE";
-  let hasSideEffects = false;
+  let hasSideEffects = false; 
 }
 def LIFETIME_START : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins i32imm:$id);
   let AsmString = "LIFETIME_START";
-  let hasSideEffects = false;
+  let hasSideEffects = false; 
 }
 def LIFETIME_END : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins i32imm:$id);
   let AsmString = "LIFETIME_END";
-  let hasSideEffects = false;
-}
-def PSEUDO_PROBE : StandardPseudoInstruction {
-  let OutOperandList = (outs);
-  let InOperandList = (ins i64imm:$guid, i64imm:$index, i8imm:$type, i32imm:$attr);
-  let AsmString = "PSEUDO_PROBE";
-  let hasSideEffects = 1;
-}
-
+  let hasSideEffects = false; 
+}
+def PSEUDO_PROBE : StandardPseudoInstruction { 
+  let OutOperandList = (outs); 
+  let InOperandList = (ins i64imm:$guid, i64imm:$index, i8imm:$type, i32imm:$attr); 
+  let AsmString = "PSEUDO_PROBE"; 
+  let hasSideEffects = 1; 
+} 
+ 
 def STACKMAP : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops);
-  let hasSideEffects = true;
-  let isCall = true;
-  let mayLoad = true;
-  let usesCustomInserter = true;
+  let hasSideEffects = true; 
+  let isCall = true; 
+  let mayLoad = true; 
+  let usesCustomInserter = true; 
 }
 def PATCHPOINT : StandardPseudoInstruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee,
                        i32imm:$nargs, i32imm:$cc, variable_ops);
-  let hasSideEffects = true;
-  let isCall = true;
-  let mayLoad = true;
-  let usesCustomInserter = true;
+  let hasSideEffects = true; 
+  let isCall = true; 
+  let mayLoad = true; 
+  let usesCustomInserter = true; 
 }
 def STATEPOINT : StandardPseudoInstruction {
-  let OutOperandList = (outs variable_ops);
+  let OutOperandList = (outs variable_ops); 
   let InOperandList = (ins variable_ops);
-  let usesCustomInserter = true;
-  let mayLoad = true;
-  let mayStore = true;
-  let hasSideEffects = true;
-  let isCall = true;
+  let usesCustomInserter = true; 
+  let mayLoad = true; 
+  let mayStore = true; 
+  let hasSideEffects = true; 
+  let isCall = true; 
 }
 def LOAD_STACK_GUARD : StandardPseudoInstruction {
   let OutOperandList = (outs ptr_rc:$dst);
   let InOperandList = (ins);
-  let mayLoad = true;
-  bit isReMaterializable = true;
-  let hasSideEffects = false;
-  bit isPseudo = true;
+  let mayLoad = true; 
+  bit isReMaterializable = true; 
+  let hasSideEffects = false; 
+  bit isPseudo = true; 
 }
 def PREALLOCATED_SETUP : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins i32imm:$a);
-  let usesCustomInserter = true;
-  let hasSideEffects = true;
+  let usesCustomInserter = true; 
+  let hasSideEffects = true; 
 }
 def PREALLOCATED_ARG : StandardPseudoInstruction {
   let OutOperandList = (outs ptr_rc:$loc);
   let InOperandList = (ins i32imm:$a, i32imm:$b);
-  let usesCustomInserter = true;
-  let hasSideEffects = true;
+  let usesCustomInserter = true; 
+  let hasSideEffects = true; 
 }
 def LOCAL_ESCAPE : StandardPseudoInstruction {
   // This instruction is really just a label. It has to be part of the chain so
@@ -1204,94 +1204,94 @@ def LOCAL_ESCAPE : StandardPseudoInstruction {
   // no side effects.
   let OutOperandList = (outs);
   let InOperandList = (ins ptr_rc:$symbol, i32imm:$id);
-  let hasSideEffects = false;
-  let hasCtrlDep = true;
+  let hasSideEffects = false; 
+  let hasCtrlDep = true; 
 }
 def FAULTING_OP : StandardPseudoInstruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins variable_ops);
-  let usesCustomInserter = true;
-  let hasSideEffects = true;
-  let mayLoad = true;
-  let mayStore = true;
-  let isTerminator = true;
-  let isBranch = true;
+  let usesCustomInserter = true; 
+  let hasSideEffects = true; 
+  let mayLoad = true; 
+  let mayStore = true; 
+  let isTerminator = true; 
+  let isBranch = true; 
 }
 def PATCHABLE_OP : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
-  let usesCustomInserter = true;
-  let mayLoad = true;
-  let mayStore = true;
-  let hasSideEffects = true;
+  let usesCustomInserter = true; 
+  let mayLoad = true; 
+  let mayStore = true; 
+  let hasSideEffects = true; 
 }
 def PATCHABLE_FUNCTION_ENTER : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins);
   let AsmString = "# XRay Function Enter.";
-  let usesCustomInserter = true;
-  let hasSideEffects = true;
+  let usesCustomInserter = true; 
+  let hasSideEffects = true; 
 }
 def PATCHABLE_RET : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "# XRay Function Patchable RET.";
-  let usesCustomInserter = true;
-  let hasSideEffects = true;
-  let isTerminator = true;
-  let isReturn = true;
+  let usesCustomInserter = true; 
+  let hasSideEffects = true; 
+  let isTerminator = true; 
+  let isReturn = true; 
 }
 def PATCHABLE_FUNCTION_EXIT : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins);
   let AsmString = "# XRay Function Exit.";
-  let usesCustomInserter = true;
-  let hasSideEffects = true;
-  let isReturn = false; // Original return instruction will follow
+  let usesCustomInserter = true; 
+  let hasSideEffects = true; 
+  let isReturn = false; // Original return instruction will follow 
 }
 def PATCHABLE_TAIL_CALL : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "# XRay Tail Call Exit.";
-  let usesCustomInserter = true;
-  let hasSideEffects = true;
-  let isReturn = true;
+  let usesCustomInserter = true; 
+  let hasSideEffects = true; 
+  let isReturn = true; 
 }
 def PATCHABLE_EVENT_CALL : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins ptr_rc:$event, unknown:$size);
   let AsmString = "# XRay Custom Event Log.";
-  let usesCustomInserter = true;
-  let isCall = true;
-  let mayLoad = true;
-  let mayStore = true;
-  let hasSideEffects = true;
+  let usesCustomInserter = true; 
+  let isCall = true; 
+  let mayLoad = true; 
+  let mayStore = true; 
+  let hasSideEffects = true; 
 }
 def PATCHABLE_TYPED_EVENT_CALL : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins unknown:$type, ptr_rc:$event, unknown:$size);
   let AsmString = "# XRay Typed Event Log.";
-  let usesCustomInserter = true;
-  let isCall = true;
-  let mayLoad = true;
-  let mayStore = true;
-  let hasSideEffects = true;
+  let usesCustomInserter = true; 
+  let isCall = true; 
+  let mayLoad = true; 
+  let mayStore = true; 
+  let hasSideEffects = true; 
 }
 def FENTRY_CALL : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins);
   let AsmString = "# FEntry call";
-  let usesCustomInserter = true;
-  let isCall = true;
-  let mayLoad = true;
-  let mayStore = true;
-  let hasSideEffects = true;
+  let usesCustomInserter = true; 
+  let isCall = true; 
+  let mayLoad = true; 
+  let mayStore = true; 
+  let hasSideEffects = true; 
 }
 def ICALL_BRANCH_FUNNEL : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "";
-  let hasSideEffects = true;
+  let hasSideEffects = true; 
 }
 
 // Generic opcodes used in GlobalISel.
@@ -1317,7 +1317,7 @@ class AsmParser {
 
   // ShouldEmitMatchRegisterName - Set to false if the target needs a hand
   // written register name matcher
-  bit ShouldEmitMatchRegisterName = true;
+  bit ShouldEmitMatchRegisterName = true; 
 
   // Set to true if the target needs a generated 'alternative register name'
   // matcher.
@@ -1325,7 +1325,7 @@ class AsmParser {
   // This generates a function which can be used to lookup registers from
   // their aliases. This function will fail when called on targets where
   // several registers share the same alias (i.e. not a 1:1 mapping).
-  bit ShouldEmitMatchRegisterAltName = false;
+  bit ShouldEmitMatchRegisterAltName = false; 
 
   // Set to true if MatchRegisterName and MatchRegisterAltName functions
   // should be generated even if there are duplicate register names. The
@@ -1333,11 +1333,11 @@ class AsmParser {
   // (e.g. in validateTargetOperandClass), and there are no guarantees about
   // which numeric register identifier will be returned in the case of
   // multiple matches.
-  bit AllowDuplicateRegisterNames = false;
+  bit AllowDuplicateRegisterNames = false; 
 
   // HasMnemonicFirst - Set to false if target instructions don't always
   // start with a mnemonic as the first token.
-  bit HasMnemonicFirst = true;
+  bit HasMnemonicFirst = true; 
 
   // ReportMultipleNearMisses -
   // When 0, the assembly matcher reports an error for one encoding or operand
@@ -1345,7 +1345,7 @@ class AsmParser {
   // When 1, the assembly matcher returns a list of encodings that were close
   // to matching the parsed instruction, so to allow more detailed error
   // messages.
-  bit ReportMultipleNearMisses = false;
+  bit ReportMultipleNearMisses = false; 
 }
 def DefaultAsmParser : AsmParser;
 
@@ -1356,7 +1356,7 @@ def DefaultAsmParser : AsmParser;
 //
 class AsmParserVariant {
   // Variant - AsmParsers can be of multiple different variants.  Variants are
-  // used to support targets that need to parse multiple formats for the
+  // used to support targets that need to parse multiple formats for the 
   // assembly language.
   int Variant = 0;
 
@@ -1392,7 +1392,7 @@ def all_of;
 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
 /// matches instructions and aliases.
 class AssemblerPredicate<dag cond, string name = ""> {
-  bit AssemblerMatcherPredicate = true;
+  bit AssemblerMatcherPredicate = true; 
   dag AssemblerCondDag = cond;
   string PredicateName = name;
 }
@@ -1467,7 +1467,7 @@ class InstAlias<string Asm, dag Result, int Emit = 1, string VariantName = ""> {
   // Setting this to 0 will cause the alias to ignore the Result instruction's
   // defined AsmMatchConverter and instead use the function generated by the
   // dag Result.
-  bit UseInstAsmMatchConverter = true;
+  bit UseInstAsmMatchConverter = true; 
 
   // Assembler variant name to use for this alias. If not specified then
   // assembler variants will be determined based on AsmString
@@ -1572,8 +1572,8 @@ class ComplexDeprecationPredicate<string dep> {
 // by the scheduler.  Each Processor definition requires corresponding
 // instruction itineraries.
 //
-class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f,
-                list<SubtargetFeature> tunef = []> {
+class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f, 
+                list<SubtargetFeature> tunef = []> { 
   // Name - Chip set name.  Used by command line (-mcpu=) to determine the
   // appropriate target chip.
   //
@@ -1589,12 +1589,12 @@ class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f,
 
   // Features - list of
   list<SubtargetFeature> Features = f;
-
-  // TuneFeatures - list of features for tuning for this CPU. If the target
-  // supports -mtune, this should contain the list of features used to make
-  // microarchitectural optimization decisions for a given processor.  While
-  // Features should contain the architectural features for the processor.
-  list<SubtargetFeature> TuneFeatures = tunef;
+ 
+  // TuneFeatures - list of features for tuning for this CPU. If the target 
+  // supports -mtune, this should contain the list of features used to make 
+  // microarchitectural optimization decisions for a given processor.  While 
+  // Features should contain the architectural features for the processor. 
+  list<SubtargetFeature> TuneFeatures = tunef; 
 }
 
 // ProcessorModel allows subtargets to specify the more general
@@ -1603,9 +1603,9 @@ class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f,
 //
 // Although this class always passes NoItineraries to the Processor
 // class, the SchedMachineModel may still define valid Itineraries.
-class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f,
-                     list<SubtargetFeature> tunef = []>
-  : Processor<n, NoItineraries, f, tunef> {
+class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f, 
+                     list<SubtargetFeature> tunef = []> 
+  : Processor<n, NoItineraries, f, tunef> { 
   let SchedModel = m;
 }